A PCB layout structure and design method for injecting crosstalk noise

Abstract

The present application relates to the technical field of printed circuit boards, and discloses a PCB layout structure and design method for injecting crosstalk noise. The PCB layout structure includes a pair of differential victim lines and multiple pairs of differential attack lines. In the transmission direction of the victim line, it includes an input area, an S-shaped winding area, a straight transmission area, and an output area. The multiple pairs of attack lines are divided into two groups and symmetrically distributed on both sides of the straight transmission area, and there are multiple coupling areas on the straight transmission area; in the transmission direction of the attack line, it includes an input layout area, a coupling area, and an output layout area, and some also have an attack line layer change via area. The design method includes PCB stacking design, PCB layout design, three-dimensional electromagnetic simulation, time domain noise calculation and PCB layout finalization. The layout structure has extremely high test freedom, can select the intensity and attack mode of injected crosstalk noise, has compact layout and wiring, low board manufacturing cost, strong robustness, and high test stability.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit boards (PCBs), and more specifically to a PCB layout structure and design method for injecting crosstalk noise. Background Art

[0002] With the in-depth development of technologies such as artificial intelligence and big data, people's demand for data transmission rate continues to increase, and high-speed serial interface (SerDes) technology is gradually replacing traditional parallel data transmission technology. Different from the traditional parallel data transmission method in which clocks and signals are transmitted in two paths, the high-speed serial interface directly adopts the differential signal transmission method. While expanding the channel bandwidth, it is necessary to greatly optimize the signal-to-noise ratio to achieve data transmission at a rate of gigabit or above. At present, high-speed serial interface technology has been widely used in various application scenarios that require the transmission of large amounts of data, such as optical modules, boards, switches, servers, data centers, supercomputing centers, intelligent driving, virtual reality, etc.

[0003] However, the rapid increase in data transmission rate means that the signal rises faster and faster, which also means that the transmission link needs to support more bandwidth. Considering that optical fiber has many advantages over PCB, such as lower loss, more bandwidth, lighter weight, and better isolation, optical fiber is currently used as the main transmission medium for large data transmission over a distance of tens of meters or more. However, the complex functions of transmitting, receiving, processing, and judging electrical signals are all completed on electrical chips. The optical module integrates core components such as SerDes interface chips and optical transmitter and receiver components. It can convert the electrical signal at the transmitting end into an optical signal and restore the optical signal at the receiving end into an electrical signal. It cleverly acts as a medium for optical / electrical signal conversion, making optical fiber transmission of big data a practical and usable technology. Inside the optical module, SerDes interface chips, optical transmitter and receiver components, power supply modules, resistor and capacitor components, etc. are mainly interconnected through PCB as a carrier. In the communications industry, upstream manufacturers as chip suppliers need to provide certain forms of PCB design index constraints for their own developed chips to facilitate downstream manufacturers to reasonably design PCBs and allow the overall function of the integrated system to operate normally.

[0004] In order to ensure that the SerDes interface chip can achieve low bit error rate transmission, it is necessary to put forward certain signal integrity requirements for the PCB environment where the SerDes interface chip is located, including but not limited to transmission coefficient, reflection coefficient, crosstalk noise, etc. Among them, the control of transmission coefficient is mainly achieved by selecting boards with lower dielectric constant (DK) and dielectric loss (DF) and copper foil with smaller roughness; the control of reflection coefficient is mainly achieved by optimizing the degree of impedance discontinuity such as vias and pads.

[0005] However, in order to achieve high-density multi-channel high-speed serial interface chip transceiver interconnection within a limited PCB layout size (especially the extremely compact and narrow PCB layout size of optical modules), it is impossible to achieve perfect isolation between channels, and a certain degree of crosstalk noise will inevitably be generated. As the signal rate is almost doubling in accordance with Moore's Law, the crosstalk noise shows a significant trend of strengthening in the frequency domain. It is particularly important to know how much crosstalk noise the high-density multi-channel high-speed serial interface chip can withstand. This is related to the indicator constraints of the corresponding PCB design of the chip, and can also be used as an important reference indicator for comparing the performance differences of interface chips from different manufacturers.

[0006] Traditional crosstalk test boards have low degrees of freedom and cannot freely inject the intensity of crosstalk noise and the number of attack lines; the test board area is large, the layout is not compact, and the manufacturing cost is high; it mainly relies on the spatial electromagnetic field coupling of the connector. This crosstalk coupling method is related to the tightness of the connector when it is plugged in and out, and the robustness of repeated tests is low. Summary of the invention

[0007] The purpose of the present application is to provide a PCB layout structure and design method for injecting crosstalk noise. The layout structure has a very high degree of testing freedom, allowing testers to freely choose the intensity and attack method of the injected crosstalk noise.

[0008] The present application discloses a PCB layout structure for injecting crosstalk noise, comprising: a pair of differential victim lines and multiple pairs of differential attack lines, wherein:

[0009] In the transmission direction of the victim line, the differential signal input area, the S-shaped winding area, the straight transmission area, and the differential signal output area of ​​the victim line are sequentially included, the multiple pairs of attack lines are divided into two groups and symmetrically distributed on both sides of the straight transmission area, wherein the straight transmission area has multiple coupling areas respectively coupled with the multiple pairs of attack lines;

[0010] In the transmission direction of the attack line, the attack line input layout area, the coupling area, and the attack line output layout area are sequentially included, wherein one or more pairs of the multiple pairs of attack lines further have an attack line layer-changing via area before coupling with the pair of victim lines;

[0011] Among them, the signal used for testing enters the victim line from the differential signal input area of ​​the victim line, passes through the S-shaped winding area of ​​the victim line with adjustable length to meet the requirements of different transmission coefficients of the victim line, passes through the coupling area of ​​the attack line and the victim line to simulate the addition of various complex crosstalk noises, and is output from the differential signal output area of ​​the victim line and connected to a high-density multi-channel high-speed serial interface chip.

[0012] In a preferred example, the PCB layout structure is composed of a pair of differential victim lines and eight pairs of differential attack lines, the line width of the differential lines is 6 mil, and the line spacing between the differential lines is 12 mil.

[0013] In a preferred embodiment, the differential signal input area of ​​the victim line and the differential signal output area of ​​the victim line both use two SMA connectors with an inner diameter of 1.85 mm as coaxial signal input and output;

[0014] The input layout area of ​​the attack line and the output layout area of ​​the attack line select an 8-channel integrated cable assembly.

[0015] In a preferred example, the attack line layer change via area includes a via, wherein the via stub of the via is no greater than 5 mil to support at least 112G bps PAM4 signals, and the via stub of the via is no greater than 3 mil to support 224G bps PAM4 signals.

[0016] In a preferred example, the attack line layer change via area further includes a plurality of companion ground holes located around the via hole, and the companion ground holes are connected to the ground terminals of other layers in the PCB layout structure.

[0017] In a preferred example, the bending radius of the S-shaped winding region of the victim line is at least twenty times the line width of the differential victim line, and the length of the victim line in the S-shaped winding region of the victim line ranges from 10 inches to 25 inches.

[0018] In a preferred example, in the coupling region between the attack line and the victim line, the distance between the victim line and the attack line is 1 times the line width of the differential victim line.

[0019] In a preferred example, the input layout area and the output layout area corresponding to a group of attack lines are located on the same side of the straight transmission area of ​​the victim line and away from the coupling area, wherein each pair of attack lines respectively reaches the corresponding output layout area of ​​the attack line from the input layout area of ​​the attack line through multiple bends.

[0020] The present application also discloses a design method for a PCB layout structure for injecting crosstalk noise, including:

[0021] Step 101, performing PCB stackup design, and determining a PCB stackup consisting of a pair of differential victim lines and multiple pairs of differential attack lines;

[0022] Step 102, performing initial PCB layout design;

[0023] Step 103, performing three-dimensional electromagnetic simulation to extract S parameters, wherein the S parameters are used to describe the coupling relationship between the plurality of pairs of differential attack lines and the pair of differential victim lines;

[0024] Step 104, performing time domain noise simulation calculation;

[0025] Step 105, modifying the initial PCB layout design according to the trend of the time domain noise simulation, and iterating until the time domain noise meets the target requirement.

[0026] In a preferred embodiment, the time domain noise calculation method of step 104 is as follows:

[0027] Step 201, first calculate the unit impulse response of a pair of attack lines to the victim line, then calculate the time domain noise caused by the pair of attack lines through the convolution of a series of unit impulse responses, and use the root mean square to measure the size of the time domain noise of the pair of attack lines to the victim line;

[0028] Step 202, calculating the time domain noise magnitude of other pairs of attack lines to the victim line;

[0029] Step 203: The effective noise power finally superimposed on the victim line is obtained by accumulating the squares of the time domain noise of each pair of attacking lines.

[0030] Compared with the prior art, the main differences and effects of the embodiments of the present application are:

[0031] In the implementation manner of the present application, the PCB layout structure has an extremely high degree of testing freedom, allowing testers to freely select the intensity and attack mode of injected crosstalk noise.

[0032] Furthermore, the PCB layout structure uses integrated cable components and S-type winding, etc., which has compact layout and wiring and low board manufacturing cost.

[0033] Furthermore, the key local structure for coupling the attack line and the victim line is on the same layer. Considering the process deviation of PCB processing, the design method of coupling the attack line and the victim line has strong robustness and high test stability.

[0034] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 is a schematic diagram of a PCB layout structure for injecting crosstalk noise according to an embodiment of the present application;

[0037] Figure 2 is a schematic diagram of an S-shaped winding area of ​​a PCB layout structure according to an embodiment of the present application;

[0038] Figure 3 is a schematic diagram of the coupling area between the attacking line and the victim line of the PCB layout structure according to one embodiment of the present application;

[0039] Figure 4 is a schematic diagram of an input / output layout area of ​​an attack line of a PCB layout structure in one embodiment of the present application;

[0040] Figure 5 is a schematic diagram of attack lines and layer-changing via areas of different layers according to an embodiment of the present application;

[0041] Figure 6 It is a schematic diagram of the design process of a PCB layout for injecting crosstalk noise according to one embodiment of the present application;

[0042] Figure 7It is a schematic diagram of the steps of calculating crosstalk noise in the design process of PCB layout in one embodiment of the present application.

[0043] In the accompanying drawings, the symbols are as follows:

[0044] 1- Differential signal input area of ​​the victim line;

[0045] 2- differential signal output area of ​​the victim line;

[0046] 3-S-type winding area;

[0047] 4- coupling region;

[0048] 401-first coupling region;

[0049] 402-second coupling region;

[0050] 403-third coupling region;

[0051] 404- fourth coupling region;

[0052] 5- Input layout area of ​​the attack line;

[0053] 501.1 to 501.4 – the first set of 4 differential attack lines;

[0054] 502.1~502.4-the second group of 4 pairs of differential attack lines;

[0055] 6- Output layout area of ​​the attack line;

[0056] 7- Attack line layer change via area;

[0057] 8- Straight-line transmission area;

[0058] 9- Winding DETAILED DESCRIPTION

[0059] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0060] Description of some concepts:

[0061] Printed Circuit Board (PCB): Also known as printed circuit board, it is an important electronic component, a support for electronic components, and a carrier for the electrical connection of electronic components. Because it is made using electronic printing technology, it is called a "printed" circuit board.

[0062] Serial Deserializer (SerDes): It is the abbreviation of SERializer / DESerializer in English. It is a mainstream time division multiplexing (TDM) and point-to-point (P2P) serial communication technology. That is, multiple low-speed parallel signals are converted into high-speed serial signals at the sending end, and then passed through the transmission media (optical cable or copper wire), and finally the high-speed serial signals are converted back into low-speed parallel signals at the receiving end. This point-to-point serial communication technology makes full use of the channel capacity of the transmission media, reduces the number of transmission channels and device pins required, and improves the transmission speed of the signal, thereby greatly reducing the communication cost.

[0063] Optical module: It is composed of optoelectronic devices, functional circuits and optical interfaces. The optoelectronic devices include transmitting and receiving parts. Simply put, the function of the optical module is to convert the electrical signal into an optical signal at the transmitting end. After being transmitted through the optical fiber, the receiving end converts the optical signal into an electrical signal.

[0064] Differential signal: Differential signal transmission is a signal transmission technology. Different from the traditional single-ended signal transmission with one signal line and one ground line, differential transmission transmits signals on both lines. The two signals have the same amplitude and opposite phase. The signal transmitted on these two lines is a differential signal. The advantage of differential transmission is that it has strong anti-interference ability. When there is external noise interference, it will almost be coupled to the two signal lines at the same time, and the receiving end only cares about the difference between the two signals, so the external common-mode noise can be completely offset.

[0065] Via: PCB via refers to the hole on the printed circuit board, which is used to connect the electrical signal or power between different layers. It consists of the hole, the pad area around the hole and the power layer isolation area, and can usually be divided into three categories: blind via, buried via and through hole.

[0066] Via stub: The unused portion of a via.

[0067] SMA connector: SMA connector is a bayonet connector, commonly used in RF circuits with 50Ω impedance. It is one of the most common coaxial connectors in the RF, microwave and millimeter wave (mmW) industries. SMA connector is called Subminiature Version A connector, which is a miniature A version connector with an outer diameter of about 6mm.

[0068] PAM4 signal: PAM4 signal is a line coding using pulse amplitude modulation technology, which has four voltage levels, and each amplitude level corresponds to the logical bits 00, 01, 10 and 11. In other words, each symbol of PAM4 encoding consists of 2 bits, which correspond to a voltage level, that is, amplitude.

[0069] Back drilling process: Back drilling process is a technology used in PCB production. It can remove the stub hole wall of connector vias or signal vias by controlling the depth of drilling to promote signal flow between different layers of the circuit board without interference from unwanted stubs.

[0070] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0071] This application discloses a PCB layout structure for injecting crosstalk noise, and its structure is referenced Figure 1 As shown, it includes: a pair of differential victim lines and multiple pairs of differential attack lines. Wherein: in the transmission direction of the victim line, it includes the differential signal input area 1 of the victim line, the S-shaped winding area 3, the straight transmission area 8, and the differential signal output area 2 of the victim line in sequence, and the multiple pairs of attack lines are divided into two groups and symmetrically distributed on both sides of the straight transmission area 8, wherein the straight transmission area 8 has multiple coupling areas 4 respectively coupled with the multiple pairs of attack lines. In the transmission direction of the attack line, it includes the input layout area 5 of the attack line, the above-mentioned coupling area 4, and the output layout area 6 of the attack line in sequence. Wherein, one or more pairs of the multiple pairs of attack lines also have an attack line layer change via area 7 before coupling with a pair of victim lines.

[0072] The term "transmission direction of the victim line" in this specification can be understood as the direction from the input area 1 of the victim line to the output area 2. The term "transmission direction of the attack line" can be understood as the direction from the input layout area 5 to the output layout area 6 of the attack line.

[0073] Among them, the signal used for testing enters the victim line from the differential signal input area of ​​the victim line, passes through the S-shaped winding area 3 of the victim line with adjustable length to meet the requirements of different transmission coefficients of the victim line, passes through the coupling areas 401 to 404 of the attack line and the victim line to simulate the addition of various complex crosstalk noises, and is output from the differential signal output area 2 of the victim line and connected to the high-density multi-channel high-speed serial interface chip.

[0074] The high-density multi-channel high-speed serial interface chip is a chip whose performance needs to be tested, and the test signal with added noise is used to complete the function of testing and evaluating the tolerance of the high-density multi-channel high-speed serial interface chip to crosstalk noise. Among them, the high-density multi-channel high-speed serial interface chip can be an optical module chip.

[0075] like Figure 1The structure shown in the PCB layout structure is illustrated by taking a pair of differential victim lines and eight pairs of differential attack lines as an example. The line width of the differential line is 6 mils, and the line spacing between the differential lines is 12 mils. It should be understood that the line width and line spacing of the differential line can be set as required and are not limited to the above values. For example, the line width of the differential line can also be 5mil, 7mil, 8mil, etc., and the line spacing between the differential lines can also be 10mil, 13mil, 15mil, 16mil, etc., and the present invention is not limited to this. In this embodiment, there are 4 pairs of differential attack lines on both sides of the victim line, and there are 4 coupling areas 401, 402, 403, and 404. The two symmetrical pairs of attack lines are coupled at symmetrical positions on both sides of the victim line to form a coupling area 4.

[0076] In one embodiment, the differential signal input region 1 of the victim line and the differential signal output region 2 of the victim line both use two SMA connectors with an inner diameter of 1.85 mm as coaxial signal input and output.

[0077] In one embodiment, the attack line input layout area 5 and the attack line output layout area 6 use an 8-channel integrated cable assembly, which can greatly reduce the PCB layout space compared to the SMA connector.

[0078] Figure 5 Schematic diagram of attack line and layer change via area of ​​different layers according to one embodiment of the present application. In one embodiment, the attack line layer change via area 7 includes vias, wherein the via stub of the via is no more than 5 mil to support at least 112G bps PAM4 signal, and the via stub of the via is no more than 3 mil to support 224G bps PAM4 signal. In this embodiment, the PCB layout adopts a back drilling process to reduce the impact of the via stub on the high-speed signal.

[0079] In one embodiment, the attack line layer change via area 7 also includes a plurality of companion ground holes located around the via holes, which are connected to the ground terminals of other layers in the PCB layout structure to provide the shortest return path for the layer-changing high-speed line.

[0080] Figure 2 It is a schematic diagram of the S-shaped winding area of ​​the PCB layout structure in one embodiment of the present application. In one embodiment, the bending radius of the S-shaped winding area 3 of the victim line is at least twenty times the line width of the differential victim line, and the length of the victim line in the S-shaped winding area 3 of the victim line ranges from 10 inches to 25 inches. It should be understood that the winding can be 10 inches, 15 inches, 20 inches, 25 inches and other different lengths to meet the needs of application scenarios with different transmission coefficients of the victim line.

[0081] Figure 3 Schematic diagram of the coupling area of ​​the attack line and the victim line of the PCB layout structure in one embodiment of the present application. In one embodiment, in the coupling area 401, 402, 403, 404 of the attack line and the victim line, the distance between the victim line and the attack line is 1 times the line width of the differential victim line. It should be noted that in the coupling area 401, 402, 403, 404, the distance between the victim line and the attack line can also be set to 1.5 times, 2 times, 2.5 times, etc., the line width of the differential line. Different distances between the victim line and the attack line can be used to adjust different additions of different types of complex crosstalk noise.

[0082] In one embodiment, the input layout area 501 of a group of attack lines and the output layout area 601 of the attack lines are located on the same side of the straight transmission area 8 of the victim line and away from the coupling areas 401, 402, 403, and 404. The input layout area 502 of another group of attack lines and the output layout area 602 of the attack lines are located on the other side of the straight transmission area 8 of the victim line and away from the coupling areas 401, 402, 403, and 404. Each pair of multiple pairs of attack lines respectively reaches the output layout area 6 of the corresponding attack line from the input layout area 5 of the attack line after multiple bends. In the process of bending the attack line, windings 9 of different lengths are also formed, mainly to control the noise intensity of each pair of attack lines reaching the output area of ​​the victim line to be equal or close. Therefore, the length of the winding needs to be fine-tuned according to the size of the simulated noise. Among them, the input layout area 5 and the output layout area 6 can be swapped with each other, which is equivalent to changing the attack direction of the attack line on the victim line.

[0083] In this embodiment, if Figure 1 As shown, in the transmission direction of the victim line, four coupling areas 401, 402, 403, and 404 are arranged in sequence, and in each coupling area 401, 402, 403, and 404, the coupling lengths of the victim line and the attack line are the same, the input layout area 5 of the attack line and the output layout area 6 of the attack line are at the same distance from the victim line, the input layout area 501 of the first attack line and the output layout area 601 of the first attack line are both on one side of the victim line and are aligned, and the input layout area 502 of the second attack line and the output layout area 602 of the second attack line are both on the other side of the victim line and are aligned. The first group of 4 pairs of differential attack lines 501.1, 501.2, 501.3, and 501.4 are input from the input layout area 501 of the first attack line and output from the output layout area 601 of the first attack line, and the second group of 4 pairs of differential attack lines 502.1, 502.2, 502.3, and 502.4 are input from the input layout area 502 of the second attack line and output from the output layout area 602 of the second attack line. Figure 4 It is a schematic diagram of the input / output layout area of ​​the attack line of the PCB layout structure in one embodiment of the present application.

[0084] In this specific embodiment, to simplify the expression, within the coupling regions 401, 402, 403, and 404, the transmission direction of the victim line is described as being to the left, the reverse direction of the transmission direction of the victim line is described as being to the right, the direction perpendicular to the transmission direction of the victim line and toward the victim line on the right side of the victim line is described as being downward, the direction perpendicular to the transmission direction of the victim line and away from the victim line on the right side of the victim line is described as being upward, the direction perpendicular to the transmission direction of the victim line and toward the victim line on the left side of the victim line is described as being upward, and the direction perpendicular to the transmission direction of the victim line and away from the victim line on the left side of the victim line is described as being downward.

[0085] The first group of four pairs of differential attack lines 501.1, 501.2, 501.3, and 501.4 are arranged in parallel in the input layout area 501 of the first attack line, with the same direction and all pointing downward. The first pair of differential attack lines 501.1 successively bends 90 degrees to the right, 90 degrees downward, and 90 degrees to the right to reach the first coupling area 401 farthest from the input layout area 501 of the first attack line. Then, the first pair of differential attack lines 501.1 bends 90 degrees upward, once winding, 90 degrees to the left, and 90 degrees upward to reach the output layout area 601 of the first attack line. The second pair of differential attack lines 501.2 successively bends 90 degrees to the right, 90 degrees downward, and 90 degrees to the right to reach the relatively central second coupling area 402. The second pair of differential attack lines 501.2 bends 90 degrees upward, once winding, and reaches the output layout area 601 of the first attack line. The third pair of differential attack lines 501.3 successively bend 90 degrees to the right to reach the third coupling region 403 closest to the input layout region 501 of the first attack line, and the third pair of differential attack lines 501.3 bend 90 degrees upward, once winding, 90 degrees to the right, and 90 degrees upward to reach the output layout region 601 of the first attack line. The fourth pair of differential attack lines 501.4 successively bend 90 degrees to the left, 90 degrees downward, and 90 degrees to the right to reach the fourth coupling region 404 closest to the victim line output region 2. The fourth pair of differential attack lines 501.4 bend 90 degrees upward, 90 degrees to the right, and 90 degrees upward to reach the output layout region 601 of the first attack line, and are in the output layout region 601 of the first attack line.

[0086] The first group of four pairs of differential attack lines 501.1, 501.2, 501.3, 501.4 are in the coupling region 4, with the same direction and all pointing to the right. The first group of four pairs of differential attack lines 501.1, 501.2, 501.3, 501.4 are arranged in parallel in the output region 6, with the same direction and all pointing upward.

[0087] The second group of 4 pairs of differential attack lines are on the left side of the victim line, and their structure is symmetrical with that of the first group of 4 pairs of differential attack lines, so they will not be elaborated here.

[0088] The tester can select different attack modes by choosing to have the attack line attack one side of the victim line, choosing to have the attack line attack both sides of the victim line, choosing to change the attack direction of the attack line on the victim line, and choosing one or more pairs of attack lines to attack the victim line.

[0089] The tester can adjust the strength of the injected crosstalk noise by adjusting the attack line input signal strength and the number of attack lines, the coupling distance between the attack line and the victim line, and the coupling length. The strength of the injected noise is the size of the noise signal coupled from the attack line to the victim line. When multiple attack lines attack the victim line at the same time, the noise on the victim line is incoherent noise, and the total crosstalk noise satisfies the superposition of the noise power of each line.

[0090] The present application also discloses a design method for a PCB layout structure for injecting crosstalk noise, and its flow chart is as follows: Figure 6 As shown, the steps of the method include: PCB stacking design, PCB layout design, three-dimensional electromagnetic simulation, time domain noise calculation and PCB layout finalization.

[0091] Step 101, perform PCB stackup design to determine a PCB stackup consisting of a pair of differential victim lines and multiple pairs of differential attack lines; the stackup can be a multi-layer board, supporting a pair of victim lines and multiple pairs of attack lines, the board can be selected from extremely low-loss M6, glass cloth is selected to reduce the influence of glass fiber effect, and HVLP grade copper foil is selected for inner layer routing.

[0092] Step 102, perform initial PCB layout design.

[0093] Step 103 , performing three-dimensional electromagnetic simulation to extract S parameters, where the S parameters are used to describe the coupling relationship between multiple pairs of differential attack lines and one pair of differential victim lines.

[0094] Step 104, performing time domain noise simulation calculation.

[0095] Step 105, modify the initial PCB layout design according to the trend of the time domain noise simulation, and iterate until the time domain noise meets the target requirements. Because the coupling mode between the attack line and the victim line will decisively affect the noise level, the noise level can be controlled by adjusting the coupling distance between the attack line and the victim line mainly through electromagnetic simulation and time domain noise calculation.

[0096] In this embodiment, firstly, a reasonable PCB stackup needs to be determined. The stackup is generally a multi-layer board that can support a pair of victim lines and several pairs of attack lines. The board material is M6 with extremely low loss, and the glass cloth is reasonably selected to reduce the influence of the glass fiber effect. The inner layer routing uses HVLP grade copper foil; then the initial PCB layout design is performed; then a three-dimensional electromagnetic simulation is performed to extract the S parameters. This S parameter needs to be perfect enough to describe the complex coupling relationship between the attack line and the victim line; then the time domain noise simulation is calculated; then the PCB layout design is modified according to the trend of the time domain noise simulation, and it is iterated back and forth several times until the layout is finalized.

[0097] In the actual test process, the strength of the attack line input signal and the number of attack line input signals can be adjusted to freely control the injected crosstalk noise intensity and attack mode. Figure 1 As shown, in the PCB layout area, area 1 is used as the differential signal input of the victim line, and area 2 is used as the differential signal output of the victim line. It should be pointed out that electromagnetic simulation needs to be done for areas 1 and 2 according to the specific stacking to minimize the impact of impedance discontinuity. The PCB layout needs to support at least 112G bps PAM4 signals. In the specific board making process, a back drilling process is required to reduce the impact of via stubs on high-speed signals. Area 3 is a section of S-shaped winding of the victim line. The bending radius needs to be at least twenty times greater than the line width to reduce the coupling interference of the S-shaped winding itself to itself. The number of bends is mainly used to adjust the length of the victim line to meet the application scenarios of different transmission coefficients of the victim line. Area 4 is the coupling of the attack line and the victim line, which is mainly used to inject crosstalk noise. In the same layer of the PCB layout, the victim line is close to (approximately 1 times the line width coupling distance) the attack line A (for example, attack line 501.1) and the attack line B (for example, attack line 502.1). According to the electromagnetic simulation and time domain noise calculation, the coupling distance and coupling length of the attack line and the victim line are adjusted. In the specific real-time process, one or more attack lines can be freely selected to attack the victim line to simulate various complex crosstalk noise attack modes. Area 5 and area 6 are the input or output layout areas of the attack line. Area 7 is the attack line layer change via area. In the specific real-time process, the back drilling process needs to be used to reduce the impact of the via stubs on the high-speed signal.

[0098] In one embodiment, the time domain noise calculation method of step 104 includes the following sub-steps:

[0099] Step 201, first calculate the unit impulse response of a pair of attack lines to the victim line, then calculate the time domain noise caused by the pair of attack lines through the convolution of a series of unit impulse responses, and use the root mean square to measure the size of the time domain noise of the pair of attack lines to the victim line; the calculation can be performed by python or other mathematical analysis software;

[0100] Step 202, calculating the time domain noise magnitude of other pairs of attack lines to the victim line;

[0101] Step 203: The effective noise power finally superimposed on the victim line is obtained by accumulating the squares of the time domain noise of each pair of attacking lines.

[0102] Assume that the amplitude of the attack line output is a ±0.4V PAM4 signal, and the PAM signal is composed of a series of impulses (1 UI corresponds to 32 impulses, where the signal bit width UI is a concept in digital signals, which refers to the pulse width of a digital signal, usually the inverse of the transmission rate). The unit impulse response of a group of attack lines to the victim line can be calculated using python or other mathematical analysis software. The time domain noise of the entire PAM signal is the convolution of a series of unit impulse responses. Mathematically, the root mean square is used to measure the size of the time domain noise of the group of attack lines to the victim line; similarly, the size of the time domain noise of other groups of attack lines to the victim line can be calculated; considering that the noise coupled to the victim line by different groups of attack lines is incoherent noise, the effective noise power finally superimposed on the victim line is equal to the accumulation of the squares of the noise of each group; the coupling mode between the attack line and the victim line determines the noise size. In this embodiment, the noise size is mainly controlled by adjusting the coupling distance.

[0103] It should be noted that in the claims and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0104] All documents mentioned in this application are cited as references in this application, just as each document is cited as reference individually. In addition, it should be understood that after reading the above teaching content of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope defined by the claims attached to this application.

[0105] In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A PCB layout structure for regulating injected crosstalk noise, characterized in that: include: A pair of differential victim lines and multiple pairs of differential attack lines, where: In the transmission direction of the victim line, the differential signal input area, the S-shaped winding area, the straight transmission area, and the differential signal output area of ​​the victim line are sequentially included, the multiple pairs of attack lines are divided into two groups and symmetrically distributed on both sides of the straight transmission area, wherein the straight transmission area has multiple coupling areas respectively coupled with the multiple pairs of attack lines; In the transmission direction of the attack line, the attack line input layout area, the coupling area, and the attack line output layout area are sequentially included, wherein one or more pairs of the multiple pairs of attack lines further have an attack line layer-changing via area before coupling with the pair of victim lines, and the multiple pairs are greater than or equal to two pairs; Among them, the signal for testing enters the victim line from the differential signal input area of ​​the victim line, passes through the S-shaped winding area of ​​the victim line with adjustable length to meet the requirements of different transmission coefficients of the victim line, and passes through the coupling area of ​​the attack line and the victim line to simulate the addition of various complex crosstalk noises, wherein different attack modes are selected by selecting the attack line to attack one side of the victim line, selecting the attack line to attack both sides of the victim line, selecting to change the attack direction of the attack line to the victim line, and selecting one or more pairs of attack lines to attack the victim line; output from the differential signal output area of ​​the victim line and connected to a high-density multi-channel high-speed serial interface chip; the signal for testing with added noise is used to complete the function of testing and evaluating the tolerance of the high-density multi-channel high-speed serial interface chip to crosstalk noise.

2. The PCB layout structure according to claim 1, characterized in that: The PCB layout structure consists of a pair of differential victim lines and eight pairs of differential attack lines. The line width of the differential lines is 6 mil, and the line spacing between the differential lines is 12 mil.

3. The PCB layout structure according to claim 2, characterized in that: The differential signal input area of ​​the victim line and the differential signal output area of ​​the victim line both use two SMA connectors with an inner diameter of 1.85 mm as coaxial signal input and output; The input layout area of ​​the attack line and the output layout area of ​​the attack line select an 8-channel integrated cable assembly.

4. The PCB layout structure according to claim 1, characterized in that: The attack line layer change via area includes a via, wherein a via stub of the via is no greater than 5 mil to support at least a 112G bps PAM4 signal, and a via stub of the via is no greater than 3 mil to support a 224G bps PAM4 signal.

5. The PCB layout structure according to claim 4, characterized in that: The attack line layer change via area also includes a plurality of companion ground holes located around the via hole, and the companion ground holes are connected to the ground terminals of other layers in the PCB layout structure.

6. The PCB layout structure according to claim 1, characterized in that: The bending radius of the S-shaped winding area of ​​the victim line is at least twenty times the line width of the differential victim line, and the length of the victim line in the S-shaped winding area of ​​the victim line ranges from 10 inches to 25 inches.

7. The PCB layout structure according to claim 1, characterized in that: In the coupling region between the aggressor line and the victim line, the distance between the victim line and the aggressor line is 1 times the line width of the differential victim line.

8. The PCB layout structure according to claim 1, characterized in that: An input layout area and an output layout area corresponding to a group of attack lines are located on the same side of the straight transmission area of ​​the victim line and away from the coupling area, wherein each pair of attack lines respectively reaches the corresponding output layout area of ​​the attack line from the input layout area of ​​the attack line through multiple bends.

9. A design method for a PCB layout structure for injecting crosstalk noise as claimed in claim 1, characterized in that: include: Step 101, performing PCB stackup design, and determining a PCB stackup consisting of a pair of differential victim lines and multiple pairs of differential attack lines; Step 102, performing initial PCB layout design; Step 103, performing three-dimensional electromagnetic simulation to extract S parameters, wherein the S parameters are used to describe the coupling relationship between the plurality of pairs of differential attack lines and the pair of differential victim lines; Step 104, performing time domain noise simulation calculation; Step 105, modifying the initial PCB layout design according to the trend of the time domain noise simulation, selecting different attack modes, and iterating until the time domain noise meets the target requirements.

10. The design method according to claim 9, characterized in that: The time domain noise calculation method of step 104 is as follows: Step 201, first calculate the unit impulse response of a pair of attack lines to the victim line, then calculate the time domain noise caused by the pair of attack lines through the convolution of a series of unit impulse responses, and use the root mean square to measure the size of the time domain noise of the pair of attack lines to the victim line; Step 202, calculating the time domain noise magnitude of other pairs of attack lines to the victim line; Step 203: The effective noise power finally superimposed on the victim line is obtained by accumulating the squares of the time domain noise of each pair of attacking lines.

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