A high-voltage and high-speed level conversion circuit and conversion method thereof

Abstract

The present invention discloses a high-voltage and high-speed level conversion circuit and a conversion method thereof, comprising an input stage, a first acceleration circuit, a high-voltage tube M5, a high-voltage tube M6, a level conversion module and a second acceleration circuit, wherein the input stage is used to identify the high and low levels of a low-voltage domain clock signal CK, the first acceleration circuit is used to accelerate the level conversion of the low-voltage domain, the high-voltage tubes M5 and M6 are used to protect transistors M1 and M2, the level conversion module is used to convert the low-voltage domain level of 0~VDD to the high-voltage domain level of VSS~VS, and the second acceleration circuit is used to accelerate the level conversion of the high-voltage domain. The present invention realizes the high-speed conversion of the low-voltage domain clock signal into the high-voltage domain clock signal through the cooperation of the first acceleration circuit, the second acceleration circuit and the level conversion circuit, and solves the problem of spikes generated by the CSA output.

Description

Technical Field

[0001] The present invention relates to a level conversion circuit and a conversion method thereof, in particular to a high-voltage and high-speed level conversion circuit and a conversion method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] With the continuous development and progress of integrated circuits, the requirements for current sense amplifiers (CSAs) are getting higher and higher. CSAs are required to have high-side / low-side detection capabilities (high common-mode input voltage / low common-mode input voltage) and high precision. At present, most of the high-precision current sensing operational amplifiers use a chopper architecture. The CSA input stage needs to handle a wide range of common-mode input voltages, and the subsequent circuit only needs to process low-voltage signals. Therefore, the clock signal used for the low-voltage chopper switch is usually level-converted to obtain a clock signal for the high-voltage chopper switch. However, there will be a delay in the process of level conversion. The existence of the delay causes the phases of the two chopper switches to have a certain period of wrong phase, which will cause the CSA output to produce spikes. Therefore, it is necessary to design a high-voltage and high-speed level conversion circuit. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a high-voltage and high-speed level conversion circuit and a conversion method thereof to realize a high-speed level conversion function.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A high-voltage and high-speed level conversion circuit comprises an input stage, a first acceleration circuit, a high-voltage tube M5, a high-voltage tube M6, a level conversion module and a second acceleration circuit, wherein the input end of the input stage inputs a low-voltage domain clock signal CK, the first output end of the input stage is connected to the first input end of the first acceleration circuit, the second output end of the input stage is connected to the second input end of the first acceleration circuit, the third output end of the input stage is connected to the fourth input end of the first acceleration circuit, the third input end of the first acceleration circuit is connected to the low-voltage domain clock signal CK, the first output end of the first acceleration circuit is connected to the source of the high-voltage tube M5, the second output end of the first acceleration circuit is connected to the source of the high-voltage tube M6, the fifth input end, the sixth input end, The gate of the high-voltage tube M5 and the gate of the high-voltage tube M6 are connected to the power supply VBN, the drain of the high-voltage tube M5 is connected to the first input end of the level conversion module, the drain of the high-voltage tube M6 is connected to the second input end of the level conversion module, the first output end of the level conversion module is connected to the first input end of the second acceleration circuit, the second output end of the level conversion module is connected to the second input end of the second acceleration circuit, the first output end of the second acceleration circuit is connected to the input end of the inverter INV1, the output end of the inverter INV1 outputs the high-voltage domain clock signal CK_OUT, the second output end of the second acceleration circuit is connected to the input end of the inverter INV2, and the output end of the inverter INV2 outputs the high-voltage domain clock signal CKB_OUT.

[0006] Furthermore, the input stage includes a transistor M1, a transistor M2, an inverter INV3 and a current source I1, the gate of the transistor M1 is connected to the input end of the inverter INV3 and is connected to the low-voltage domain clock signal CK as the input end of the input stage, the output end of the inverter INV3 is connected to the gate of the transistor M2 and is used as the third output end of the input stage to output the low-voltage domain clock signal CKB, the source of the transistor M1 is connected to the source of the transistor M2 and one end of the current source I1, the other end of the current source I1 is grounded, the drain of the transistor M1 serves as the first output end of the input stage, and the drain of the transistor M2 serves as the second output end of the input stage.

[0007] Further, the first acceleration circuit includes a transistor M3, a transistor M4, a capacitor C1 and a capacitor C2, the source of the transistor M3 is connected to the power supply VBN as the fifth input terminal of the first acceleration circuit, the source of the transistor M4 is connected to the power supply VBN as the sixth output terminal of the first acceleration circuit, the gate of the transistor M3 is connected to one end of the capacitor C1 and serves as the third input terminal of the first acceleration circuit, the gate of the transistor M4 is connected to one end of the capacitor C1 and serves as the fourth input terminal of the first acceleration circuit, the drain of the transistor M3 and the other end of the capacitor C2 are connected to a node A, and the node A is both the first input terminal and the first output terminal of the first acceleration circuit, and the drain of the transistor M4 and the other end of the capacitor C1 are connected to a node B, and the node B is both the second input terminal and the second output terminal of the first acceleration circuit.

[0008] Further, the second acceleration circuit comprises a transistor M11, a transistor M12, a capacitor C3, a capacitor C4, an inverter INV4, an inverter INV5, an inverter INV6 and an inverter INV7, the source of the transistor M11 is connected to the source of the transistor M12 and connected to the power supply VS, the drain of the transistor M11 is connected to the input end of the inverter INV4 and serves as the first input end of the second acceleration circuit, and the drain of the transistor M12 is connected to the input end of the inverter INV6 and serves as the second input end of the second acceleration circuit. , the gate of the transistor M11 is connected to one end of the capacitor C4, the gate of the transistor M12 is connected to one end of the capacitor C3, the output end of the inverter INV4 is connected to the input end of the inverter INV5, the output end of the inverter INV5 and the other end of the capacitor C3 are connected to the node G and serve as the first output end of the second acceleration circuit, the output end of the inverter INV6 is connected to the input end of the inverter INV7, the output end of the inverter INV7 and the other end of the capacitor C4 are connected to the node H and serve as the second output end of the second acceleration circuit.

[0009] Further, the level conversion module includes a transistor M9, a transistor M10, a transistor M7, a transistor M8, a resistor R1, a resistor R2, a diode D1, a diode D2, a diode D3 and a diode D4, the source of the transistor M9 is connected to the source of the transistor M10 and connected to the power supply VS, the drain of the transistor M9 is connected to one end of the resistor R1, the other end of the resistor R1 and the gate of the transistor M10, the drain of the transistor M7 and the gate of the transistor M7 are connected to the node E and serve as the first output end of the level conversion module, the drain of the transistor M10 is connected to one end of the resistor R2, and the other end of the resistor R2 is connected to the gate of the transistor M10, the drain of the transistor M7 and the gate of the transistor M7. The gate of transistor M9, the drain of transistor M8 and the gate of transistor M8 are connected to node F and serve as the second output end of the level conversion module, the source of transistor M7, the anode of diode D1 and the cathode of diode D2 are connected to node C and serve as the first input end of the level conversion module, the cathode of diode D1 is connected to power supply VS, the anode of diode D2 is connected to power supply VSS, the source of transistor M8, the anode of diode D3 and the cathode of diode D4 are connected to node D and serve as the second input end of the level conversion module, the cathode of diode D3 is connected to power supply VS, and the anode of diode D4 is connected to power supply VSS.

[0010] Furthermore, the transistor M1, the transistor M2, the transistor M5, the transistor M6, the transistor M7 and the transistor M8 are NMOS transistors, and the transistor M3, the transistor M4, the transistor M9, the transistor M10, the transistor M11 and the transistor M12 are PMOS transistors.

[0011] A conversion method for a high-voltage and high-speed level conversion circuit comprises the following steps:

[0012] When the low-voltage domain clock signal CK=VDD, transistor M1 is turned on and transistor M2 is turned off. At this time, the voltage of node A is pulled down to VBN-VGS5 by the current source I1, and the voltage of node B is pulled up to VBN; where VDD is the peak voltage of the low-voltage domain clock signal CK, VBN is the voltage value of the power supply VBN, and VGS5 is the gate-source voltage of transistor M5;

[0013] The first acceleration circuit accelerates the process of pulling down the voltage of node A and pulling up the voltage of node B, specifically: when the low-voltage domain clock signal CK steps up from 0V to VDD, the upper step voltage is coupled to node B through capacitor C1, thereby accelerating the voltage increase of node B; at the same time, the low-voltage domain clock signal CKB steps down from VDD to 0V, and the lower step voltage is coupled to node A through capacitor C2, thereby accelerating the voltage pull-down of node A; during the step-down process of the low-voltage domain clock signal CKB, the transistor M4 is turned on, thereby accelerating the voltage increase of node B;

[0014] When the voltage of node A is pulled down to VBN-VGS5 and the voltage of node B is pulled up to VBN, the high-voltage tube M5 is turned on and the high-voltage tube M6 is turned off. There are two current paths flowing into the high-voltage tube M5, the first is VS ->M9 ->R1 ->M7 ->M5, and the second is VSS ->D2 ->M5.

[0015] Assuming that I1R1-VGS7 is much smaller than VD2, where I1 is the current of current source I1, VGS7 is the gate-source voltage of transistor M7, and VD2 is the forward conduction voltage drop of diode D2, it is considered that the current all takes the second path, and the voltage of node E is equal to VSS-VD2+VGS7 ≈VSS, so transistor M10 is turned on, and the voltage of node F is pulled up to VS, where VS is the voltage value of power supply VS;

[0016] The second acceleration circuit accelerates the establishment of the voltage of the node E and the voltage of the node F. Specifically, when the voltage of the node E steps down from VS to VSS and the voltage of the node F steps up from VSS to VS, the voltage of the node G steps down to VSS and is coupled to the gate of the transistor M12 through the capacitor C3, so that the transistor M12 is turned on, thereby accelerating the voltage of the node F to step up to VS.

[0017] The node G obtains the high-voltage domain clock signal CK_OUT after passing through the inverter IN1, and the node H signal obtains the high-voltage domain clock signal CKB_OUT after passing through the inverter IN2.

[0018] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a high-voltage and high-speed level conversion circuit, which realizes high-speed conversion of a low-voltage domain clock signal into a high-voltage domain clock signal through the cooperation of a first acceleration circuit, a second acceleration circuit and a level conversion circuit, greatly reduces the delay in the level conversion process, eliminates the wrong phase of the two chopper switches, and solves the problem of spikes in the CSA output. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a high-voltage and high-speed level conversion circuit of the present invention. DETAILED DESCRIPTION

[0020] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0021] like Figure 1 As shown, a high-voltage and high-speed level conversion circuit of the present invention comprises an input stage, a first acceleration circuit, a high-voltage tube M5, a high-voltage tube M6, a level conversion module and a second acceleration circuit, the input end of the input stage inputs a low-voltage domain clock signal CK, the first output end of the input stage is connected to the first input end of the first acceleration circuit, the second output end of the input stage is connected to the second input end of the first acceleration circuit, the third output end of the input stage is connected to the fourth input end of the first acceleration circuit, the third input end of the first acceleration circuit is connected to the low-voltage domain clock signal CK, the first output end of the first acceleration circuit is connected to the source of the high-voltage tube M5, the second output end of the first acceleration circuit is connected to the source of the high-voltage tube M6, the fifth input end and the sixth input end of the first acceleration circuit are connected to the low-voltage domain clock signal CK, and the first output end of the first acceleration circuit is connected to the source of the high-voltage tube M5. The input end, the gate of the high-voltage tube M5 and the gate of the high-voltage tube M6 are connected to the power supply VBN, the drain of the high-voltage tube M5 is connected to the first input end of the level conversion module, the drain of the high-voltage tube M6 is connected to the second input end of the level conversion module, the first output end of the level conversion module is connected to the first input end of the second acceleration circuit, the second output end of the level conversion module is connected to the second input end of the second acceleration circuit, the first output end of the second acceleration circuit is connected to the input end of the inverter INV1, the output end of the inverter INV1 outputs the high-voltage domain clock signal CK_OUT, the second output end of the second acceleration circuit is connected to the input end of the inverter INV2, and the output end of the inverter INV2 outputs the high-voltage domain clock signal CKB_OUT.

[0022] Among them, the input stage is used to identify the high and low levels of the low-voltage domain clock signal CK. The first acceleration circuit is used to accelerate the level conversion of the low-voltage domain. The high-voltage tubes M5 and M6 are used to protect the transistors M1 and M2. The level conversion module is used to convert the low-voltage domain level of 0~VDD to the high-voltage domain level of VSS~VS. The second acceleration circuit is used to accelerate the level conversion of the high-voltage domain.

[0023] The input stage includes a transistor M1, a transistor M2, an inverter INV3 and a current source I1. The gate of the transistor M1 is connected to the input end of the inverter INV3 and is connected to the low-voltage domain clock signal CK as the input end of the input stage. The output end of the inverter INV3 is connected to the gate of the transistor M2 and is used as the third output end of the input stage to output the low-voltage domain clock signal CKB. The source of the transistor M1 is connected to the source of the transistor M2 and one end of the current source I1. The other end of the current source I1 is grounded. The drain of the transistor M1 serves as the first output end of the input stage, and the drain of the transistor M2 serves as the second output end of the input stage.

[0024] The first acceleration circuit includes a transistor M3, a transistor M4, a capacitor C1 and a capacitor C2. The source of the transistor M3 is connected to the power supply VBN as the fifth input terminal of the first acceleration circuit. The source of the transistor M4 is connected to the power supply VBN as the sixth output terminal of the first acceleration circuit. The gate of the transistor M3 is connected to one end of the capacitor C1 and serves as the third input terminal of the first acceleration circuit. The gate of the transistor M4 is connected to one end of the capacitor C1 and serves as the fourth input terminal of the first acceleration circuit. The drain of the transistor M3 and the other end of the capacitor C2 are connected to a node A. Node A is both the first input terminal and the first output terminal of the first acceleration circuit. The drain of the transistor M4 and the other end of the capacitor C1 are connected to a node B. Node B is both the second input terminal and the second output terminal of the first acceleration circuit.

[0025] The second acceleration circuit comprises a transistor M11, a transistor M12, a capacitor C3, a capacitor C4, an inverter INV4, an inverter INV5, an inverter INV6 and an inverter INV7. The source of the transistor M11 is connected to the source of the transistor M12 and to the power supply VS. The drain of the transistor M11 is connected to the input end of the inverter INV4 and serves as the first input end of the second acceleration circuit. The drain of the transistor M12 is connected to the input end of the inverter INV6 and serves as the second input end of the second acceleration circuit. The gate of the transistor M11 is connected to one end of the capacitor C4, the gate of the transistor M12 is connected to one end of the capacitor C3, the output end of the inverter INV4 is connected to the input end of the inverter INV5, the output end of the inverter INV5 and the other end of the capacitor C3 are connected to the node G and serve as the first output end of the second acceleration circuit, the output end of the inverter INV6 is connected to the input end of the inverter INV7, the output end of the inverter INV7 and the other end of the capacitor C4 are connected to the node H and serve as the second output end of the second acceleration circuit.

[0026] The level conversion module includes a transistor M9, a transistor M10, a transistor M7, a transistor M8, a resistor R1, a resistor R2, a diode D1, a diode D2, a diode D3 and a diode D4. The source of the transistor M9 is connected to the source of the transistor M10 and connected to the power supply VS. The drain of the transistor M9 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the gate of the transistor M10, the drain of the transistor M7 and the gate of the transistor M7 at a node E and serves as a first output end of the level conversion module. The drain of the transistor M10 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the transistor M10. The gate of transistor M9, the drain of transistor M8 and the gate of transistor M8 are connected to node F and serve as the second output terminal of the level conversion module. The source of transistor M7, the anode of diode D1 and the cathode of diode D2 are connected to node C and serve as the first input terminal of the level conversion module. The cathode of diode D1 is connected to power supply VS, the anode of diode D2 is connected to power supply VSS, the source of transistor M8, the anode of diode D3 and the cathode of diode D4 are connected to node D and serve as the second input terminal of the level conversion module. The cathode of diode D3 is connected to power supply VS, and the anode of diode D4 is connected to power supply VSS.

[0027] The transistor M1 , the transistor M2 , the transistor M5 , the transistor M6 , the transistor M7 and the transistor M8 are NMOS transistors, and the transistor M3 , the transistor M4 , the transistor M9 , the transistor M10 , the transistor M11 and the transistor M12 are PMOS transistors.

[0028] A conversion method for a high-voltage and high-speed level conversion circuit comprises the following steps:

[0029] Since the level conversion circuit of the present invention has symmetry, when CK=VDD, CKB=0, and vice versa when CK=0, CKB=VDD, in both cases, the circuit can be flipped. Therefore, the embodiment of the present invention only lists the case when CK=VDD.

[0030] When the low-voltage domain clock signal CK=VDD, transistor M1 is turned on and transistor M2 is turned off. At this time, the voltage of node A is pulled down to VBN-VGS5 by the current source I1, and the voltage of node B is pulled up to VBN; wherein VDD is the peak voltage of the low-voltage domain clock signal CK, VBN is the voltage value of the power supply VBN, and VGS5 is the gate-source voltage of transistor M5.

[0031] The first acceleration circuit accelerates the process of pulling down the voltage of node A and pulling up the voltage of node B, specifically: when the low-voltage domain clock signal CK steps up from 0V to VDD, the upper step voltage is coupled to node B through capacitor C1, thereby accelerating the voltage increase of node B; at the same time, the low-voltage domain clock signal CKB steps down from VDD to 0V, and the lower step voltage is coupled to node A through capacitor C2, thereby accelerating the voltage pull-down of node A; during the lower step process of the low-voltage domain clock signal CKB, transistor M4 will be turned on, thereby accelerating the voltage increase of node B, achieving an acceleration effect.

[0032] When the voltage of node A is pulled down to VBN-VGS5 and the voltage of node B is pulled up to VBN, the high-voltage tube M5 is turned on and the high-voltage tube M6 is turned off; there are two current paths flowing into the high-voltage tube M5, the first is VS ->M9 ->R1 ->M7 ->M5, and the second is VSS ->D2 ->M5.

[0033] Assuming that I1R1-VGS7 is much smaller than VD2, where I1 is the current of current source I1, VGS7 is the gate-source voltage of transistor M7, and VD2 is the forward conduction voltage drop of diode D2, it can be considered that the current almost entirely takes the second path, and the voltage at node E is equal to VSS-VD2+VGS7 ≈VSS. Therefore, transistor M10 is turned on, and the voltage at node F is pulled up to VS, where VS is the voltage value of power supply VS.

[0034] The second acceleration circuit accelerates the establishment of the voltage of node E and the voltage of node F. Specifically, when the voltage of node E steps down from VS to VSS and the voltage of node F steps up from VSS to VS, the voltage of node G steps down to VSS and is coupled to the gate of transistor M12 through capacitor C3, causing transistor M12 to turn on, thereby accelerating the voltage of node F to step up to VS.

[0035] The second acceleration circuit can accelerate the pull-up establishment of the node E and the node F. The pull-down of the node E and the node F is through the path of the diode D2 and the diode D4, and the speed is relatively fast, so no additional acceleration circuit is required.

[0036] The node G obtains the high-voltage domain clock signal CK_OUT after passing through the inverter IN1, and the node H signal obtains the high-voltage domain clock signal CKB_OUT after passing through the inverter IN2.

[0037] The present invention provides a high-voltage and high-speed level conversion circuit. Through the cooperation of a first acceleration circuit, a second acceleration circuit and a level conversion circuit, a high-speed conversion of a low-voltage domain clock signal into a high-voltage domain clock signal is achieved, the delay in the level conversion process is greatly reduced, the wrong phase of the phases of two chopper switches is eliminated, and the problem of spikes generated in CSA output is solved.

[0038] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A high-voltage and high-speed level conversion circuit, characterized in that: The invention comprises an input stage, a first acceleration circuit, a transistor M5, a transistor M6, a level conversion module and a second acceleration circuit, wherein the input end of the input stage inputs a low-voltage domain clock signal CK, the first output end of the input stage is connected to the first input end of the first acceleration circuit, the second output end of the input stage is connected to the second input end of the first acceleration circuit, the third output end of the input stage is connected to the fourth input end of the first acceleration circuit, the third input end of the first acceleration circuit is connected to the low-voltage domain clock signal CK, the first output end of the first acceleration circuit is connected to the source of the transistor M5, the second output end of the first acceleration circuit is connected to the source of the transistor M6, the fifth input end, the sixth input end and the gate electrode of the transistor M5 of the first acceleration circuit are connected to the gate electrode of the transistor M6, and the gate electrode of the transistor M6 is connected to the gate electrode of the transistor M6. The gate of the transistor M6 is connected to the power supply VBN, the drain of the transistor M5 is connected to the first input end of the level conversion module, the drain of the transistor M6 is connected to the second input end of the level conversion module, the first output end of the level conversion module is connected to the first input end of the second acceleration circuit, the second output end of the level conversion module is connected to the second input end of the second acceleration circuit, the first output end of the second acceleration circuit is connected to the input end of the inverter INV1, the output end of the inverter INV1 outputs the high-voltage domain clock signal CK_OUT, the second output end of the second acceleration circuit is connected to the input end of the inverter INV2, and the output end of the inverter INV2 outputs the high-voltage domain clock signal CKB_OUT; The first acceleration circuit comprises a transistor M3, a transistor M4, a capacitor C1 and a capacitor C2, the source of the transistor M3 is connected to the power supply VBN as the fifth input terminal of the first acceleration circuit, the source of the transistor M4 is connected to the power supply VBN as the sixth output terminal of the first acceleration circuit, the gate of the transistor M3 is connected to one end of the capacitor C1 and serves as the third input terminal of the first acceleration circuit, the gate of the transistor M4 is connected to one end of the capacitor C2 and serves as the fourth input terminal of the first acceleration circuit, the drain of the transistor M3 and the other end of the capacitor C2 are connected to a node A, which is both the first input terminal and the first output terminal of the first acceleration circuit, the drain of the transistor M4 and the other end of the capacitor C1 are connected to a node B, which is both the second input terminal and the second output terminal of the first acceleration circuit; The second acceleration circuit comprises a transistor M11, a transistor M12, a capacitor C3, a capacitor C4, an inverter INV4, an inverter INV5, an inverter INV6 and an inverter INV7, a source of the transistor M11 is connected to a source of the transistor M12 and to a power supply VS, a drain of the transistor M11 is connected to an input end of the inverter INV4 and serves as a first input end of the second acceleration circuit, a drain of the transistor M12 is connected to an input end of the inverter INV6 and serves as a second input end of the second acceleration circuit, The gate of the transistor M11 is connected to one end of the capacitor C4, the gate of the transistor M12 is connected to one end of the capacitor C3, the output end of the inverter INV4 is connected to the input end of the inverter INV5, the output end of the inverter INV5 and the other end of the capacitor C3 are connected to the node G and serve as the first output end of the second acceleration circuit, the output end of the inverter INV6 is connected to the input end of the inverter INV7, the output end of the inverter INV7 and the other end of the capacitor C4 are connected to the node H and serve as the second output end of the second acceleration circuit; The level conversion module includes a transistor M9, a transistor M10, a transistor M7, a transistor M8, a resistor R1, a resistor R2, a diode D1, a diode D2, a diode D3 and a diode D4. The source of the transistor M9 is connected to the source of the transistor M10 and to the power supply VS. The drain of the transistor M9 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to the gate of the transistor M10, the drain of the transistor M7 and the gate of the transistor M7 at a node E and serves as a first output end of the level conversion module. The drain of the transistor M10 is connected to one end of the resistor R2. The other end of the resistor R2 is connected to the transistor M10. The gate of the transistor M9, the drain of the transistor M8 and the gate of the transistor M8 are connected to the node F and serve as the second output terminal of the level conversion module. The source of the transistor M7, the anode of the diode D1 and the cathode of the diode D2 are connected to the node C and serve as the first input terminal of the level conversion module. The cathode of the diode D1 is connected to the power supply VS, and the anode of the diode D2 is connected to the power supply VSS. The source of the transistor M8, the anode of the diode D3 and the cathode of the diode D4 are connected to the node D and serve as the second input terminal of the level conversion module. The cathode of the diode D3 is connected to the power supply VS, and the anode of the diode D4 is connected to the power supply VSS.

2. The high-voltage and high-speed level conversion circuit according to claim 1, characterized in that: The input stage includes a transistor M1, a transistor M2, an inverter INV3 and a current source I1. The gate of the transistor M1 is connected to the input end of the inverter INV3 and is connected to the low-voltage domain clock signal CK as the input end of the input stage. The output end of the inverter INV3 is connected to the gate of the transistor M2 and outputs the low-voltage domain clock signal CKB as the third output end of the input stage. The source of the transistor M1 is connected to the source of the transistor M2 and one end of the current source I1. The other end of the current source I1 is grounded. The drain of the transistor M1 serves as the first output end of the input stage, and the drain of the transistor M2 serves as the second output end of the input stage.

3. The high-voltage and high-speed level conversion circuit according to claim 1, characterized in that: The transistor M1, the transistor M2, the transistor M5, the transistor M6, the transistor M7 and the transistor M8 are NMOS transistors, and the transistor M3, the transistor M4, the transistor M9, the transistor M10, the transistor M11 and the transistor M12 are PMOS transistors.

4. A conversion method for a high-voltage and high-speed level conversion circuit according to claim 1, characterized in that The following steps are involved: When the low-voltage domain clock signal CK=VDD, transistor M1 is turned on and transistor M2 is turned off. At this time, the voltage of node A is pulled down to VBN-VGS5 by the current source I1, and the voltage of node B is pulled up to VBN. Wherein VDD is the voltage peak value of the low voltage domain clock signal CK, VBN is the voltage value of the power supply VBN, and VGS5 is the gate-source voltage of the transistor M5; The first acceleration circuit accelerates the process of pulling down the voltage of node A and pulling up the voltage of node B. Specifically, when the low-voltage domain clock signal CK steps up from 0V to VDD, the up-step voltage is coupled to node B through capacitor C1, thereby accelerating the voltage increase of node B. At the same time, the low-voltage domain clock signal CKB steps down from VDD to 0V, and the step-down voltage is coupled to node A through capacitor C2, thereby accelerating the voltage pull-down of node A; the transistor M4 is turned on during the step-down process of the low-voltage domain clock signal CKB, thereby accelerating the voltage rise of node B; When the voltage of node A is pulled down to VBN-VGS5 and the voltage of node B is pulled up to VBN, transistor M5 is turned on and transistor M6 is turned off; there are two current paths flowing into transistor M5, the first is VS -> M9 -> R1 -> M7 -> M5, and the second is VSS -> D2 -> M5; Assuming that I1R1-VGS7 is much smaller than VD2, where I1 is the current of current source I1, VGS7 is the gate-source voltage of transistor M7, and VD2 is the forward conduction voltage drop of diode D2, it is considered that the current all takes the second path, and the voltage of node E is equal to VSS-VD2+VGS7 ≈VSS, so transistor M10 is turned on, and the voltage of node F is pulled up to VS, where VS is the voltage value of power supply VS; The second acceleration circuit accelerates the establishment of the voltage of the node E and the voltage of the node F. Specifically, when the voltage of the node E steps down from VS to VSS and the voltage of the node F steps up from VSS to VS, the voltage of the node G steps down to VSS and is coupled to the gate of the transistor M12 through the capacitor C3, so that the transistor M12 is turned on, thereby accelerating the voltage of the node F to step up to VS. The node G obtains the high-voltage domain clock signal CK_OUT after passing through the inverter INV1, and the node H signal obtains the high-voltage domain clock signal CKB_OUT after passing through the inverter INV2.

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