A read-write equalization circuit and method based on ferroelectric memory and ferroelectric memory

Abstract

The present invention discloses a read-write equalization circuit, method and ferroelectric memory based on ferroelectric memory, which can suppress the drift of hysteresis loop of ferroelectric memory and improve reliability. The circuit comprises: a read circuit; a write circuit; a sensing device; a control circuit; and a pre-read detection circuit. When the original logic state of the ferroelectric memory is the first logic state and the ferroelectric memory is to be subjected to a first write operation, the pre-read detection circuit controls the write circuit to perform a second write operation, and then the control circuit controls the write circuit to perform a first write operation, thereby writing data corresponding to the first logic state into the ferroelectric memory.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a read-write equalization circuit and method based on a ferroelectric memory and a ferroelectric memory. Background Art

[0002] As an indispensable part of the integrated circuit industry, memory is widely used in various fields such as communications, the Internet of Things, and computers. Ferroelectric memory is a new type of memory developed on the basis of the development of semiconductor technology. Ferroelectric memory has the advantages of high-speed reading and writing, low power consumption, long service life, non-volatile storage, and good radiation resistance, and has broad application prospects.

[0003] The development of ferroelectric memory has entered the third generation and is moving towards higher process nodes. However, reliability issues are still the biggest obstacle to the real application of third-generation ferroelectric memory, and fatigue characteristics are the most significant problem. The read and write operations of existing ferroelectric memories are closely related, that is, when performing a read operation, it is accompanied by a write back, and when performing a write operation, it is necessary to pre-read in advance. Unbalanced read and write operations is a common phenomenon in practical applications. This imbalance can cause the hysteresis loop of the ferroelectric memory to drift, which has a potential impact on system performance and the reliability of the ferroelectric memory.

[0004] Figure 1A to Figure 1D The figure shows a schematic diagram of the hysteresis loop of a ferroelectric memory. In each figure, the horizontal axis is the electric field strength E applied to the ferroelectric material (equivalent to the voltage applied on both sides of the ferroelectric material), and the vertical axis is the polarization value P of the ferroelectric material. Points A and C in the figure are residual polarization points, which respectively represent the polarization values ​​of the ferroelectric material corresponding to the "0" and "1" data stored in the ferroelectric memory, that is, A corresponds to "0" and C corresponds to "1". Points B and D are saturation polarization points. Ec and -Ec respectively represent the coercive field strength when the polarity of the ferroelectric material is zero (that is, the electric field that demagnetizes the polarized ferroelectric material).

[0005] Since the read and write operations of ferroelectric memory exist together in one operation process, the read and write operations of ferroelectric memory can be divided into Figure 1A to Figure 1D The four types shown are:

[0006] Figure 1A The hysteresis loop "0-0" operation path of the ferroelectric memory, that is, the original storage data in the ferroelectric memory cell is "0", and the data "0" must be written after the read and write operation. In the hysteresis loop, it is represented by pre-reading operation, writing or writing back "0" operation from point A to point D, and then removing the voltage on both sides of the ferroelectric material, returning to point A, and realizing the storage of data "0".

[0007] Figure 1BThe hysteresis loop "0-1" operation path of the ferroelectric memory, that is, the original storage data in the ferroelectric memory cell is "0", and the data "1" needs to be written after the read and write operation. In the hysteresis loop, it is represented by the pre-read operation from point A to point D, then the write "1" operation to point B, and the voltage on both sides of the ferroelectric material is removed to point C, realizing the storage of data "1".

[0008] Figure 1C The hysteresis loop "1-0" operation path of the ferroelectric memory, that is, the original storage data in the ferroelectric memory cell is "1", and the data "0" needs to be written after the read and write operation. In the hysteresis loop, it is shown as starting from point C through the pre-read operation and the write "0" operation to point D, and then the voltage on both sides of the ferroelectric material is removed to point A to realize the storage of data "0".

[0009] Figure 1D The hysteresis loop "1-1" operation path of the ferroelectric memory, that is, the original storage data in the ferroelectric memory cell is "1", and the data "1" needs to be written after the read and write operation. In the hysteresis loop, it is represented by pre-reading from point C to point D, then writing or writing back "1" to point B, removing the voltage on both sides of the ferroelectric material to point C, and realizing the storage of data "1".

[0010] As can be seen from the diagram, Figure 1B to Figure 1D The operating paths of the hysteresis loops shown all pass through the coercive field, e.g. Figure 1B In the case of, the path from point A to point B passes through the coercive field strength -Ec, Figure 1C In the case of , the path from point C to point D passes through the coercive field strength Ec. Figure 1D In this case, the path from point C to point D passes through the coercive field strength Ec, and the path from point A to point B also passes through the coercive field strength -Ec. Figure 1A The "0-0" operation path (point A→point D→point A) of the hysteresis loop shown does not pass through any coercive field strength. However, such operation for a long time will cause the hysteresis loop of the ferroelectric memory to drift, thereby affecting the reliability of the ferroelectric memory. Summary of the invention

[0011] In order to make ferroelectric memory applicable to more application scenarios, its reliability needs to be improved. The present invention focuses on the drift of the hysteresis loop, improves the "0-0" operation of the ferroelectric memory, and proposes a method and circuit for improving the drift of the hysteresis loop of the ferroelectric memory, which can suppress the drift of the hysteresis curve and balance the read and write operations of the ferroelectric memory.

[0012] According to some exemplary embodiments of the present disclosure, a read-write equalization circuit based on a ferroelectric memory is provided, which performs read and write operations on a ferroelectric memory capable of storing at least a first logic state and a second logic state, and is characterized in that it includes: a read circuit, which applies a pre-read voltage to the ferroelectric memory to perform a pre-read operation; a write circuit, which performs a write operation on the ferroelectric memory, including a first write operation to make the ferroelectric memory store the first logic state, and a second write operation to make the ferroelectric memory store the second logic state; a sensing device, which senses the ferroelectric memory and outputs a result of the pre-read operation, i.e., a pre-read result, to determine an original logic state stored in the ferroelectric memory; a control circuit, which controls the write circuit to perform the first write operation or the second write operation; and a pre-read detection circuit, which detects the pre-read result and determines whether to turn on the write circuit to perform the write operation according to the pre-read result. When the original logic state of the ferroelectric memory is the first logic state and the first write operation is to be performed on the ferroelectric memory, after the pre-read detection circuit controls the write circuit to perform the second write operation, the control circuit controls the write circuit to perform the first write operation, thereby writing data corresponding to the first logic state to the ferroelectric memory.

[0013] In some embodiments, the first logic state corresponds to a logic "0" and the second logic state corresponds to a logic "1".

[0014] In some embodiments, the write circuit includes a first write circuit for performing the first write operation, and a second write circuit for performing the second write operation.

[0015] In some embodiments, one end of the pre-read detection circuit is connected between the sensing device and the control circuit, and the other end is connected to the second writing circuit.

[0016] In some embodiments, during the period when the pre-read detection circuit controls the write circuit to perform the first write operation, the control circuit is bypassed.

[0017] In some embodiments, when the original logical state of the ferroelectric memory is the first logical state and the second write operation is to be performed on the ferroelectric memory, the control circuit controls the write circuit to perform the second write operation, thereby writing data corresponding to the second logical state to the ferroelectric memory.

[0018] In some embodiments, when the original logical state of the ferroelectric memory is the second logical state, the control circuit controls the write circuit to perform the first write operation or the second write operation, thereby writing data corresponding to the first logical state or the second logical state to the ferroelectric memory.

[0019] According to some exemplary embodiments of the present disclosure, there is also provided a read-write balance method based on a ferroelectric memory, which performs read and write operations on a ferroelectric memory capable of storing at least a first logic state and a second logic state, and is characterized in that it includes: a read circuit applies a pre-read voltage to the ferroelectric memory to perform a pre-read operation; a sensing device senses the ferroelectric memory and outputs a result of the pre-read operation, i.e., a pre-read result, to determine an original logic state stored in the ferroelectric memory; a control circuit controls a write circuit to perform a write operation on the ferroelectric memory, including a first write operation to make the ferroelectric memory store the first logic state, and a second write operation to make the ferroelectric memory store the second logic state; and a pre-read detection circuit detects the pre-read result, and decides whether to turn on the write circuit to perform the write operation according to the pre-read result, and when the original logic state of the ferroelectric memory is the first logic state and the first write operation is to be performed on the ferroelectric memory, after the pre-read detection circuit controls the write circuit to perform the second write operation, the control circuit controls the write circuit to perform the first write operation, thereby writing data corresponding to the first logic state to the ferroelectric memory.

[0020] According to some exemplary embodiments of the present disclosure, a ferroelectric memory is further provided, which uses the read-write equalization circuit based on the ferroelectric memory as claimed in any one of claims 1 to 7 to perform read and write operations.

[0021] The read-write balance circuit disclosed in the present invention is characterized in that by setting a pre-read detection circuit, when the original storage data in the memory cell is the first logic state "0" and the data of the first logic state "0" is to be written into the memory cell, after the original storage data is read out as "0" through the pre-read operation, the second write circuit for writing "1" is turned on through the pre-read detection circuit, and after the second write operation of writing "1" is completed, the first write circuit for writing "0" is controlled by the control circuit to perform the first write operation, thereby realizing the "0-0" operation. Through two write operations, the path on the hysteresis loop passes through the coercive field strength twice, so that the read-write operation can be balanced, the hysteresis loop is suppressed from drifting, and the reliability of the ferroelectric memory is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0023] Figure 1A to Figure 1D A schematic diagram of the hysteresis loop of a ferroelectric memory is shown, wherein: Figure 1A This is a schematic diagram of the hysteresis loop "0-0" operation of the ferroelectric memory. Figure 1B This is a schematic diagram of the hysteresis loop "0-1" operation of the ferroelectric memory. Figure 1C This is a schematic diagram of the hysteresis loop "1-0" operation of the ferroelectric memory. Figure 1D It is a schematic diagram of the "1-1" operation of the hysteresis loop of the ferroelectric memory;

[0024] Figure 2 is a schematic diagram of a basic structure of a ferroelectric memory cell 1 according to an embodiment of the present disclosure;

[0025] Figure 3 Shows the Figure 2 The circuit diagram of the ferroelectric memory cell 1 shown in FIG. 1 performs read and write operations;

[0026] Figure 4 is a circuit structure diagram of the read-write equalization circuit 200 involved in this embodiment;

[0027] Figure 5 is a flow chart of the read-write balancing method involved in this embodiment;

[0028] Figure 6 A schematic diagram of a “0-0” operation path of a hysteresis loop of a ferroelectric memory using the read-write equalization circuit and method according to the present embodiment is shown. DETAILED DESCRIPTION

[0029] The specific implementation methods of the present disclosure will be described below. It should be noted that in the specific description of these implementation methods, in order to provide a concise description, it is impossible for this specification to provide a detailed description of all the features of the actual implementation methods. It should be understood that in the actual implementation of any implementation method, just as in the process of any engineering project or design project, in order to achieve the specific goals of the developer and to meet system-related or business-related restrictions, various specific decisions are often made, and this will also change from one implementation method to another. In addition, it can also be understood that although the efforts made in this development process may be complex and lengthy, for ordinary technicians in the field related to the content disclosed by the present disclosure, some changes in design, manufacturing or production based on the technical content disclosed in the present disclosure are just conventional technical means, and should not be understood as insufficient content of the present disclosure.

[0030] Unless otherwise defined, the technical terms or scientific terms used in the claims and the specification shall have the usual meanings understood by persons with ordinary skills in the technical field to which the present disclosure belongs. The words "first", "second" and similar words used in the patent application specification and the claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one" or "one" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalent elements, and do not exclude other elements or objects. Words such as "connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, nor are they limited to direct or indirect connections.

[0031] In the present disclosure, unless otherwise specified, all embodiments and preferred embodiments mentioned herein can be combined with each other to form a new technical solution. In the present disclosure, unless otherwise specified, all technical features and preferred features mentioned herein can be combined with each other to form a new technical solution.

[0032] In the description of the embodiments of the present disclosure, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0033] The following describes in detail a read-write equalization method and circuit based on a ferroelectric memory provided according to an embodiment of the present disclosure in conjunction with the accompanying drawings.

[0034] Figure 2Schematic diagram of the basic structure of the ferroelectric memory cell involved in the embodiment of the present disclosure. As shown in the figure, the ferroelectric memory cell 1 of the present embodiment adopts a 1T1C structure, that is, it includes a capacitor 10 and a transistor 20. The capacitor 10 is a ferroelectric capacitor with a ferroelectric material arranged between the upper and lower plates. The ferroelectric material includes, for example, barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), bismuth tantalate (SBT), bismuth ferrite (BFO), etc. The data "0" or "1" is stored by charging or discharging the capacitor 10, that is, by polarizing the ferroelectric material in the capacitor 10. The lower plate of the capacitor 10 is connected to the plate line PL (plate line), the upper plate is connected to the source (or drain) of the transistor 20, the drain (or source) of the transistor 20 is connected to the bit line BL (bit line), and the gate is connected to the word line WL (word line). By applying a voltage to the gate of the transistor 20 through the word line WL, the memory cell 1 corresponding to the capacitor 10 can be selected (activated) for programming operation.

[0035] Since the plates of the capacitor 10 are made of ferroelectric material, different voltages are applied between the upper and lower plates of the capacitor 10 by applying different voltages through the bit line BL and the plate line PL, so that the ferroelectric material is polarized differently, thereby changing the charge stored on the capacitor 10. The polarization state of the ferroelectric material, i.e., the change in the stored charge, corresponds to the logic state ("0" or "1") of the capacitor 10. By comparing the change in the charge stored in the capacitor 10 obtained on the bit line BL, i.e., the voltage signal of the capacitor 10, with a reference signal (e.g., the reference voltage VREF shown in the figure), the data stored in the memory cell 1 can be determined (corresponding to a read operation) through a sensing element 30, such as a sensitive amplifier SA.

[0036] For a write operation, a higher voltage (e.g., a positive voltage) is applied to the lower plate of the capacitor 10 through the plate line PL, and a lower voltage (e.g., ground or a negative voltage) is applied to the upper plate of the capacitor 10 through the bit line BL, so that "0" can be written to the memory cell 1. "1" can be written by performing the opposite process, that is, the lower plate of the capacitor 10 is a low voltage or grounded to zero, and the upper plate is a high voltage. In some instances, the logic of the polarity state corresponding to the writing of "0" and "1" can be reversed without changing the understanding.

[0037] Figure 3 Yes Figure 2 The circuit diagram of the ferroelectric memory cell 1 for performing read and write operations is shown. The read and write operation circuit 100 includes the ferroelectric memory cell 1, a sense amplifier 30, a read circuit 40, a write "0" circuit 50, a write "1" circuit 60, a write-back / write control circuit 70, and a control module for controlling each circuit component which is omitted from the diagram.

[0038] The read and write operation process of ferroelectric memory includes pre-read (ACT = Activate), read (RD = Read), write (WR = Write), write back / write (PRE = Precharge) and other operations. The pre-read operation is to apply a read voltage to the ferroelectric memory cell and determine whether the data stored in the memory cell is "0" or "1" through the comparison output of the sensing element. The read operation is to output the data output by the sensing element to the external control logic, the write operation is to send the data written by the external control logic back to the sensing element, and the write back / write operation is to write data into the ferroelectric memory cell, such as writing "1" or writing back "1".

[0039] First, a pre-read operation is performed, that is, after the ferroelectric memory cell 1 shown in the figure is selected (activated) by the word line WL, the read circuit 40 connects one plate ( Figure 3 A pre-read voltage is applied to the right plate (in the figure), so that the plate line PL changes from a low level to a high level, for example, to charge the capacitor 10 to polarize it. The signal (e.g., voltage) output by the bit line BL is compared with a reference signal such as a reference voltage VREF through the sense amplifier 30, thereby determining the state stored in the memory cell 1, that is, determining whether the data in the memory cell 1 is "0" or "1". For example, if the bit line BL has a higher voltage than the reference voltage VREF, the sense amplifier can determine that the state stored in the memory cell 1 is a logic "1", and vice versa.

[0040] For example, in Figure 1A to Figure 1D In the example, when the data originally stored in the memory cell 1 is "0", the pre-read voltage is applied so that the change of the charge stored in the capacitor 10 follows the operation path from point A to point D. At this time, the voltage obtained by the bit line BL is compared with the reference voltage VREF by the sense amplifier 30, so that the initial charge state stored in the capacitor 10 can be determined, that is, the logic value of the ferroelectric memory cell 1 is determined to be "0". After removing the pre-read voltage, the charge will return to the initial charge state along the opposite path, that is, point D to point A.

[0041] When the data originally stored in the memory cell 1 is "1", by applying the pre-read voltage, the change of the charge stored in the capacitor 10 follows the operation path from point C to point D. At this time, by comparing the voltage obtained by the bit line BL with the reference voltage VREF through the sense amplifier 30, the initial charge state stored in the capacitor 10 can be determined, that is, the logic value of the ferroelectric memory cell 1 is determined to be "1". After removing the pre-read voltage, the charge will return to the initial charge state along the opposite path, that is, point D → point C.

[0042] Then, the sense amplifier 30 outputs the result representing the original storage data of the memory cell 1 to the write-back / write control circuit 70. The write-back / write control circuit 70 controls the write "0" circuit 50 and the write "1" circuit 60 according to the result, respectively, to conduct at both ends of the ferroelectric capacitor 10 to perform the corresponding write operation.

[0043] For example, when the result obtained by the sensitive amplifier 30 indicates that the original storage data of the memory cell 1 is "0", if data "0" is to be written in the memory cell 1 at this time, the write back / write control circuit 70 turns on the write "0" circuit to perform a write "0" or write back operation.

[0044] When the result obtained by the sense amplifier 30 indicates that the original storage data of the memory cell 1 is "0", if data "1" is to be written into the memory cell 1 at this time, the write-back / write control circuit 70 turns on the write "1" circuit to perform a write "1" operation.

[0045] When the result obtained by the sense amplifier 30 indicates that the original storage data of the memory cell 1 is "1", if data "0" is to be written into the memory cell 1 at this time, the write-back / write control circuit 70 turns on the write "0" circuit to perform a write "0" operation.

[0046] When the result obtained by the sensitive amplifier 30 indicates that the original storage data of the memory cell 1 is "1", if data "1" is to be written in the memory cell 1 at this time, the write-back / write-control circuit 70 turns on the write "1" circuit to perform a write "1" or write-back operation.

[0047] As mentioned above, when the original storage data of memory cell 1 is "0" and data "0" is to be written into memory cell 1, the "0-0" operation path point A → point D → point A does not pass through any coercive field strength. Such operation for a long time will cause the hysteresis loop of the ferroelectric memory to drift, thereby affecting the reliability of the ferroelectric memory.

[0048] The read-write equalization circuit and method provided by the present invention can improve the problem of hysteresis loop drift of ferroelectric memory.

[0049] Figure 4 2 is a circuit diagram of a read / write equalization circuit 200 according to the present embodiment. The read / write equalization circuit 200 includes a ferroelectric memory cell 1, a sense amplifier 30, a read circuit 40, a write "0" circuit 50, a write "1" circuit 60, a write-back / write control circuit 70, a pre-read detection circuit 80, and a control module for controlling each circuit component which is omitted from the diagram. Figure 3The difference between the read and write operation circuit 100 shown is the pre-read detection circuit 80, and the other structures are the same as those in the read and write operation circuit 100, so the same parts will not be repeated, and only the difference between the two will be further described here.

[0050] One end of the pre-read detection circuit 80 is connected between the output end of the sense amplifier 30 and the write-back / write control circuit 70 , and the other end is connected to the write “1” circuit 60 .

[0051] The pre-read detection circuit 80 is used to detect the pre-read result of the memory cell 1, that is, to detect the output result of the sense amplifier 30, and to decide whether to turn on the write "1" circuit according to the detection result. For example, when the result obtained by the sense amplifier 30 indicates that the original storage data of the memory cell 1 is "0", that is, when the pre-read detection result is that the original storage data is "0", if the data "0" is to be written in the memory cell 1, the pre-read detection circuit 80 turns on the write "1" circuit 60, and the write-back / write control circuit 70 is bypassed at this time, that is, the write-back / write control circuit 70 will not turn on the write "0" circuit based on the output of the sense amplifier 30 (that is, the output indicating that the original storage data of the memory cell 1 is "0"). After the write "1" circuit 60 writes data "1" to the memory cell 1, the sensitive amplifier 30 will output a result indicating that the storage data of the memory cell 1 is "1". At this time, the pre-read detection result obtained by the pre-read detection circuit 80 becomes that the storage data is "1", so the write "1" circuit 60 is disconnected, and the write-back / write control circuit 70 controls the connection of the write "0" circuit 50 based on the output of the sensitive amplifier 30, and performs a write "0" operation on the memory cell 1, thereby realizing the writing of data "0" and completing the "0-0" operation.

[0052] For the "0-1" operation, although the pre-read detection result obtained by the pre-read detection circuit 80 is that the original storage data is "0", because the data to be written is "1", the pre-read detection circuit 80 does not connect to the write "1" circuit 60, and the write-back / write control circuit 70 controls the write "1" circuit 60 to perform the write "1" operation. Of course, in this case, the pre-read detection circuit 80 can also connect to the write "1" circuit 60 to perform the write "1" operation.

[0053] For the "1-0" operation, the pre-read detection result obtained by the pre-read detection circuit 80 is that the original storage data is "1", so the pre-read detection circuit 80 does not connect the write "1" circuit 60, but the write-back / write control circuit 70 controls the write "0" circuit 50 to perform the write "0" operation.

[0054] For the "1-1" operation, the pre-read detection result obtained by the pre-read detection circuit 80 is that the original storage data is "1", so the pre-read detection circuit 80 will not connect the write "1" circuit 60, but the write-back / write control circuit 70 controls the write "1" circuit 50 to perform the write "1" operation.

[0055] Based on the read-write equalization circuit 200 of this embodiment, when performing a "0-0" operation, that is, when the original storage data in the memory cell 1 is "0" and the data "0" is to be written in the memory cell 1, after the pre-read operation reads out that the original storage data is "0", the write "1" circuit 60 is turned on through the pre-read detection circuit 80 to insert a write "1" operation, and after the write "1" operation is completed, the write "0" circuit 50 is controlled by the write-back / write control circuit 70 to perform a write "0" or write-back operation.

[0056] Figure 5 It is a flow chart of the read-write balance method involved in this embodiment.

[0057] In step S11, a pre-read operation is performed. Memory cell 1 (such as Figure 4 As shown), that is, the transistor 20 in the memory cell 1 is turned on, and the read circuit 40 applies a pre-read voltage to one end of the capacitor 10 in the memory cell 1 through the plate line PL, thereby generating a potential difference across the two ends of the capacitor 10, and the memory cell 1 outputs a voltage signal through the bit line BL.

[0058] In step S12, the voltage signal outputted by the memory cell 1 is compared with the reference voltage VREF in the sense amplifier 30 as a sensing element, and a signal indicating whether the original storage data in the memory cell 1 is "0" or "1" is outputted according to the comparison result.

[0059] In step S13, it is determined whether the original storage data in the memory cell 1 is "0". If the determination result is "yes", that is, the original storage data in the memory cell 1 is "0", the process proceeds to step S14. If the determination result is "no", that is, the original storage data in the memory cell 1 is "1", the process proceeds to step S17.

[0060] In step S14, it is determined whether the data to be written into the memory cell 1 is "0". If the determination result is "yes", that is, the data "0" is to be written into the memory cell 1, the process proceeds to step S15. If the determination result is "no", that is, the data "1" is to be written into the memory cell 1, the process proceeds to step S18.

[0061] In step S15, according to the judgment results of the above steps S13 and S14, the original storage data in the memory cell 1 is "0" and the data "0" is to be written into the memory cell 1, therefore, Figure 4 The pre-read detection circuit 80 in the memory cell 1 turns on the write "1" circuit 60 and bypasses the write-back / write control circuit 70, that is, the write-back / write control circuit 70 does not work at this time, but the pre-read detection circuit 80 directly controls the write "1" circuit 60 to write data "1" to the memory cell 1. The write "1" circuit 60 applies a negative voltage difference across the capacitor element 10 in the memory cell 1 (that is, the plate corresponding to the plate line PL is at a low voltage or grounded, and the other plate is at a high voltage), so that the ferroelectric material in the capacitor element 10 changes to a storage state of logic "1".

[0062] After the write "1" operation is completed, Figure 5 Although not shown in the figure, at this time, the sense amplifier 30 through the pre-read operation will output a result indicating that the storage data of the memory cell 1 is "1", that is, the pre-read detection circuit 80 will obtain a pre-read result that the storage data is "1", so the pre-read detection circuit 80 disconnects the write "1" circuit 60 and restores the connection of the write-back / write control circuit 70. Then, in step S16, the write-back / write control circuit 70 connects the write "0" circuit 50 based on the output ("1") of the sense amplifier 30 and the fact that the data "0" is to be written in the memory cell 1, and performs a write "0" operation on the memory cell 1 to achieve the writing of the data "0". Thus, the "0-0" operation is completed.

[0063] go through Figure 5 In the process shown in FIG. 1 , when the original storage data in the memory cell 1 is “0” and the data “0” is to be written into the memory cell 1, the process does not directly go through pre-reading, writing “0” or writing back (according to FIG. 1 ). Figure 1A Instead of completing the "0-0" operation by inserting a write "1" operation after the pre-read operation and then performing a write "0" operation (as described later in the following text), the "0-0" operation is not completed. Figure 6 Through two write operations, the path on the hysteresis loop passes through the coercive field strength twice, so that the read and write operations can be balanced, the drift of the hysteresis loop can be suppressed, and the reliability of the ferroelectric memory can be improved.

[0064] Back to Figure 5 In step S17, since the original storage data in the memory cell 1 is "1", the pre-read detection circuit 80 will not connect the write "1" circuit 60. Therefore, the write-back / write control circuit 70 controls the write "0" circuit or the write "1" circuit to perform the corresponding write operation based on whether the data to be written is "0" or "1". That is, step S17 is the same as the conventional "1-1" and "1-0" operations, and the operation path on its hysteresis loop is also the same as Figure 1C (“1-0” operation: point C → point D → point A), Figure 1D(“1-1” operation: point C → point D → point A → point B → point C) is the same.

[0065] In step S18, since the original storage data in the memory cell 1 is "0" and "1" data is to be written, the pre-read detection circuit 80 does not connect the write "1" circuit 60, so the write-back / write control circuit 70 controls the write "1" circuit to perform the write "1" operation. That is, step S17 is the same as the conventional "0-1" operation, and the operation path on its hysteresis loop is also the same as Figure 1B (“0-1” operation: point A→point D→point A→point B→point C) is the same.

[0066] Figure 6 It is a schematic diagram of the "0-0" operation path of the hysteresis loop of the ferroelectric memory using the read-write equalization circuit and method involved in this embodiment. Figure 6 The horizontal axis, vertical axis, and letter labels shown in Figure 1A to Figure 1D The reference numerals indicated in the figure are the same, so their repeated description is omitted.

[0067] According to the read-write equalization circuit and method of the present embodiment, when the original storage data of the memory cell 1 is "0" and the data "0" is to be written into the memory cell 1, the operation path is from point A to point D after the pre-reading stage, the pre-reading voltage is removed and the path returns to point A, and then the write "1" operation is performed to make the operation path from point A to point B, and the path returns to point C after the write "1" voltage is removed, and then the conventional write "0" operation is performed to make the path reach point D, and finally return to point A, completing the writing of data "0". Specifically, when the original storage data of the memory cell 1 is "0" and the data "0" is to be written into the memory cell 1, the write "1" operation is inserted on the basis of the previous pre-reading, writing or writing back "0" operation, so that the "0-0" operation path is changed from point A→point D→point A to point A→point D→point A→point B→point C→point D→point A. There are two times in the middle of the operation path that pass through the coercive field strength -Ec and Ec, which are respectively in the middle of point A→point B and point C→point D. Thus, the conventional "0-0" operation path is avoided without any coercive field strength, so that the read and write operations can be balanced, and the drift of the hysteresis loop of the ferroelectric memory is suppressed, which is beneficial to improving the reliability of the ferroelectric memory.

[0068] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present disclosure, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present disclosure. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present disclosure, the various embodiments are not meant to be restrictive, but exemplary embodiments. In reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. A read-write equalization circuit based on a ferroelectric memory, which performs read and write operations on a ferroelectric memory capable of storing at least a first logic state and a second logic state, characterized in that: include: A read circuit, applying a pre-read voltage to the ferroelectric memory to perform a pre-read operation; A write circuit, which performs a write operation on the ferroelectric memory, including a first write circuit that performs a first write operation to make the ferroelectric memory store the first logic state, and a second write circuit that performs a second write operation to make the ferroelectric memory store the second logic state; A sensing device, sensing the ferroelectric memory and outputting a result of the pre-reading operation, i.e., a pre-reading result, to determine an original logic state stored in the ferroelectric memory; a control circuit, controlling the write circuit to perform the first write operation or the second write operation; as well as a pre-read detection circuit, detecting the pre-read result, and determining whether to turn on the second write circuit to perform the second write operation according to the pre-read result, In the case where the original logic state of the ferroelectric memory is the first logic state and the first write operation is to be performed on the ferroelectric memory, after the pre-read detection circuit turns on the second write circuit and makes it perform the second write operation, the control circuit controls the write circuit to perform the first write operation, thereby writing data corresponding to the first logic state into the ferroelectric memory, The first logic state corresponds to a logic "0", and the second logic state corresponds to a logic "1".

2. The read-write equalization circuit according to claim 1, characterized in that: One end of the pre-reading detection circuit is connected between the sensing device and the control circuit, and the other end is connected to the second writing circuit.

3. The read-write equalization circuit according to claim 1 or 2, characterized in that: During the period when the pre-read detection circuit turns on the second write circuit to perform the second write operation, the control circuit is bypassed.

4. The read-write equalization circuit according to claim 1 or 2, characterized in that: When the original logic state of the ferroelectric memory is the first logic state and the second write operation is to be performed on the ferroelectric memory, the control circuit controls the write circuit to perform the second write operation, thereby writing data corresponding to the second logic state to the ferroelectric memory.

5. The read-write equalization circuit according to claim 1 or 2, characterized in that: When the original logic state of the ferroelectric memory is the second logic state, the control circuit controls the write circuit to perform the first write operation or the second write operation, thereby writing data corresponding to the first logic state or the second logic state to the ferroelectric memory.

6. A ferroelectric memory, characterized in that: The read and write equalization circuit based on the ferroelectric memory as claimed in any one of claims 1 to 5 is used to perform read and write operations.

7. A read-write balance method based on a ferroelectric memory, performing read and write operations on a ferroelectric memory capable of storing at least a first logic state and a second logic state, characterized in that: include: The read circuit applies a pre-read voltage to the ferroelectric memory to perform a pre-read operation; The sensing device senses the ferroelectric memory and outputs the result of the pre-reading operation, i.e., the pre-reading result, to determine the original logic state stored in the ferroelectric memory; The control circuit controls the write circuit to perform a write operation on the ferroelectric memory, wherein the write circuit includes a first write circuit that performs a first write operation to make the ferroelectric memory store the first logic state, and a second write circuit that performs a second write operation to make the ferroelectric memory store the second logic state; as well as The pre-read detection circuit detects the pre-read result and determines whether to turn on the second write circuit to perform the second write operation according to the pre-read result. In the case where the original logic state of the ferroelectric memory is the first logic state and the first write operation is to be performed on the ferroelectric memory, after the pre-read detection circuit turns on the second write circuit and makes it perform the second write operation, the control circuit controls the write circuit to perform the first write operation, thereby writing data corresponding to the first logic state into the ferroelectric memory, The first logic state corresponds to a logic "0", and the second logic state corresponds to a logic "1".

8. The read-write balance method according to claim 7, characterized in that: One end of the pre-reading detection circuit is connected between the sensing device and the control circuit, and the other end is connected to the second writing circuit.

9. The read-write balance method according to claim 7, characterized in that: During the period when the pre-read detection circuit turns on the second write circuit to perform the second write operation, the control circuit is bypassed.

10. The read-write balance method according to claim 7, characterized in that: When the original logic state of the ferroelectric memory is the first logic state and the second write operation is to be performed on the ferroelectric memory, the control circuit controls the write circuit to perform the second write operation, thereby writing data corresponding to the second logic state to the ferroelectric memory.

11. The read-write balance method according to claim 7, characterized in that: When the original logic state of the ferroelectric memory is the second logic state, the control circuit controls the write circuit to perform the first write operation or the second write operation, thereby writing data corresponding to the first logic state or the second logic state to the ferroelectric memory.

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