A low power consumption LDO circuit

Abstract

The present invention relates to the field of LDO technology, and specifically discloses a low-power LDO circuit, including: a main amplifier, provided with a positive input port, a first negative input port, a second negative input port and an output port, the positive input port being a reference voltage input port; an NMOS driving tube, the gate of which is electrically connected to the output port, and the source of which is electrically connected to the load capacitor as the LDO output; a slow feedback unit, which forms a slow feedback path together with the LDO output and the first negative input port; and a fast feedback unit, which forms a fast feedback path together with the LDO output, the gate of the NMOS driving tube and the second negative input port, and the fast feedback path is used to improve the stability of the LDO circuit. The present invention ensures the accuracy of the LDO output voltage, improves the stability of the LDO circuit, saves the cost of correction and compensation outside the chip, and has strong practicality by simultaneously forming a slow feedback path and a fast feedback path in the main amplifier and the NMOS driving tube.

Description

Technical Field

[0001] The present invention relates to the technical field of LDO, and in particular to a low power consumption LDO circuit. Background Art

[0002] LDO is a linear regulator. The existing mainstream linear regulator uses MOS power transistors working in the linear region, connected in the form of source followers to provide relatively strong driving capabilities and the lowest voltage drop. However, when the LDO works in a low-power state, the MOS power transistor and the load capacitor will form a low-frequency pole, resulting in reduced circuit stability, which in turn affects the normal operation of downstream circuits. Furthermore, existing LDOs often cannot take into account both accuracy and stability. In order to achieve the expected indicators, it is usually necessary to perform corrections and compensation outside the chip, which increases the cost of off-chip components and also increases the limited area of ​​the PCB board.

[0003] Based on this technical background, the present invention studies a low power consumption LDO circuit. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention proposes a low-power LDO circuit. In a low-power working state, a slow feedback path and a fast feedback path are simultaneously formed in a main amplifier and an NMOS driver tube, thereby ensuring the accuracy of the LDO output voltage, improving the stability of the LDO circuit, saving the cost of off-chip correction and compensation, and having strong practicality.

[0005] In order to achieve the above object, the present invention provides a low power consumption LDO circuit, comprising:

[0006] A main amplifier is provided with a positive input port, a first negative input port, a second negative input port and an output port, wherein the positive input port is a reference voltage input port;

[0007] An NMOS driving tube, the gate of which is electrically connected to the output port, and the source of which is electrically connected to the load capacitor as an LDO output;

[0008] A slow feedback unit, which forms a slow feedback path together with the LDO output and the first negative input port, wherein the slow feedback path is used to improve the accuracy of the LDO output voltage;

[0009] The fast feedback unit forms a fast feedback path together with the LDO output, the gate of the NMOS driving tube and the second negative input port, and the fast feedback path is used to improve the stability of the LDO circuit.

[0010] The beneficial effects of the present invention include:

[0011] (1) The low-power LDO circuit proposed in the present invention, under the low-power working state, forms a slow feedback path and a fast feedback path in the main amplifier and the NMOS driver tube at the same time, thereby ensuring the accuracy of the LDO output voltage, improving the stability of the LDO circuit, saving the cost of off-chip correction and compensation, and having strong practicality.

[0012] (2) The low-power LDO circuit proposed in the present invention provides a desired gate voltage for the resistor PMOS tube by setting a bias circuit, thereby ensuring that the resistor PMOS tube operates in a linear region, providing a stable zero-adjusting resistor value, and achieving the purpose of achieving a larger isolation resistor value with a smaller area.

[0013] (3) The low-power LDO circuit proposed in the present invention has an output stage composed of an NMOS driver tube and a PMOS driver tube, which can increase the LDO output current sinking and sourcing capabilities, thereby improving the overall driving capability of the LDO.

[0014] (4) In the low-power LDO circuit proposed by the present invention, the resistor PMOS tube works in the linear region as a fast feedback path formed by the zero adjustment resistor and the compensation capacitor, thereby ensuring the stability of the loop when driving a large load capacitor and reducing the thermal noise introduced by the resistor PMOS.

[0015] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0017] Figure 1 This is a schematic diagram of the overall structure of the low power consumption LDO circuit proposed by the present invention.

[0018] Figure 2 The figure is a schematic structural diagram of a specific implementation of the low power consumption LDO circuit proposed by the present invention.

[0019] Figure 3 This is a structural schematic diagram of another specific implementation of the low power consumption LDO circuit proposed by the present invention.

[0020] Figure 4 This is a schematic structural diagram of a third specific implementation manner of the low power consumption LDO circuit proposed by the present invention.

[0021] Description of reference numerals:

[0022] V REF-reference voltage, Mpn-NMOS driver, VDD-power supply, VSS-ground, FB_fast-fast feedback path, FB_slow-slow feedback path, V OUT -LDO output, Cload-load capacitor, Ra1-first resistor, Ra2-second resistor, Rz-compensation resistor, Cc-compensation capacitor, Mp0-second main PMOS tube, Mp1-first main PMOS tube, Mn0-positive NMOS input tube, Mn1_1-first negative NMOS input tube, Mn1_2-second negative NMOS input tube, Mn2-main NMOS tube, Mbp0-first bias PMOS tube, Mbp1-second bias PMOS tube, Mbn0-bias positive NMOS input tube, Mbn1-bias negative NMOS input tube, Mbn2-first bias drive NMOS tube, Mbn3-second bias drive driving NMOS tube, Mbp2-bias driving PMOS tube, Mbp3-third bias PMOS tube, Mbp4-fourth bias PMOS tube, Mbn4-first bias NMOS tube, Mbn5-second bias NMOS tube, Mpr0-resistance PMOS tube, Mpp-PMOS driving tube, α-first auxiliary amplifier gain, β-second auxiliary amplifier gain, k, m, n are the number of unit NMOS tubes contained in the positive NMOS input tube, the first negative NMOS input tube and the second negative NMOS input tube respectively, vb1-external PMOS bias input, vb2-external NMOS bias input, vbp-gate bias voltage. DETAILED DESCRIPTION

[0023] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0024] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0025] The present invention provides a low power consumption LDO circuit, such as Figure 1 As shown, including:

[0026] A main amplifier is provided with a positive input port, a first negative input port, a second negative input port and an output port, wherein the positive input port is a reference voltage input port;

[0027] NMOS driver tube Mpn, the gate is electrically connected to the output port, and the source serves as the LDO output V OUT electrically connected to a load capacitor Cload;

[0028] Slow feedback unit, with LDO output V OUT , and the first negative input port together form a slow feedback path FB_slow, which is used to increase the LDO output V OUT Voltage accuracy;

[0029] Fast feedback unit, with LDO output V OUT , the gate of the NMOS driving tube Mpn and the second negative input port together form a fast feedback path FB_fast, and the fast feedback path FB_fast is used to improve the stability of the LDO circuit.

[0030] In summary, in a low-power working state, the slow feedback path FB_slow and the fast feedback path FB_fast are simultaneously formed in the main amplifier and the NMOS driver tube Mpn, thereby ensuring that the LDO output V OUT The voltage accuracy improves the stability of the LDO circuit, saves the cost of off-chip correction and compensation, and has strong practicality.

[0031] According to the present invention, the slow feedback unit includes a first auxiliary amplifier, a first resistor Ra1 and a second resistor Ra2;

[0032] An output of the first auxiliary amplifier is electrically connected to the first negative input port;

[0033] One end of the first resistor Ra1 is connected to the LDO output V OUT The other end is electrically connected to one end of the second resistor Ra2 and the input of the first auxiliary amplifier;

[0034] The other end of the second resistor Ra2 is electrically connected to the ground.

[0035] According to the present invention, the slow feedback unit includes a first auxiliary amplifier and a PMOS driving tube Mpp;

[0036] An output of the first auxiliary amplifier is electrically connected to the first negative input port;

[0037] The source of the PMOS driver tube Mpp is connected to the input of the first auxiliary amplifier and the output of the LDO V OUT Electrical connection;

[0038] The drain of the PMOS driving tube Mpp is electrically connected to the ground.

[0039] In the present invention, the output stage composed of the NMOS drive tube Mpn and the PMOS drive tube Mpp can increase the LDO output V OUT The ability to sink and source current improves the overall driving capability of the LDO.

[0040] Preferably, the fast feedback unit comprises a second auxiliary amplifier, a compensation resistor Rz and a compensation capacitor Cc;

[0041] An output of the second auxiliary amplifier is electrically connected to the second negative input port;

[0042] One end of the compensation resistor Rz and one end of the compensation capacitor Cc are electrically connected to the input of the second auxiliary amplifier at the same time;

[0043] The other end of the compensation resistor Rz is electrically connected to the input of the first auxiliary amplifier;

[0044] The other end of the compensation capacitor Cc is electrically connected to the gate of the NMOS driving tube Mpn.

[0045] Preferably, the compensation resistor Rz is a resistor PMOS tube Mpr0;

[0046] The resistor PMOS tube Mpr0 works in the linear region;

[0047] The source of the resistor PMOS tube Mpr0 is electrically connected to the input of the second auxiliary amplifier, and the drain is electrically connected to the input of the first auxiliary amplifier, or,

[0048] The source of the resistor PMOS tube Mpr0 is electrically connected to the input of the first auxiliary amplifier, and the drain is electrically connected to the input of the second auxiliary amplifier.

[0049] In the present invention, by setting a bias circuit, a desired gate voltage is provided for the resistor PMOS tube Mpr0, thereby ensuring that the resistor PMOS tube Mpr0 operates in a linear region, providing a stable zero-adjusting resistance value, and achieving the purpose of achieving a larger isolation resistance value with a smaller area.

[0050] According to the present invention, the main amplifier, the first auxiliary amplifier and the second auxiliary amplifier together form an overall amplification structure of the LDO circuit, and the overall amplification structure includes:

[0051] The main PMOS tube includes a first main PMOS tube Mp1 and a second main PMOS tube Mp0, wherein the gates of the first main PMOS tube Mp1 and the second main PMOS tube Mp0 are electrically connected to each other to form a mirror structure, the sources are both electrically connected to a power supply, and the drain of the first main PMOS tube Mp1 is electrically connected to its own gate;

[0052] The main input tubes include a positive NMOS input tube Mn0, a first negative NMOS input tube Mn1_1, and a second negative NMOS input tube Mn1_2, wherein the drain of the positive NMOS input tube Mn0 is electrically connected to the drain of the first main PMOS tube Mp1, and the drains of the first negative NMOS input tube Mn1_1 and the second negative NMOS input tube Mn1_2 are both electrically connected to the drain of the second main PMOS tube Mp0;

[0053] The main NMOS transistor Mn2 has a source electrically connected to the ground, and a drain electrically connected to the sources of the positive NMOS input transistor Mn0, the first negative NMOS input transistor Mn1_1, and the second negative NMOS input transistor Mn1_2.

[0054] In the present invention, the resistor PMOS tube Mpr0 works in the linear region as a zero adjustment resistor and forms a fast feedback path FB_fast together with the compensation capacitor Cc, which ensures the stability of the loop when driving a large load capacitor Cload and reduces the thermal noise introduced by the resistor PMOS.

[0055] According to the present invention, the gate input of the positive NMOS input tube Mn0 serves as the positive input port;

[0056] The gate input of the first negative NMOS input tube Mn1_1 serves as the input of the first auxiliary amplifier;

[0057] The gate input of the second negative NMOS input tube Mn1_2 serves as the input of the second auxiliary amplifier.

[0058] Preferably, a bias circuit is also included;

[0059] The bias circuit is used to provide a gate bias voltage vbp for the resistor PMOS tube Mpr0 and / or the PMOS driving tube Mpp.

[0060] Preferably, the bias circuit comprises:

[0061] A bias PMOS tube, comprising a first bias PMOS tube Mbp0 and a second bias PMOS tube Mbp1, wherein the gates of the first bias PMOS tube Mbp0 and the second bias PMOS tube Mbp1 are electrically connected to each other to form a mirror structure, the sources are both electrically connected to a power supply, and the drain of the first bias PMOS tube Mbp0 is electrically connected to its own gate;

[0062] The bias input tube includes a bias positive NMOS input tube Mbn0 and a bias negative NMOS input tube Mbn1. The drain of the bias positive NMOS input tube Mbn0 is electrically connected to the drain of the first bias PMOS tube Mbp0, and the gate is connected to the reference voltage V REF The drain of the biased negative NMOS input tube Mbn1 is electrically connected to its own gate and the drain of the second biased PMOS tube Mbp1;

[0063] The bias driving tube comprises a first bias driving NMOS tube Mbn2, a second bias driving NMOS tube Mbn3 and a bias driving PMOS tube Mbp2, wherein the sources of the first bias driving NMOS tube Mbn2 and the second bias driving NMOS tube Mbn3 are both electrically connected to the ground, the drain of the first bias driving NMOS tube Mbn2 is electrically connected to the sources of the bias positive NMOS input tube Mbn0 and the bias negative NMOS input tube Mbn1 at the same time, the drain of the second bias driving NMOS tube Mbn3 is electrically connected to the drain of the bias driving PMOS tube Mbp2, and the source of the bias driving PMOS tube Mbp2 is electrically connected to the gate of the bias negative NMOS input tube Mbn1;

[0064] The drain of the bias-driven PMOS tube Mbp2 is electrically connected to its own gate, and its gate voltage serves as the gate bias voltage vbp;

[0065] The gates of the main NMOS transistor Mn2, the first bias driving NMOS transistor Mbn2, and the second bias driving NMOS transistor Mbn3 are all electrically connected to the external NMOS bias input vb2.

[0066] According to the present invention, the bias circuit comprises:

[0067] A third bias PMOS transistor Mbp3, whose source is electrically connected to the power supply and whose gate is electrically connected to the external PMOS bias input vb1;

[0068] The first bias NMOS tube Mbn4 has a drain electrically connected to the drain of the third bias PMOS tube Mbp3, a gate electrically connected to its own drain, and a source electrically connected to the drain of the main NMOS tube Mn2;

[0069] The fourth bias PMOS transistor Mbp4 has a source electrically connected to the gate of the first bias NMOS transistor Mbn4, a gate electrically connected to its own drain, and a gate voltage thereof serving as a gate bias voltage vbp;

[0070] A second bias NMOS transistor Mbn5, whose source is electrically connected to the ground, and whose drain is electrically connected to the drain of the fourth bias PMOS transistor Mbp4;

[0071] The gates of the main NMOS transistor Mn2 and the second bias NMOS transistor Mbn5 are both electrically connected to the external NMOS bias input vb2.

[0072] The present invention will be described in more detail below through specific embodiments.

[0073] Example 1

[0074] like Figure 2 As shown, this embodiment provides a low power consumption LDO circuit, including:

[0075] A main amplifier is provided with a positive input port, a first negative input port, a second negative input port and an output port, wherein the positive input port is a reference voltage input port;

[0076] NMOS driver tube Mpn, the gate is electrically connected to the output port, and the source serves as the LDO output V OUT electrically connected to a load capacitor Cload;

[0077] Slow feedback unit, with LDO output V OUT , and the first negative input port together form a slow feedback path FB_slow, which is used to increase the LDO output V OUT Voltage accuracy;

[0078] Fast feedback unit, with LDO output V OUT , the gate of the NMOS driving tube Mpn and the second negative input port together form a fast feedback path FB_fast, and the fast feedback path FB_fast is used to improve the stability of the LDO circuit;

[0079] In this embodiment, the slow feedback unit includes a first auxiliary amplifier, a first resistor Ra1 and a second resistor Ra2;

[0080] An output of the first auxiliary amplifier is electrically connected to the first negative input port;

[0081] One end of the first resistor Ra1 is connected to the LDO output V OUT The other end is electrically connected to one end of the second resistor Ra2 and the input of the first auxiliary amplifier;

[0082] The other end of the second resistor Ra2 is electrically connected to the ground;

[0083] In this embodiment, the fast feedback unit includes a second auxiliary amplifier, a compensation resistor Rz and a compensation capacitor Cc;

[0084] An output of the second auxiliary amplifier is electrically connected to the second negative input port;

[0085] One end of the compensation resistor Rz and one end of the compensation capacitor Cc are electrically connected to the input of the second auxiliary amplifier at the same time;

[0086] The other end of the compensation resistor Rz is electrically connected to the input of the first auxiliary amplifier;

[0087] The other end of the compensation capacitor Cc is electrically connected to the gate of the NMOS driving tube Mpn;

[0088] The compensation resistor Rz is a resistor PMOS tube Mpr0;

[0089] The resistor PMOS tube Mpr0 works in the linear region;

[0090] The source of the resistor PMOS tube Mpr0 is electrically connected to the input of the first auxiliary amplifier, and the drain is electrically connected to the input of the second auxiliary amplifier;

[0091] In this embodiment, the main amplifier, the first auxiliary amplifier and the second auxiliary amplifier together form an overall amplification structure of the LDO circuit, and the overall amplification structure includes:

[0092] The main PMOS tube includes a first main PMOS tube Mp1 and a second main PMOS tube Mp0, wherein the gates of the first main PMOS tube Mp1 and the second main PMOS tube Mp0 are electrically connected to each other to form a mirror structure, the sources are both electrically connected to a power supply, and the drain of the first main PMOS tube Mp1 is electrically connected to its own gate;

[0093] The main input tubes include a positive NMOS input tube Mn0, a first negative NMOS input tube Mn1_1, and a second negative NMOS input tube Mn1_2, wherein the drain of the positive NMOS input tube Mn0 is electrically connected to the drain of the first main PMOS tube Mp1, and the drains of the first negative NMOS input tube Mn1_1 and the second negative NMOS input tube Mn1_2 are both electrically connected to the drain of the second main PMOS tube Mp0;

[0094] The main NMOS transistor Mn2 has a source electrically connected to the ground, and a drain electrically connected to the sources of the positive NMOS input transistor Mn0, the first negative NMOS input transistor Mn1_1, and the second negative NMOS input transistor Mn1_2;

[0095] In this embodiment, the gate input of the positive NMOS input tube Mn0 serves as the positive input port;

[0096] The gate input of the first negative NMOS input tube Mn1_1 serves as the input of the first auxiliary amplifier;

[0097] The gate input of the second negative NMOS input tube Mn1_2 serves as the input of the second auxiliary amplifier.

[0098] In this embodiment, a bias circuit is also included;

[0099] The bias circuit is used to provide a gate bias voltage vbp for the resistor PMOS tube Mpr0;

[0100] In this embodiment, the bias circuit includes:

[0101] A bias PMOS tube, comprising a first bias PMOS tube Mbp0 and a second bias PMOS tube Mbp1, wherein the gates of the first bias PMOS tube Mbp0 and the second bias PMOS tube Mbp1 are electrically connected to each other to form a mirror structure, the sources are both electrically connected to a power supply, and the drain of the first bias PMOS tube Mbp0 is electrically connected to its own gate;

[0102] The bias input tube includes a bias positive NMOS input tube Mbn0 and a bias negative NMOS input tube Mbn1. The drain of the bias positive NMOS input tube Mbn0 is electrically connected to the drain of the first bias PMOS tube Mbp0, and the gate is connected to the reference voltage V REF The drain of the biased negative NMOS input tube Mbn1 is electrically connected to its own gate and the drain of the second biased PMOS tube Mbp1;

[0103] The bias driving tube comprises a first bias driving NMOS tube Mbn2, a second bias driving NMOS tube Mbn3 and a bias driving PMOS tube Mbp2, wherein the sources of the first bias driving NMOS tube Mbn2 and the second bias driving NMOS tube Mbn3 are both electrically connected to the ground, the drain of the first bias driving NMOS tube Mbn2 is electrically connected to the sources of the bias positive NMOS input tube Mbn0 and the bias negative NMOS input tube Mbn1 at the same time, the drain of the second bias driving NMOS tube Mbn3 is electrically connected to the drain of the bias driving PMOS tube Mbp2, and the source of the bias driving PMOS tube Mbp2 is electrically connected to the gate of the bias negative NMOS input tube Mbn1;

[0104] The drain of the bias-driven PMOS tube Mbp2 is electrically connected to its own gate, and its gate voltage serves as the gate bias voltage vbp;

[0105] The gates of the main NMOS transistor Mn2, the first bias driving NMOS transistor Mbn2, and the second bias driving NMOS transistor Mbn3 are all electrically connected to the external NMOS bias input vb2.

[0106] In this embodiment, the input pair is composed of a positive NMOS input tube Mn0, a first negative NMOS input tube Mn1_1, and a second negative NMOS input tube / Mn1_2. The NMOS driving tube Mpn forms an output stage that can provide a stronger output current capability. The first resistor Ra1 and the second resistor Ra2 determine the feedback coefficient. The resistor PMOS tube Mpr0 is designed in the linear region as a zero adjustment resistor.

[0107] In this embodiment, the feedback path is designed as two feedback paths with different gains. The advantage of this design is that the slow feedback path FB_slow is used as the main feedback path to ensure that the LDO output V OUTThe fast feedback path FB_fast forms an Rz structure through the compensation capacitor Cc and the resistor PMOS tube Mpr0 to ensure that the loop can stably drive the large load capacitor Cload. At the same time, the gain of the fast feedback path FB_fast is designed to be α=m / m+n, and the gain of the slow feedback path FB_slow is set to β=n / m+n. This has the advantage of reducing the thermal noise introduced by the resistor PMOS tube, which is equivalent to reducing the resistance value of the resistor PMOS tube by (α / β)^2 times;

[0108] The bias circuit is used to provide a gate bias voltage vbp for the resistor PMOS tube Mpr0. The advantage of this design is that the resistor PMOS tube Mpr0 is always biased at V REF Under the condition of -Vgsn (Vgsn is the gate-source voltage of the resistor PMOS tube Mpr0), the stable zero-adjusting resistance value of the resistor PMOS tube Mpr0 is ensured, so that a larger isolation resistance value can be achieved with a smaller area.

[0109] Example 2

[0110] like Figure 3 As shown, this embodiment provides a low power consumption LDO circuit, including:

[0111] A main amplifier is provided with a positive input port, a first negative input port, a second negative input port and an output port, wherein the positive input port is a reference voltage input port;

[0112] NMOS driver tube Mpn, the gate is electrically connected to the output port, and the source serves as the LDO output V OUT electrically connected to a load capacitor Cload;

[0113] Slow feedback unit, with LDO output V OUT , and the first negative input port together form a slow feedback path FB_slow, which is used to increase the LDO output V OUT Voltage accuracy;

[0114] Fast feedback unit, with LDO output V OUT , the gate of the NMOS driving tube Mpn and the second negative input port together form a fast feedback path FB_fast, and the fast feedback path FB_fast is used to improve the stability of the LDO circuit;

[0115] In this embodiment, the slow feedback unit includes a first auxiliary amplifier, a first resistor Ra1 and a second resistor Ra2;

[0116] An output of the first auxiliary amplifier is electrically connected to the first negative input port;

[0117] One end of the first resistor Ra1 is connected to the LDO output V OUTThe other end is electrically connected to one end of the second resistor Ra2 and the input of the first auxiliary amplifier;

[0118] The other end of the second resistor Ra2 is electrically connected to the ground;

[0119] In this embodiment, the fast feedback unit includes a second auxiliary amplifier, a compensation resistor Rz and a compensation capacitor Cc;

[0120] An output of the second auxiliary amplifier is electrically connected to the second negative input port;

[0121] One end of the compensation resistor Rz and one end of the compensation capacitor Cc are electrically connected to the input of the second auxiliary amplifier at the same time;

[0122] The other end of the compensation resistor Rz is electrically connected to the input of the first auxiliary amplifier;

[0123] The other end of the compensation capacitor Cc is electrically connected to the gate of the NMOS driving tube Mpn;

[0124] The compensation resistor Rz is a resistor PMOS tube Mpr0;

[0125] The resistor PMOS tube Mpr0 works in the linear region;

[0126] The source of the resistor PMOS tube Mpr0 is electrically connected to the input of the first auxiliary amplifier, and the drain is electrically connected to the input of the second auxiliary amplifier;

[0127] In this embodiment, the main amplifier, the first auxiliary amplifier and the second auxiliary amplifier together form an overall amplification structure of the LDO circuit, and the overall amplification structure includes:

[0128] The main PMOS tube includes a first main PMOS tube Mp1 and a second main PMOS tube Mp0, wherein the gates of the first main PMOS tube Mp1 and the second main PMOS tube Mp0 are electrically connected to each other to form a mirror structure, the sources are both electrically connected to a power supply, and the drain of the first main PMOS tube Mp1 is electrically connected to its own gate;

[0129] The main input tubes include a positive NMOS input tube Mn0, a first negative NMOS input tube Mn1_1, and a second negative NMOS input tube Mn1_2, wherein the drain of the positive NMOS input tube Mn0 is electrically connected to the drain of the first main PMOS tube Mp1, and the drains of the first negative NMOS input tube Mn1_1 and the second negative NMOS input tube Mn1_2 are both electrically connected to the drain of the second main PMOS tube Mp0;

[0130] The main NMOS transistor Mn2 has a source electrically connected to the ground, and a drain electrically connected to the sources of the positive NMOS input transistor Mn0, the first negative NMOS input transistor Mn1_1, and the second negative NMOS input transistor Mn1_2;

[0131] In this embodiment, the gate input of the positive NMOS input tube Mn0 serves as the positive input port;

[0132] The gate input of the first negative NMOS input tube Mn1_1 serves as the input of the first auxiliary amplifier;

[0133] The gate input of the second negative NMOS input tube Mn1_2 serves as the input of the second auxiliary amplifier.

[0134] In this embodiment, a bias circuit is also included;

[0135] The bias circuit is used to provide a gate bias voltage vbp for the resistor PMOS tube Mpr0;

[0136] In this embodiment, the bias circuit includes:

[0137] A third bias PMOS transistor Mbp3, whose source is electrically connected to the power supply and whose gate is electrically connected to the external PMOS bias input vb1;

[0138] The first bias NMOS tube Mbn4 has a drain electrically connected to the drain of the third bias PMOS tube Mbp3, a gate electrically connected to its own drain, and a source electrically connected to the drain of the main NMOS tube Mn2;

[0139] The fourth bias PMOS transistor Mbp4 has a source electrically connected to the gate of the first bias NMOS transistor Mbn4, a gate electrically connected to its own drain, and a gate voltage thereof serving as a gate bias voltage vbp;

[0140] A second bias NMOS transistor Mbn5, whose source is electrically connected to the ground, and whose drain is electrically connected to the drain of the fourth bias PMOS transistor Mbp4;

[0141] The gates of the main NMOS transistor Mn2 and the second bias NMOS transistor Mbn5 are both electrically connected to the external NMOS bias input vb2.

[0142] In this embodiment, the input pair is composed of a positive NMOS input tube Mn0, a first negative NMOS input tube Mn1_1, and a second negative NMOS input tube / Mn1_2. The NMOS driving tube Mpn forms an output stage that can provide a stronger output current capability. The first resistor Ra1 and the second resistor Ra2 determine the feedback coefficient. The resistor PMOS tube Mpr0 is designed in the linear region as a zero adjustment resistor.

[0143] In this embodiment, the feedback path is designed as two feedback paths with different gains. The advantage of this design is that the slow feedback path FB_slow is used as the main feedback path to ensure that the LDO output V OUTThe fast feedback path FB_fast forms an Rz structure through the compensation capacitor Cc and the resistor PMOS tube Mpr0 to ensure that the loop can stably drive the large load capacitor Cload. At the same time, the gain of the fast feedback path FB_fast is designed to be α=m / m+n, and the gain of the slow feedback path FB_slow is set to β=n / m+n. This has the advantage of reducing the thermal noise introduced by the resistor PMOS tube, which is equivalent to reducing the resistance value of the resistor PMOS tube by (α / β)^2 times;

[0144] The third bias PMOS transistor Mbp3, the first bias NMOS transistor Mbn4, the fourth bias PMOS transistor Mbp4 and the second bias NMOS transistor Mbn5 form a bias circuit of the resistor PMOS transistor Mpr0. The advantage of this design is that the resistor PMOS transistor Mpr0 is always biased at V REF Under the condition of -Vgsn (Vgsn is the gate-source voltage of the resistor PMOS tube Mpr0), the stable zero-adjusting resistance value of the resistor PMOS tube Mpr0 is ensured, so that a larger isolation resistance value can be achieved with a smaller area.

[0145] Example 3

[0146] like Figure 4 As shown, this embodiment provides a low power consumption LDO circuit, including:

[0147] A main amplifier is provided with a positive input port, a first negative input port, a second negative input port and an output port, wherein the positive input port is a reference voltage input port;

[0148] NMOS driver tube Mpn, the gate is electrically connected to the output port, and the source serves as the LDO output V OUT electrically connected to a load capacitor Cload;

[0149] Slow feedback unit, with LDO output V OUT , and the first negative input port together form a slow feedback path FB_slow, which is used to increase the LDO output V OUT Voltage accuracy;

[0150] Fast feedback unit, with LDO output V OUT , the gate of the NMOS driving tube Mpn and the second negative input port together form a fast feedback path FB_fast, and the fast feedback path FB_fast is used to improve the stability of the LDO circuit;

[0151] In this embodiment, the slow feedback unit includes a first auxiliary amplifier and a PMOS driving tube Mpp;

[0152] An output of the first auxiliary amplifier is electrically connected to the first negative input port;

[0153] The source of the PMOS driver tube Mpp is connected to the input of the first auxiliary amplifier and the output of the LDO V OUT Electrical connection;

[0154] The drain of the PMOS driver tube Mpp is electrically connected to the ground;

[0155] In this embodiment, the fast feedback unit includes a second auxiliary amplifier, a compensation resistor Rz and a compensation capacitor Cc;

[0156] An output of the second auxiliary amplifier is electrically connected to the second negative input port;

[0157] One end of the compensation resistor Rz and one end of the compensation capacitor Cc are electrically connected to the input of the second auxiliary amplifier at the same time;

[0158] The other end of the compensation resistor Rz is electrically connected to the input of the first auxiliary amplifier;

[0159] The other end of the compensation capacitor Cc is electrically connected to the gate of the NMOS driving tube Mpn;

[0160] In this embodiment, the compensation resistor Rz is a resistor PMOS tube Mpr0;

[0161] The resistor PMOS tube Mpr0 works in the linear region;

[0162] The source of the resistor PMOS tube Mpr0 is electrically connected to the input of the second auxiliary amplifier, and the drain is electrically connected to the input of the first auxiliary amplifier;

[0163] In this embodiment, the main amplifier, the first auxiliary amplifier and the second auxiliary amplifier together form an overall amplification structure of the LDO circuit, and the overall amplification structure includes:

[0164] The main PMOS tube includes a first main PMOS tube Mp1 and a second main PMOS tube Mp0, wherein the gates of the first main PMOS tube Mp1 and the second main PMOS tube Mp0 are electrically connected to each other to form a mirror structure, the sources are both electrically connected to a power supply, and the drain of the first main PMOS tube Mp1 is electrically connected to its own gate;

[0165] The main input tubes include a positive NMOS input tube Mn0, a first negative NMOS input tube Mn1_1, and a second negative NMOS input tube Mn1_2, wherein the drain of the positive NMOS input tube Mn0 is electrically connected to the drain of the first main PMOS tube Mp1, and the drains of the first negative NMOS input tube Mn1_1 and the second negative NMOS input tube Mn1_2 are both electrically connected to the drain of the second main PMOS tube Mp0;

[0166] The main NMOS transistor Mn2 has a source electrically connected to the ground, and a drain electrically connected to the sources of the positive NMOS input transistor Mn0, the first negative NMOS input transistor Mn1_1, and the second negative NMOS input transistor Mn1_2;

[0167] In this embodiment, the gate input of the positive NMOS input tube Mn0 serves as the positive input port;

[0168] The gate input of the first negative NMOS input tube Mn1_1 serves as the input of the first auxiliary amplifier;

[0169] The gate input of the second negative NMOS input tube Mn1_2 serves as the input of the second auxiliary amplifier;

[0170] In this embodiment, a bias circuit is also included;

[0171] The bias circuit is used to provide a gate bias voltage vbp for the resistor PMOS tube Mpr0 and the PMOS driver tube Mpp.

[0172] In this embodiment, the bias circuit includes:

[0173] A third bias PMOS transistor Mbp3, whose source is electrically connected to the power supply and whose gate is electrically connected to the external PMOS bias input vb1;

[0174] The first bias NMOS tube Mbn4 has a drain electrically connected to the drain of the third bias PMOS tube Mbp3, a gate electrically connected to its own drain, and a source electrically connected to the drain of the main NMOS tube Mn2;

[0175] The fourth bias PMOS transistor Mbp4 has a source electrically connected to the gate of the first bias NMOS transistor Mbn4, a gate electrically connected to its own drain, and a gate voltage thereof serving as a gate bias voltage vbp;

[0176] A second bias NMOS transistor Mbn5, whose source is electrically connected to the ground, and whose drain is electrically connected to the drain of the fourth bias PMOS transistor Mbp4;

[0177] The gates of the main NMOS transistor Mn2 and the second bias NMOS transistor Mbn5 are both electrically connected to the external NMOS bias input vb2.

[0178] In this embodiment, the input pair consists of a positive NMOS input tube Mn0, a first negative NMOS input tube Mn1_1 and a second negative NMOS input tube / Mn1_2. The output stage composed of the NMOS driving tube Mpn and the PMOS driving tube Mpp can provide the ability to sink and source current. The resistor PMOS tube Mpr0 is designed in the linear region as a zero adjustment resistor to ensure the stability of the loop together with the compensation capacitor Cc.

[0179] In this embodiment, the feedback path is designed to be two feedback paths with different gains. The advantage of this design is that the slow feedback path FB_slow is used as the main feedback path to ensure that the LDO output V OUT The fast feedback path FB_fast forms an Rz structure through the compensation capacitor Cc and the resistor PMOS tube Mpr0 to ensure that the loop can stably drive the large load capacitor Cload. At the same time, the gain of the fast feedback path FB_fast is designed to be α=m / m+n. This has the advantage of reducing the thermal noise introduced by the resistor PMOS tube.

[0180] The third bias PMOS transistor Mbp3, the first bias NMOS transistor Mbn4, the fourth bias PMOS transistor Mbp4 and the second bias NMOS transistor Mbn5 form a bias circuit of the resistor PMOS transistor Mpr0. The advantage of this design is that the resistor PMOS transistor Mpr0 is always biased at V REF -Vgsn (Vgsn is the gate-source voltage of the resistor PMOS tube Mpr0) condition, the stable zero-adjusting resistance value of the resistor PMOS tube Mpr0 is guaranteed, so that a larger isolation resistance value can be achieved with a smaller area, and at the same time, a stable bias voltage is provided for the PMOS driving tube Mpp.

[0181] The low-power LDO circuit proposed in the embodiment of the present invention, under the low-power working state, ensures the accuracy of the LDO output voltage by simultaneously forming a slow feedback path and a fast feedback path in the main amplifier and the NMOS driving tube, improves the stability of the LDO circuit, saves the cost of off-chip correction and compensation, and has strong practicality.

[0182] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A low power consumption LDO circuit, characterized in that: include: A main amplifier is provided with a positive input port, a first negative input port, a second negative input port and an output port, wherein the positive input port is a reference voltage input port; An NMOS driving tube, the gate of which is electrically connected to the output port, and the source of which is electrically connected to the load capacitor as an LDO output; A slow feedback unit, which forms a slow feedback path together with the LDO output and the first negative input port, wherein the slow feedback path is used to improve the accuracy of the LDO output voltage; A fast feedback unit, which forms a fast feedback path together with the LDO output, the gate of the NMOS driving tube and the second negative input port, wherein the fast feedback path is used to improve the stability of the LDO circuit; The slow feedback unit includes a first auxiliary amplifier and a PMOS driving tube; The output of the first auxiliary amplifier is electrically connected to the first negative input port; The source of the PMOS driving tube is electrically connected to the input of the first auxiliary amplifier and the output of the LDO at the same time; The drain of the PMOS driving tube is electrically connected to the ground; The fast feedback unit includes a second auxiliary amplifier, a compensation resistor and a compensation capacitor; The output of the second auxiliary amplifier is electrically connected to the second negative input port; One end of the compensation resistor and one end of the compensation capacitor are electrically connected to the input of the second auxiliary amplifier at the same time; The other end of the compensation resistor is electrically connected to the input of the first auxiliary amplifier; The other end of the compensation capacitor is electrically connected to the gate of the NMOS driving tube; The compensation resistor is a PMOS resistor; The resistor PMOS tube operates in the linear region; The source of the resistor PMOS tube is electrically connected to the input of the second auxiliary amplifier, and the drain is electrically connected to the input of the first auxiliary amplifier, or, The source of the resistor PMOS tube is electrically connected to the input of the first auxiliary amplifier, and the drain is electrically connected to the input of the second auxiliary amplifier.

2. The LDO circuit according to claim 1, characterized in that: The slow feedback unit includes a first auxiliary amplifier, a first resistor and a second resistor; The output of the first auxiliary amplifier is electrically connected to the first negative input port; One end of the first resistor is electrically connected to the LDO output, and the other end is electrically connected to one end of the second resistor and the input of the first auxiliary amplifier; The other end of the second resistor is electrically connected to the ground.

3. The LDO circuit according to claim 1, characterized in that: The main amplifier, the first auxiliary amplifier and the second auxiliary amplifier together form an overall amplification structure of the LDO circuit, and the overall amplification structure includes: A main PMOS tube, comprising a first main PMOS tube and a second main PMOS tube, wherein the gates of the first main PMOS tube and the second main PMOS tube are electrically connected to each other to form a mirror structure, the sources are both electrically connected to a power supply, and the drain of the first main PMOS tube is electrically connected to its own gate; A main input tube, comprising a positive NMOS input tube, a first negative NMOS input tube and a second negative NMOS input tube, wherein the drain of the positive NMOS input tube is electrically connected to the drain of the first main PMOS tube, and the drains of the first negative NMOS input tube and the second negative NMOS input tube are both electrically connected to the drain of the second main PMOS tube; The main NMOS tube has a source electrically connected to the ground, and a drain electrically connected to the sources of the positive NMOS input tube, the first negative NMOS input tube and the second negative NMOS input tube.

4. The LDO circuit according to claim 3, characterized in that: The gate input of the positive NMOS input tube serves as the positive input port; The gate input of the first negative NMOS input tube serves as the input of the first auxiliary amplifier; The gate input of the second negative NMOS input tube serves as the input of the second auxiliary amplifier.

5. The LDO circuit according to claim 4, characterized in that: Also included is a bias circuit; The bias circuit is used to provide a gate bias voltage for the resistor PMOS tube and / or the PMOS driving tube.

6. The LDO circuit according to claim 5, characterized in that: The bias circuit comprises: A bias PMOS tube, comprising a first bias PMOS tube and a second bias PMOS tube, wherein the gates of the first bias PMOS tube and the second bias PMOS tube are electrically connected to each other to form a mirror structure, the sources are both electrically connected to a power supply, and the drain of the first bias PMOS tube is electrically connected to its own gate; A bias input tube, comprising a bias positive NMOS input tube and a bias negative NMOS input tube, wherein the drain of the bias positive NMOS input tube is electrically connected to the drain of the first bias PMOS tube, and the gate is electrically connected to a reference voltage, and the drain of the bias negative NMOS input tube is electrically connected to its own gate and the drain of the second bias PMOS tube at the same time; A bias driving tube, comprising a first bias driving NMOS tube, a second bias driving NMOS tube and a bias driving PMOS tube, wherein the sources of the first bias driving NMOS tube and the second bias driving NMOS tube are both electrically connected to the ground, the drain of the first bias driving NMOS tube is electrically connected to the sources of the bias positive NMOS input tube and the bias negative NMOS input tube at the same time, the drain of the second bias driving NMOS tube is electrically connected to the drain of the bias driving PMOS tube, and the source of the bias driving PMOS tube is electrically connected to the gate of the bias negative NMOS input tube; The drain of the bias-driven PMOS tube is electrically connected to its own gate, and its gate voltage serves as the gate bias voltage; The gates of the main NMOS tube, the first bias driving NMOS tube, and the second bias driving NMOS tube are all electrically connected to the external NMOS bias input.

7. The LDO circuit according to claim 5, characterized in that: The bias circuit comprises: A third bias PMOS tube, a source electrically connected to a power supply, and a gate electrically connected to an external PMOS bias input; A first bias NMOS tube, whose drain is electrically connected to the drain of the third bias PMOS tube, whose gate is electrically connected to its own drain, and whose source is electrically connected to the drain of the main NMOS tube; a fourth bias PMOS tube, whose source is electrically connected to the gate of the first bias NMOS tube, whose gate is electrically connected to its own drain, and whose gate voltage serves as the gate bias voltage; A second bias NMOS tube, whose source is electrically connected to the ground and whose drain is electrically connected to the drain of the fourth bias PMOS tube; The gates of the main NMOS tube and the second bias NMOS tube are both electrically connected to the external NMOS bias input.

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