A hash input circuit and data input method

Abstract

The present application provides a hash input circuit and a data input method. The hash input circuit provided by the present application includes a control unit and a plurality of input branches; the control unit is used to configure input parameters for each input branch, and the input parameters include algorithm configuration parameters and calculation parameters; if the length of the algorithm configuration parameter is less than a preset length, the input parameter also includes a redundant parameter, and the redundant parameter is used to fill the algorithm configuration parameter so that the length of the algorithm configuration parameter matches the preset length, so that the position and length of the calculation parameter in the input parameter received by each input branch are consistent. The problem of excessive resource consumption and insufficient flexibility of SPHINCS+ hardware implementation is solved, and efficient use of system resources is achieved.

Description

Technical Field

[0001] The present application relates to the field of information security, and in particular to a hash input circuit and a data input method. Background Art

[0002] Quantum computers equipped with Shor's algorithm can easily crack traditional RSA algorithms based on large integer factorization problems and ECC algorithms based on discrete logarithm problems, thus posing a huge threat to information security. Therefore, modern information security systems need new solutions to resist attacks from classical computers and quantum computers, namely post-quantum cryptography (PQC).

[0003] The National Institute of Standards and Technology of the United States launched the post-quantum cryptography solicitation project in 2016, publicly soliciting new generation encryption schemes from all over the world, striving to complete the formulation of the next generation of public key encryption and digital signature standards before the popularization of quantum computers. Since February 2016, a screening will be conducted every two years from the aspects of algorithm security, resource overhead and performance. By July 2022, in the final competition, only Kyber, Dilithium, Falcon and SPHINCS+ were selected from the 69 algorithms that initially passed the first round of screening and are about to be standardized. The first three of them are all lattice-based cryptographic primitives. Although lattice cryptography has the advantages of high performance and low overhead, its security has only been strictly proved in ideal lattices, and the security proof is incomplete. In contrast, the hash-based signature scheme SPHINCS+ can be strictly proved to be secure as long as the hash algorithm it selects is considered secure. In addition, the relatively low resource overhead and simple operation advantages of SPHINCS+ make it stand out among many alternative algorithms, and it is the only hash-based digital signature scheme among the selected schemes.

[0004] However, since the algorithm uses different data bit widths for its diverse security levels, its hardware implementation faces the challenges of high resource overhead and low flexibility. Summary of the invention

[0005] To solve the above problems, the present application provides a hash input circuit and a data input method, which can reduce the resource overhead of the circuit.

[0006] In a first aspect, the present application provides a hash input circuit, comprising: a control unit and multiple input branches; the control unit is used to configure input parameters for each input branch, the input parameters including algorithm configuration parameters and calculation parameters; if the length of the algorithm configuration parameters is less than a preset length, the input parameters also include redundant parameters, and the redundant parameters are used to fill the algorithm configuration parameters so that the length of the algorithm configuration parameters matches the preset length, so that the position and length of the calculation parameters in the input parameters received by each of the input branches are consistent.

[0007] In one embodiment, the multiple input branches are connected in series in sequence, the input branch located at the head end is connected to the control unit, and the control unit controls the multiple input branches to shift between groups to receive the input parameters from the control unit, and transmits the input parameters received for the first time to the input branch located at the end or the input branch located in the middle through the input branch located in the middle, so that each of the input branches receives one input parameter.

[0008] In one embodiment, the input branch includes: a plurality of shift registers connected in series in sequence; when the control circuit controls the input branch to receive the input parameters, the control circuit controls the plurality of shift registers in the input branch to shift and select redundant parameters in the input parameters, and stores the redundant parameters in the target shift register.

[0009] In one embodiment, the control unit controls the remaining shift registers in the input branch except the target shift register to output the parameters stored in the remaining shift registers.

[0010] In one embodiment, if the length of the algorithm configuration parameter is equal to a preset length, the input parameter does not include redundant parameters.

[0011] In one embodiment, the number of shift registers in the input branch is the greatest common factor of the length of the algorithm configuration parameter.

[0012] In one embodiment, it also includes: a memory and a data distribution branch

[0013] The data distribution branch includes a plurality of data distributors, one input end of the data distributor is connected to the memory, another input end is connected to the control unit, and the output end is connected to the input branch;

[0014] The memory is used to store loading parameters and transmit the loading parameters to the input branches in sequence.

[0015] In a second aspect, the present application provides a data input method based on a hash input circuit, wherein the hash input circuit includes any of the above hash input circuits, and the data input method includes:

[0016] Determine whether the length of the algorithm configuration parameter is less than the preset length;

[0017] If the length of the algorithm configuration parameter is less than the preset length, padding the algorithm configuration parameter with redundant parameters so that the length of the algorithm configuration parameter is equal to the preset length;

[0018] The calculation parameters are supplemented after the algorithm configuration parameters or after the redundant parameters to obtain input parameters, and the input parameters are transmitted to the input branch.

[0019] In one embodiment, transmitting the input parameter to the input branch comprises:

[0020] The control unit controls multiple input branches to perform inter-group shifting to receive the input parameters from the control unit, and transmits the input parameters received for the first time to the input branch at the end or the input branch in the middle through the input branch in the middle, so that each input branch receives one input parameter accordingly.

[0021] In one embodiment, transmitting the input parameter to the input branch comprises:

[0022] Controlling a plurality of shift registers in the input branch to shift and select redundant parameters in the input parameters, and storing the redundant parameters in a target shift register;

[0023] The remaining shift registers except the target shift register in the input branch are controlled to output the parameters stored in the remaining shift registers.

[0024] The beneficial effect of the present application is different from the prior art. The hash input circuit provided by the present application includes a control unit and multiple input branches; the control unit is used to configure input parameters for each input branch, and the input parameters include algorithm configuration parameters and calculation parameters; if the length of the algorithm configuration parameter is less than the preset length, the input parameter also includes a redundant parameter, and the redundant parameter is used to fill the algorithm configuration parameter so that the length of the algorithm configuration parameter matches the preset length, so that the position and length of the calculation parameter in the input parameter received by each input branch are consistent. The problem of excessive resource consumption and insufficient flexibility of SPHINCS+ hardware implementation is solved, and efficient use of system resources is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0026] Figure 1 It is a structural schematic diagram of a first embodiment of a hash input circuit of the present invention;

[0027] Figure 2 It is a structural schematic diagram of a second embodiment of a hash input circuit of the present invention;

[0028] Figure 3 It is a flowchart diagram of an embodiment of a data input method based on a hash input circuit of the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] See also Figure 1 , Figure 1 It is a structural schematic diagram of a first embodiment of a hash input circuit of the present invention, which specifically comprises: a control unit 11 and a plurality of input branches 12 .

[0031] Among them, the control unit 11 is connected to the input branch 12, and is used to configure input parameters for each input branch 12, and the input parameters include an algorithm configuration parameter n and a calculation parameter m; if the length of the algorithm configuration parameter n is less than a preset length, the input parameter also includes a redundant parameter p, and the redundant parameter p is used to fill the algorithm configuration parameter n so that the length of the algorithm configuration parameter n matches the preset length, so that the position and length of the calculation parameter m in the input parameters received by each of the input branches 12 are consistent.

[0032] It should be noted that the hash input circuit of the present application is used to generate corresponding input data for the hash operation. First, the control unit 11 configures input parameters for the input branch 12, and then the input branch 12 processes the configuration parameters and outputs the input data corresponding to the hash operation.

[0033] The input data of the hash operation needs to include the algorithm configuration parameter n, which is used to ensure the security of the algorithm. Generally, the algorithm configuration parameter n is configured to be 256 / 192 / 128 bits. When n=256 bits, the algorithm security is the highest, and when n=128 bits, the algorithm security is the lowest. It can be seen that the number of bits of the algorithm configuration parameter n is uncertain. The input parameters of the input branch configuration need to be connected to the calculation parameter m after the algorithm configuration parameter n, which makes the calculation parameter m input to multiple input branches have different starting positions in the input parameters; and because the input parameters input to multiple input branches have the same length, the calculation parameter m input to multiple input branches also has different lengths in the input parameters. This will increase the resource overhead of the circuit.

[0034] Therefore, the present application provides a hash input circuit, which introduces a redundant parameter p, and uses the redundant parameter p to fill the algorithm configuration parameter n, so that the length of the algorithm configuration parameter n matches the preset length, so that the position and length of the calculation parameter m in the input parameter received by each input branch 12 are consistent. Since the maximum value of the algorithm configuration parameter n is 256 bits, the preset length is set to 256 bits. For example, when the algorithm configuration parameter n is 128 bits, a 128-bit redundant parameter p is filled after the algorithm configuration parameter n, so that the length of the algorithm configuration parameter n plus the length of the redundant parameter p is exactly 256 bits. For example, when the algorithm configuration parameter n is 192 bits, a 64-bit redundant parameter p is filled after the algorithm configuration parameter n, so that the length of the algorithm configuration parameter n plus the length of the redundant parameter p is exactly 256 bits. If the length of the algorithm configuration parameter n is equal to the preset length, that is, the length of the algorithm configuration parameter n is exactly 256 bits, the input parameter does not include a redundant parameter.

[0035] In this way, the length of the algorithm configuration parameter n can be matched with the preset length, so that the position and length of the calculation parameter p in the input parameters received by each input branch 12 are consistent.

[0036] Please combine Figure 2 , multiple input branches 12 are connected in series in sequence, the input branch 12 at the head end is connected to the control unit 11, and the control unit 11 controls the multiple input branches 12 to perform inter-group shifting to receive the input parameters from the control unit 11, and transmits the input parameters received for the first time to the input branch 12 at the end or the input branch 12 at the middle through the input branch 12 at the middle, so that each input branch 12 receives one input parameter. Figure 2 As shown, the input branch Array0 at the beginning is connected to the control unit 11. After Array0 receives the input parameter, it transmits the input parameter to the input branch Array3 at the end through the middle input branches Array1 and Array2. After Array0 receives the input parameter, it transmits the input parameter to the middle input branch Array2 through the middle input branch Array1. After Array0 receives the input parameter, it transmits the input parameter to the middle input branch Array1. Until finally Array0 receives the input parameter. In this process, Figure 2 Array Shift controls shown.

[0037] In one embodiment, the input parameter may be 1088 bits, and all the input parameters except the first 256 bits are calculation parameters.

[0038] Specifically, the input branch 12 includes: a plurality of shift registers connected in series in sequence. When receiving the input parameters, the control unit 11 controls the input branch 12 to shift and select redundant parameters in the input parameters, and stores the redundant parameters in the target shift register.

[0039] The number of shift registers in the input branch 12 is the greatest common factor of the length of the algorithm configuration parameter n. In one embodiment, the length of the algorithm configuration parameter n is 256 / 192 / 128 bits. The number of shift registers in each input branch 12 is 256 / 192 / 128, which is 64.

[0040] In one embodiment, when the algorithm configuration parameter n takes the minimum value of 128 bits, the redundant parameter p takes the maximum value of 128 bits, so the two bottom shift registers in the input branch 12 can be used as the target shift register. When the input parameter is stored in the shift register, the redundant parameter p is stored in the target shift register through shift control.

[0041] In one embodiment, after the input parameters are stored in the input branch 12, the control unit 11 controls the remaining shift registers in the input branch 12 except the target shift register to output the parameters stored in the remaining shift registers. Since the hash operation only requires the algorithm configuration parameter n and the calculation parameter m to participate, the hash input circuit needs to eliminate the redundant parameter p in the input parameter when outputting the input data corresponding to the hash operation. The control unit 11 outputs the algorithm configuration parameter n and the calculation parameter m stored in the shift register in the non-target shift register through the control of the Security Switch signal.

[0042] In one embodiment, the hash input circuit of the present application further includes a memory 13 and a data distribution branch 14. The data distribution branch 14 includes a plurality of data distributors, one input end of the data distributor is connected to the memory 13, another input end is connected to the control unit 11, and the output end is connected to the shift register in the input branch Array0. The memory 13 is used to store the load parameters and sequentially transmit the load parameters to the input branch 12 through the data distributor.

[0043] The hash input circuit of the present invention is used for the post-quantum cryptographic algorithm SPHINCS+. The circuit adopts the method of introducing redundant data and eliminating it by shifting, thereby solving the problem of excessive resource consumption and insufficient flexibility of SPHINCS+ hardware implementation, and realizing efficient utilization of system resources.

[0044] See also Figure 3 , Figure 3The present invention is a flow chart of an embodiment of a data input method based on a hash input circuit, wherein the hash input circuit includes the above Figure 1 and Figure 2 The hash input circuit and the data input method include:

[0045] Step S31: Determine whether the length of the algorithm configuration parameter is less than a preset length.

[0046] As mentioned above, the general configuration algorithm configuration parameter n is 256 / 192 / 128 bits. When n=256 bits, the algorithm security is the highest, and when n=128 bits, the algorithm security is the lowest. It can be seen that the number of bits of the algorithm configuration parameter n is uncertain, so it is necessary to determine whether the length of the algorithm configuration parameter n is less than the preset length, which is 256 bits.

[0047] Step S32: If the length of the algorithm configuration parameter is less than the preset length, the algorithm configuration parameter is padded with redundant parameters to make the length of the algorithm configuration parameter equal to the preset length.

[0048] For example, when the algorithm configuration parameter n is 128 bits, a 128-bit redundant parameter p is padded after the algorithm configuration parameter n, so that the length of the algorithm configuration parameter n plus the length of the redundant parameter p is exactly 256 bits. For example, when the algorithm configuration parameter n is 192 bits, a 64-bit redundant parameter p is padded after the algorithm configuration parameter n, so that the length of the algorithm configuration parameter n plus the length of the redundant parameter p is exactly 256 bits. If the length of the algorithm configuration parameter n is equal to the preset length, that is, the length of the algorithm configuration parameter n is exactly 256 bits, the input parameter does not include redundant parameters.

[0049] Step S33: Supplement the calculation parameters after the algorithm configuration parameters or after the redundant parameters to obtain input parameters, and transmit the input parameters to the input branch.

[0050] In one embodiment, the control unit controls multiple input branches to perform inter-group shifting to receive the input parameters from the control unit, and transmits the input parameters received for the first time to the input branch at the end or the input branch in the middle through the input branch in the middle, so that each of the input branches receives one input parameter.

[0051] In one embodiment, the control unit controls multiple shift registers in the input branch to shift and select redundant parameters in the input parameters, and stores the redundant parameters in a target shift register; controls the remaining shift registers in the input branch except the target shift register to output the parameters stored in the remaining shift registers to eliminate the redundant parameters.

[0052] The data input method of the present invention is used for the post-quantum cryptographic algorithm SPHINCS+. The circuit adopts the method of introducing redundant data and eliminating it by shifting, which solves the problem of excessive resource consumption and insufficient flexibility of SPHINCS+ hardware implementation, and realizes efficient utilization of system resources.

[0053] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A hash input circuit, characterized in that: include: A control unit and a plurality of input branches; The control unit is used to configure input parameters for each input branch, the input parameters including algorithm configuration parameters and calculation parameters; if the length of the algorithm configuration parameters is less than a preset length, the input parameters further include redundant parameters, the redundant parameters are used to fill the algorithm configuration parameters so that the length of the algorithm configuration parameters matches the preset length, so that the position and length of the calculation parameters in the input parameters received by each of the input branches are consistent; The multiple input branches are connected in series in sequence, and the input branch located at the head end is connected to the control unit. The control unit controls the multiple input branches to shift between groups to receive the input parameters from the control unit, and transmits the input parameters received for the first time to the input branch located at the end or the input branch located in the middle through the input branch located in the middle, so that each of the input branches receives one input parameter accordingly.

2. The hash input circuit according to claim 1, characterized in that: The input branch includes: a plurality of shift registers connected in series in sequence; The control unit controls the input branch to control a plurality of shift registers in the input branch to shift and select redundant parameters in the input parameters when receiving the input parameters, and stores the redundant parameters in a target shift register.

3. The hash input circuit according to claim 2, characterized in that: The control unit controls the remaining shift registers in the input branch except the target shift register to output the parameters stored in the remaining shift registers.

4. The hash input circuit according to claim 3, characterized in that: If the length of the algorithm configuration parameter is equal to the preset length, the input parameter does not include redundant parameters.

5. The hash input circuit according to claim 3, characterized in that: The number of shift registers in the input branch is the greatest common factor of the length of the algorithm configuration parameter.

6. The hash input circuit according to any one of claims 1 to 4, characterized in that: Also includes: Memory and data allocation branch The data distribution branch includes a plurality of data distributors, one input end of the data distributor is connected to the memory, another input end is connected to the control unit, and an output end of the data distributor is connected to the input branch; The memory is used to store loading parameters and transmit the loading parameters to the input branches in sequence.

7. A data input method based on a hash input circuit, characterized in that: The hash input circuit comprises the hash input circuit according to any one of claims 1 to 6 above, and the data input method comprises: Determine whether the length of the algorithm configuration parameter is less than the preset length; If the length of the algorithm configuration parameter is less than the preset length, padding the algorithm configuration parameter with redundant parameters so that the length of the algorithm configuration parameter is equal to the preset length; The calculation parameters are supplemented after the algorithm configuration parameters or after the redundant parameters to obtain input parameters, and the input parameters are transmitted to the input branch.

8. The data input method according to claim 7, characterized in that: Transmitting the input parameter to the input branch comprises: The control unit controls multiple input branches to perform inter-group shifting to receive the input parameters from the control unit, and transmits the input parameters received for the first time to the input branch at the end or the input branch in the middle through the input branch in the middle, so that each input branch receives one input parameter accordingly.

9. The data input method according to claim 8, characterized in that: Transmitting the input parameter to the input branch comprises: Controlling a plurality of shift registers in the input branch to shift and select redundant parameters in the input parameters, and storing the redundant parameters in a target shift register; The remaining shift registers except the target shift register in the input branch are controlled to output the parameters stored in the remaining shift registers.

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