Chip design method and chip for optimizing space utilization

Abstract

The present invention relates to the field of chip optimization technology, and in particular to a method for optimizing space utilization chip design and a chip thereof. The method comprises the following steps: performing local optimal analysis on chip historical component data to obtain local optimal component data; performing random gradient analysis on register transfer level data under the condition that timing constraints are satisfied to obtain optimized circuit parameter mapping data; performing local optimal matching of indicators on local optimal component data and chip design indicator data to obtain optimal indicator component data; performing micro-architecture construction on chip component data and optimized circuit parameter mapping data according to the optimal indicator component data to obtain a spatial hierarchy optimization model; performing embedded spatial balance analysis based on the spatial hierarchy optimization model to obtain embedded balance analysis data; performing embedded learning migration on the spatial hierarchy optimization model to obtain a spatial utilization optimization model. The present invention can efficiently optimize the spatial utilization of chip design.

Description

Technical Field

[0001] The present invention relates to the technical field of chip optimization, and in particular to a chip design method for optimizing space utilization and a chip thereof. Background Art

[0002] The chip design method for optimizing space utilization is one of the important technologies in the field of integrated circuit design and is widely used in various electronic devices and systems, such as mobile communications, the Internet of Things, artificial intelligence, and embedded systems. However, in the existing chip design methods for optimizing space utilization, the integration of a large number of functional modules of the chip often lacks an efficient layout algorithm, resulting in large intervals and redundant space between modules. For example, in embedded chip scenarios where there is a greater demand for space utilization optimization, it is difficult to make an effective balance between the power consumption, performance, and layout footprint (PPA) of the chip design, resulting in difficulty in optimizing space utilization in the process of balancing PPA. Summary of the invention

[0003] Based on this, it is necessary for the present invention to provide a chip design method and a chip for optimizing space utilization to solve at least one of the above technical problems.

[0004] To achieve the above object, the present invention provides a chip design method for optimizing space utilization, comprising the following steps:

[0005] Step S1: Obtain chip historical component data and register transfer level data; perform local optimal analysis on the chip historical component data to obtain local optimal component data; perform stochastic gradient analysis on the register transfer level data under the condition that timing constraints are satisfied to obtain optimized circuit parameter mapping data;

[0006] Step S2: Obtain chip design index data and chip component data; perform local optimal matching of the local optimal component data and the chip design index data, thereby obtaining the optimal index component data; perform micro-architecture construction on the chip component data and the optimized circuit parameter mapping data according to the optimal index component data, thereby obtaining a spatial hierarchical structure optimization model;

[0007] Step S3: performing embedded spatial balance analysis based on the spatial hierarchy optimization model, thereby obtaining embedded balance analysis data;

[0008] Step S4: Perform embedded learning migration on the spatial hierarchy optimization model according to the embedded balance analysis data, so as to obtain a spatial utilization optimization model.

[0009] The present invention firstly uses the chip historical component data to perform local optimal analysis, and can identify the component configuration with the best performance in a specific functional area. The advantage of doing so is that the performance of the local area of ​​the chip can be maximized, thereby improving the performance and efficiency of the overall chip. By performing random gradient analysis on the register transfer level data under the condition of satisfying the timing constraint, optimized circuit parameter mapping data can be obtained. This helps to improve the timing performance of the chip to meet the timing constraint requirements in the design. Performing local optimal matching of indicators can match the design indicators of the chip with the local optimal component data, thereby achieving the best match of performance and function within the entire chip range. This helps to improve the overall performance and function of the chip and meet the design requirements. Using the optimal indicator component data to construct the micro-architecture can optimize the architecture and layout of the chip according to the performance requirements and the characteristics of the local optimal components. The advantage of doing so is that the space utilization of the chip can be improved, the area waste can be reduced, and a compact and efficient chip design can be achieved. Performing embedded space balance analysis can consider the space utilization balance between different functional modules in the chip. This helps to optimize the overall spatial layout of the chip, improve the space utilization, and ensure the reasonable arrangement and connection between the functional modules, thereby improving the performance and efficiency of the chip. By using embedded balance analysis data to perform embedded learning migration on the spatial hierarchy optimization model, the model can be adjusted and optimized according to the actual space utilization. The advantage of doing so is that it can further improve the space utilization of the chip and adapt to different design requirements and constraints. In general design, performance is prioritized while reducing area and power consumption as much as possible. Area and power consumption depend on the application scenario, and area is considered last. In scenarios such as embedded systems that rely more on space utilization optimization, the optimal choice of space utilization for data paths and layout is considered at an early stage, which is more in line with the chip design optimization of the scenario. Of course, consideration and balance of performance and power consumption are also essential, and the weight of chip performance is still higher.

[0010] Preferably, the present invention also provides a chip designed and manufactured by the chip design method for optimizing space utilization as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments thereof made with reference to the following drawings:

[0012] Figure 1 A schematic diagram of the steps of the method for designing a chip with optimized space utilization according to the present invention;

[0013] Figure 2 for Figure 1 Detailed step flow diagram of step S1;

[0014] Figure 3 for Figure 2 Detailed step flow chart of step S15 in FIG. DETAILED DESCRIPTION

[0015] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0016] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0017] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0018] To achieve this, please refer to Figures 1 to 3 The present invention provides a chip design method for optimizing space utilization, comprising the following steps:

[0019] Step S1: Obtain chip historical component data and register transfer level data; perform local optimal analysis on the chip historical component data to obtain local optimal component data; perform stochastic gradient analysis on the register transfer level data under the condition that timing constraints are satisfied to obtain optimized circuit parameter mapping data;

[0020] Step S2: Obtain chip design index data and chip component data; perform local optimal matching of the local optimal component data and the chip design index data, thereby obtaining the optimal index component data; perform micro-architecture construction on the chip component data and the optimized circuit parameter mapping data according to the optimal index component data, thereby obtaining a spatial hierarchical structure optimization model;

[0021] Step S3: performing embedded spatial balance analysis based on the spatial hierarchy optimization model, thereby obtaining embedded balance analysis data;

[0022] Step S4: Perform embedded learning migration on the spatial hierarchy optimization model according to the embedded balance analysis data, so as to obtain a spatial utilization optimization model.

[0023] In the embodiment of the present invention, please refer to Figure 1 FIG. 1 is a schematic diagram of the steps of the method for designing a chip for optimizing space utilization according to the present invention. In this example, the method for designing a chip for optimizing space utilization includes the following steps:

[0024] Step S1: Obtain chip historical component data and register transfer level data; perform local optimal analysis on the chip historical component data to obtain local optimal component data; perform stochastic gradient analysis on the register transfer level data under the condition that timing constraints are satisfied to obtain optimized circuit parameter mapping data;

[0025] The embodiment of the present invention collects historical component data and register transfer level data of the chip. The historical component data of the chip includes relevant information of the components used in previous designs, such as performance indicators, power consumption, etc. The register transfer level data contains information on the register transfer level in the chip design, which is used to analyze timing constraints and perform local optimal analysis on the historical component data of the chip. By evaluating indicators such as performance and power consumption of different components under specific conditions, the component that performs best in the local scenario is selected as the local optimal component data, and a random gradient analysis is performed on the register transfer level data under the condition that the timing constraints are met. Under the premise of considering the timing constraints, the stochastic gradient analysis method is used to optimize different circuit parameters to obtain the optimal circuit parameter mapping data that meets the constraints.

[0026] Step S2: Obtain chip design index data and chip component data; perform local optimal matching of the local optimal component data and the chip design index data, thereby obtaining the optimal index component data; perform micro-architecture construction on the chip component data and the optimized circuit parameter mapping data according to the optimal index component data, thereby obtaining a spatial hierarchical structure optimization model;

[0027] The embodiment of the present invention obtains chip design index data and chip component data. The chip design index data includes requirements and goals for chip performance, power consumption, area, etc. The chip component data includes a selectable component library and its related performance parameters. The local optimal component data is matched with the chip design index data for local optimal index matching. By comparing the degree of adaptation of the local optimal component data with the design index, the component that best suits the design index is selected as the optimal index component data. Based on the optimal index component data, the chip component data and the optimized circuit parameter mapping data are micro-architected. According to the characteristics and performance of the optimal index component data, suitable chip components and their parameters are selected and configured, and at the same time, the circuit parameters are mapped and configured according to the optimized circuit parameter mapping data to construct a micro-architecture that adapts to the design requirements.

[0028] Step S3: performing embedded spatial balance analysis based on the spatial hierarchy optimization model, thereby obtaining embedded balance analysis data;

[0029] The embodiment of the present invention performs embedded spatial balance analysis based on a spatial hierarchy optimization model. The constructed spatial hierarchy optimization model is used to analyze and evaluate the spatial resources of the chip. The model can consider the resource allocation and utilization between different levels and regions, as well as the impact of optimized circuit parameter mapping data. An embedded spatial balance analysis is performed, including evaluation and analysis of the rationality of resource allocation, resource utilization, and performance. Through this analysis, embedded balance analysis data is obtained, which describes the spatial resource utilization of different regions and levels in the chip.

[0030] Step S4: Perform embedded learning migration on the spatial hierarchy optimization model according to the embedded balance analysis data, so as to obtain a spatial utilization optimization model.

[0031] The embodiment of the present invention performs embedded learning transfer on the spatial hierarchy optimization model by utilizing embedded balance analysis data. Embedded learning transfer refers to applying the knowledge and experience that has been learned to new tasks or models. Here, the information in the embedded balance analysis data is used to optimize and improve the spatial hierarchy optimization model. The embedded balance analysis data is used as training data and trained and optimized with the original spatial hierarchy optimization model. Through the method of transfer learning, the parameters of the existing model are fine-tuned and optimized to adapt to the features and patterns in the embedded balance analysis data. After embedded learning transfer, a spatial utilization optimization model is obtained. This model can better utilize the information in the embedded balance analysis data and provide more accurate spatial resource utilization prediction and optimization guidance.

[0032] The present invention firstly uses the chip historical component data to perform local optimal analysis, and can identify the component configuration with the best performance in a specific functional area. The advantage of doing so is that the performance of the local area of ​​the chip can be maximized, thereby improving the performance and efficiency of the overall chip. By performing random gradient analysis on the register transfer level data under the condition of satisfying the timing constraint, optimized circuit parameter mapping data can be obtained. This helps to improve the timing performance of the chip to meet the timing constraint requirements in the design. Performing local optimal matching of indicators can match the design indicators of the chip with the local optimal component data, thereby achieving the best match of performance and function within the entire chip range. This helps to improve the overall performance and function of the chip and meet the design requirements. Using the optimal indicator component data to construct the micro-architecture can optimize the architecture and layout of the chip according to the performance requirements and the characteristics of the local optimal components. The advantage of doing so is that the space utilization of the chip can be improved, the area waste can be reduced, and a compact and efficient chip design can be achieved. Performing embedded space balance analysis can consider the space utilization balance between different functional modules in the chip. This helps to optimize the overall spatial layout of the chip, improve the space utilization, and ensure the reasonable arrangement and connection between the functional modules, thereby improving the performance and efficiency of the chip. By using embedded balance analysis data to perform embedded learning migration on the spatial hierarchy optimization model, the model can be adjusted and optimized according to the actual space utilization. The advantage of doing so is that it can further improve the space utilization of the chip and adapt to different design requirements and constraints. In general design, performance is prioritized while reducing area and power consumption as much as possible. Area and power consumption depend on the application scenario, and area is considered last. In scenarios such as embedded systems that rely more on space utilization optimization, the optimal choice of space utilization for data paths and layout is considered at an early stage, which is more in line with the chip design optimization of the scenario. Of course, consideration and balance of performance and power consumption are also essential, and the weight of chip performance is still higher.

[0033] As an embodiment of the present invention, refer to Figure 2 As shown, Figure 1 Detailed step flow diagram of step S1 in FIG. 1 , in this embodiment, step S1 includes the following steps:

[0034] Step S11: Acquire chip historical component data, wherein the chip historical component data includes component performance historical data, electrical parameter historical data, and process characteristic historical data;

[0035] Step S12: clustering the component performance history data and the electrical parameter history data according to the process characteristic history data, thereby obtaining chip component clustering data, wherein the data clustering includes component material characteristic clustering and component connection timing characteristic clustering;

[0036] Step S13: performing local optimal analysis of different components on the chip component clustering data, thereby obtaining local optimal component data, wherein the local optimal analysis of different components includes local optimal analysis of performance, local optimal analysis of power consumption, and local optimal analysis of area utilization, wherein the local optimal analysis of power consumption includes power consumption analysis at different temperatures and power consumption analysis at different workloads;

[0037] Step S14: acquiring register transfer level data, wherein the register transfer level data includes circuit logic history data, circuit structure history data and time constraint history data;

[0038] Step S15: performing random gradient analysis on the register transfer level data under the condition that the timing constraints are satisfied, thereby obtaining optimized circuit parameter mapping data.

[0039] The embodiment of the present invention collects historical component data of the chip, including component performance history data, electrical parameter history data and process characteristic history data. These data can come from chip examples designed in the past or related chip databases; component performance history data includes performance indicators of the component, such as speed, power consumption, area, etc. Electrical parameter history data includes electrical characteristic parameters of the component, such as voltage, current, delay, etc. Process characteristic history data includes process parameters in the manufacturing process of the component, such as process nodes, materials, etc. Using process characteristic history data, cluster analysis is performed on component performance history data and electrical parameter history data. Clustering algorithms, such as K-means clustering or hierarchical clustering, can be used to divide component data into different categories or clusters. Component material characteristic clustering is based on the similarity of component materials. For example, components are grouped according to characteristics such as material type and crystal structure. Component connection timing characteristic clustering is based on the connection timing characteristics of components. For example, components are grouped according to characteristics such as signal delay and clock frequency. The chip component clustering data is subjected to local optimal performance analysis. Perform performance evaluation on each component category, consider the speed, power consumption, area and other indicators of the components, and select the components with the best performance under specific conditions as the local optimal component data, and perform local optimal analysis on power consumption of chip component cluster data. Under different temperature conditions, evaluate the power consumption characteristics of each component category, and select the components with the best power consumption within a specific temperature range as the local optimal component data. In addition, power consumption analysis under different workload conditions can be performed to obtain a more comprehensive power consumption optimization solution. Perform local optimal analysis on area utilization of chip component cluster data. Consider the area utilization of each component category, and select the components with the best area utilization as the local optimal component data. Collect register transfer level data, including circuit logic history data, circuit structure history data and time constraint history data. These data can be used to design register transfer level circuits or related circuit design databases. Circuit logic history data includes the logical functions and operations of register transfer level circuits. Circuit structure history data includes information such as the structure, layout and connection method of register transfer level circuits. Time constraint history data includes timing constraints in register transfer level circuits, such as clock frequency, data delay, etc. According to the time constraint information in the register transfer level data, the timing constraints are defined, and random gradient analysis is performed to optimize the circuit parameters so that the circuit meets the timing constraints. Optimization algorithms such as gradient descent and genetic algorithms can be used to search for the optimal circuit parameter settings. During the optimization process, the circuit parameters are adjusted according to the timing constraints, and the performance indicators of the circuit, such as clock frequency, data delay, etc., are evaluated. Based on the evaluation results, the optimized circuit parameter mapping data is determined to meet the timing constraints.

[0040] The present invention firstly obtains component performance history data to analyze and compare the performance of various components in the chip under different conditions. This helps to understand the characteristics and performance range of the components, and provides a basis for subsequent local optimal analysis and optimization. Obtaining electrical parameter history data can understand the behavior and response of chip components under different electrical conditions. This is crucial for optimizing circuit parameters and meeting design requirements. Obtaining process characteristic history data can understand process changes and characteristic evolution in the chip manufacturing process. This helps to consider process factors in the design process and provides a reference for the selection and optimization of chip components. By clustering component performance history data and electrical parameter history data, similar components can be classified into the same category. This helps to simplify data analysis and processing, and provides an overall understanding of chip component characteristics. Component material characteristic clustering can group components with similar material characteristics to better select and match the application of components in design. Component connection timing characteristic clustering can group components with similar connection timing characteristics to better consider and meet the timing constraint requirements in chip design. Performing local optimal analysis of performance can identify the component configuration with the best performance in a specific functional area to maximize the performance of the local area of ​​the chip. Performing local optimal analysis of power consumption can optimize the power consumption characteristics of the chip. By considering the power consumption analysis under different temperature and workload conditions, energy saving and optimization of the power consumption performance of the chip can be achieved. Performance, thereby improving the performance and efficiency of the overall chip. Performing local optimal analysis of area utilization can optimize the layout and area utilization of the chip, ensuring that the area resources of the chip are fully utilized, thereby achieving compact and efficient chip design. Obtaining circuit logic history data can understand the logical function and behavior of the chip circuit. This is very important for optimizing the function and performance of the circuit. Obtaining circuit structure history data can understand the structure and topology characteristics of the chip circuit. This helps to optimize the layout and connection method of the circuit, improve the performance and reliability of the circuit, and obtain time constraint history data to understand the timing requirements and restrictions in chip design. Performing random gradient analysis under the condition of satisfying timing constraints can optimize circuit parameter mapping, ensure that the circuit meets timing requirements and obtains better performance. Through random gradient analysis, circuit parameters can be adjusted and optimized under the premise of meeting timing constraints to improve circuit performance, power consumption and area efficiency. Optimizing circuit parameter mapping data can improve circuit reliability, stability and power consumption efficiency while meeting design requirements and constraints.

[0041] As an embodiment of the present invention, refer to Figure 3 As shown, Figure 2 Detailed step flow diagram of step S15 in FIG. 1 , in this embodiment, step S15 includes the following steps:

[0042] Step S151: performing logic module identification on the circuit logic history data, thereby obtaining logic module data;

[0043] Step S152: constructing component connection relationships for circuit logic history data according to logic module data, thereby obtaining a component connection relationship network model;

[0044] Step S153: performing a signal transmission path relationship analysis between logic modules on the component connection relationship network model, thereby obtaining signal transmission path relationship data, wherein the signal transmission path relationship analysis between logic modules includes a signal input relationship analysis, an output relationship analysis, and a timing relationship analysis;

[0045] Step S154: constructing a component logic diagram for the signal transmission path relationship data, thereby obtaining a component logic network model;

[0046] Step S155: performing key component layout analysis on the circuit structure history data to obtain key component layout data, wherein the key component layout analysis includes logic module layout analysis, register layout analysis, and memory layout analysis;

[0047] Step S156: constructing a component space model for the circuit structure history data according to the key component layout data, thereby obtaining a component space model, wherein the component space model construction includes relative position vector layout and wiring rule vector layout;

[0048] Step S157: performing layout space constraint analysis between components on the component space model, thereby obtaining component layout constraint analysis data, wherein the layout space constraint analysis between components includes physical constraint analysis and signal transmission path length constraint analysis;

[0049] Step S158: performing two-dimensional plane abstract mapping on the component space model according to the component layout constraint analysis data, thereby obtaining a layout space model;

[0050] Step S159: performing stochastic gradient analysis on the component logic network model and the layout space model under the condition that the timing constraints are satisfied, so as to obtain optimized circuit parameter mapping data.

[0051] The embodiment of the present invention identifies the logic modules therein by analyzing the circuit logic history data. The logic module can be a functionally independent and reusable circuit unit, such as an adder, a multiplier, a register, etc., and uses a logic analysis tool or a custom algorithm to organize the components in the circuit logic history data into logic modules by detecting the functional mode, signal flow, and logic relationship in the circuit. The identified logic modules are named and classified to generate logic module data, including module name, input / output interface, function description, etc. The logic module data is used to analyze the connection relationship of the components in the circuit logic history data. According to the input / output interface information of the logic module, the connection relationship between the components is determined, and according to the connection information in the logic module data, a component connection relationship network model is constructed. The connection relationship between the components can be represented by a graph theory method, where the components are nodes in the graph and the connection relationship is an edge. The signal transmission path relationship between the logic modules in the component connection relationship network model is analyzed. Determine the transmission path of signals between different logic modules, perform input relationship analysis of signals, determine the input signal source and input relationship of each logic module, perform output relationship analysis of signals, determine the output signal destination and output relationship of each logic module, perform timing relationship analysis, analyze the timing characteristics such as signal transmission delay and clock edge between logic modules to determine the timing constraint relationship. Construct component logic diagram based on signal transmission path relationship data. The logic diagram represents the logical relationship and signal transmission path between components. The logic module is used as a node and the signal transmission path as an edge to construct a logic network model. Analyze the historical data of circuit structure and identify the key components therein. Key components can be components that have a greater impact on circuit performance, power consumption or area, such as high-speed logic modules, key registers or memories. Use layout analysis tools or custom algorithms to perform layout analysis on key components in the historical data of circuit structure. Consider the physical constraints between key components, signal transmission path length constraints and other design rules, determine their layout positions in the circuit, perform logic module layout analysis, determine the relative position relationship between logic modules to optimize signal transmission and wiring length, perform register layout analysis, determine the position of registers in the circuit to meet timing requirements and data path design, perform memory layout analysis, determine the location and arrangement of memory to improve access efficiency and save area. Use key component layout data to build a component space model. The component space model describes the relative position and wiring rules of components in the circuit, performs relative position vector layout, and determines the relative position relationship between components. The layout position of components can be represented by a coordinate system or a relative position vector, and a wiring rule vector layout is performed to determine the wiring rules between components. The wiring rules include constraints such as the length, direction, and routing hierarchy of the signal transmission path. Analyze the layout space constraints between components in the component space model.Considering physical constraints such as component size, spacing, position relationship, and length constraints of signal transmission paths, physical constraint analysis is performed to determine physical constraints between components, such as avoiding overlap and maintaining minimum spacing, and signal transmission path length constraint analysis is performed to limit the length of the signal transmission path to reduce delay and power consumption. Using component layout constraint analysis data, the component space model is abstractly mapped to a two-dimensional plane. The component positions and wiring rules in the component space model are mapped to a two-dimensional plane, and the layout algorithm or optimization method is used to determine the layout position of the component on the plane to meet the component layout constraints and signal transmission path length constraints. Combined with the component logic network model and the layout space model, random gradient analysis is performed under the condition that timing constraints are met. Considering factors such as timing requirements, signal transmission delay, and layout constraints, the random gradient analysis method is used to optimize the circuit parameter mapping, such as wiring length, signal transmission delay, power consumption, etc., to meet timing constraints and improve circuit performance.

[0052] The present invention firstly separates and identifies different logic function modules in the circuit logic history data through logic module identification. This helps to understand and analyze the structure and function of the circuit, provides basic data for subsequent steps, and accurately describes and represents the logical connection relationship between components in the circuit by constructing a component connection relationship network model. This helps to understand the structure and behavior of the circuit, and the signal transmission path relationship analysis can understand the signal transmission mode and relationship between different logic modules. This helps to understand the data flow and signal transmission of the circuit. Through the construction of the component logic diagram, the logical relationship and interaction between different components in the circuit can be more clearly represented. This helps to analyze and optimize the function and behavior of the circuit, and the key component layout analysis can identify the key components that have an important impact on the overall circuit performance and layout. This helps to optimize the layout and wiring of the circuit and improve the performance and reliability of the circuit. Constructing a component space model can represent the relative position relationship between different components in the circuit in physical space. This helps to optimize the circuit layout and improve the wiring and connection effect of the circuit. The layout space constraint analysis can consider the layout constraints between different components, such as physical space limitations, signal transmission path length, etc. This helps to optimize the layout of the circuit and ensure that the layout meets physical and timing requirements. Through two-dimensional plane abstract mapping, the component space model can be mapped onto the two-dimensional plane, which can more intuitively display the layout and connection relationship of the circuit. This helps designers to conduct further layout analysis and optimization. Stochastic gradient analysis under the condition of timing constraint satisfaction can optimize the mapping of circuit parameters to meet timing requirements and improve circuit performance. This helps to optimize and adjust parameters in the design stage so that the circuit meets the expected functional and performance requirements.

[0053] Preferably, step S159 includes the following steps:

[0054] According to the key component layout data, feature matching is performed on the component logic network model and the layout space model to obtain a circuit logic distribution model;

[0055] Performing timing relationship constraint analysis on the time constraint history data based on the circuit logic distribution model, thereby obtaining timing relationship data, wherein the timing relationship data includes signal transmission delay relationship data, clock frequency relationship data and data path relationship data;

[0056] Performing full convolution mapping of parameters on the circuit logic distribution model according to the signal transmission delay relationship data, the clock frequency relationship data, and the data path relationship data, thereby obtaining mapping parameter data;

[0057] The mapping parameter data is subjected to random gradient analysis under the condition that the timing constraints are satisfied, thereby obtaining the optimized circuit parameter mapping data.

[0058] The embodiment of the present invention uses key component layout data to perform feature matching between the component logic network model and the layout space model. The layout position and wiring rules of the logic module are compared, and the logic module is mapped to the corresponding position in the layout space model. According to the matching result, the circuit logic distribution model is generated. In the logic distribution model, the relative position and wiring rules of the logic module are consistent with the actual layout space model. According to the circuit logic distribution model, the timing relationship in the time constraint history data is analyzed. Considering the correlation of signal transmission delay, clock frequency and data path, the signal transmission delay relationship analysis is performed to determine the transmission delay of the signal between the logic modules, the clock frequency relationship analysis is performed to determine the frequency and clock domain division of the clock signal, and the data path relationship analysis is performed to determine the transmission path and correlation of the data between the logic modules. The circuit logic distribution model is parameter fully convolutionally mapped using the signal transmission delay relationship data, the clock frequency relationship data and the data path relationship data. The timing relationship data is mapped to each logic module and signal path of the logic distribution model, and the layout position of the logic module, the length of the signal transmission path and the clock frequency and other parameters are adjusted based on the mapping parameter data to meet the timing constraints and performance requirements. Based on the mapping parameter data, stochastic gradient analysis is performed under the condition that the timing constraints are met. Considering factors such as timing relationships, layout constraints, and performance indicators, the stochastic gradient analysis method is used to optimize the circuit parameter mapping, such as layout position, signal transmission path length, clock frequency, etc., to meet timing constraints and improve circuit performance.

[0059] The present invention first matches key component layout data with component logic network model and layout space model through feature matching, thereby establishing a logic distribution model of the circuit. This helps to better understand the logic structure and layout characteristics of the circuit, and provides a more accurate data basis for subsequent steps. Performing timing relationship constraint analysis can study the transmission delay, clock frequency and data path relationship between different signals in the circuit. This helps to accurately evaluate the timing performance and clock frequency requirements of the circuit, and provides important timing relationship data for subsequent steps. Through parameter full convolution mapping, the logic distribution model of the circuit can be parameter mapped according to the signal transmission delay, clock frequency and data path relationship data. This helps to optimize the layout and parameter settings of the circuit to meet the timing and performance requirements. Performing random gradient analysis under the condition of timing constraint satisfaction can optimize the mapping parameters to meet the timing requirements of the circuit and improve the performance of the circuit. This helps to adjust and optimize the parameters in the design stage so that the circuit can achieve better timing performance and functional requirements.

[0060] Preferably, step S2 comprises the following steps:

[0061] Step S21: Acquire chip design index data and chip component data;

[0062] Step S22: constructing a thermal environment regression neural network for the local optimal component data and the chip design index data, thereby obtaining a thermal environment regression model;

[0063] Step S23: performing dynamic power consumption prediction based on the thermal environment regression model, thereby obtaining dynamic power consumption prediction data;

[0064] Step S24: performing local optimal matching of the dynamic power consumption prediction data and the chip design index data, thereby obtaining optimal index component data;

[0065] Step S25: dividing the chip component data into logical modules according to the optimal index component data, thereby obtaining a logical module division data set;

[0066] Step S26: performing optimal data path parameter analysis on the optimized circuit parameter mapping data and the logic module partition data set, thereby obtaining optimal data path data;

[0067] Step S27: classifying the flow modes between adjacent logic modules for the optimal data path data, thereby obtaining the connection flow module path data;

[0068] Step S28: integrating the connection flow module path data with minimum occupied area and constructing a micro-architecture with minimum wiring length, thereby obtaining a spatial hierarchical structure optimization model.

[0069] The embodiment of the present invention collects chip design index data, including performance requirements, power consumption requirements, area requirements, etc. These index data describe the design goals and constraints, and obtain chip component data, including various available components, devices, IP cores, etc. These data describe the available building blocks and resources. The functional requirements and performance goals of the chip are clarified, which can be obtained through discussions with system architects, product managers and other relevant stakeholders, and the functions, performance indicators, storage requirements, interface requirements, etc. that the chip needs to achieve are determined. These requirements will provide basic guidance and constraints for the design of the microarchitecture. For example, when designing a graphics processor (GPU), it is necessary to clarify the graphics algorithms and features that it needs to support, such as image rendering, lighting effects, texture mapping, etc. It is also necessary to determine the required processing power, memory bandwidth, and power consumption limit and other performance indicators. The local optimal component data and chip design index data are used as input data to construct a thermal environment regression neural network model. Deep learning methods such as multi-layer perceptron (MLP) or convolutional neural network (CNN) can be used to train the neural network model using a training data set so that it can predict chip performance under different thermal environment conditions. Using the constructed thermal environment regression model, input the design index data and thermal environment parameters (such as temperature, power supply voltage, etc.). Use the thermal environment regression model to predict dynamic power consumption and obtain the chip power consumption prediction data under a given thermal environment. Perform the local optimal matching analysis of the dynamic power consumption prediction data and the chip design index data. According to the chip design index requirements, select the component data that best matches the target index as the optimal index component data. Based on the optimal index component data, divide the chip component data into logical modules. Considering the interconnection relationship and functional division between components, generate a logical module division data set, where each logical module contains a group of components with specific functions and connection relationships. Combined with the optimized circuit parameter mapping data and the logical module division data set, perform the optimal data path parameter analysis, consider the data transmission path, clock domain division, data path length and delay, optimize the data path parameters, and obtain the optimal data path data, including the optimized transmission path, clock frequency and path delay information. According to the optimal data path data, the data flow mode between adjacent logic modules is analyzed and classified, such as direct connection, buffer / repetition, multi-level buffer, clock network, etc., to generate connection flow module path data to describe the data flow mode and related connection information between logic modules. Using the connection flow module path data, a micro-architecture with minimum occupied area integration and minimum wiring length is constructed. Factors such as layout constraints, signal path length, and power consumption distribution are considered in the micro-architecture to optimize the design to meet area and performance requirements, and a spatial hierarchy optimization model is generated to describe the layout and wiring information of the optimal micro-architecture.

[0070] The present invention first obtains chip design index data and chip component data as the basis for subsequent steps. These data provide information about the design requirements, performance indicators and component properties of the chip, and provide an accurate data basis for the analysis and optimization of the subsequent steps. By constructing a thermal environment regression model, the local optimal component data and chip design index data can be modeled and analyzed with the characteristics related to the thermal environment. This helps to predict the performance and power consumption characteristics of the chip under different thermal environments. Dynamic power consumption prediction can predict the power consumption of the chip during operation according to the thermal environment regression model and other related factors. This helps to evaluate the power consumption performance of the chip under actual use. Through the local optimal matching of indicators, the dynamic power consumption prediction data and the chip design index data can be matched and optimized with the component parameters. This helps to find the best component combination to meet the design requirements and optimize the performance and power consumption of the chip. Logical module division is to divide the chip component data into different logical modules for subsequent optimization and layout. Logical module division through optimal indicator component data can improve the effect of modular design, making the subsequent steps more efficient and accurate. Through optimal data path parameter analysis, the optimized circuit parameter mapping data and the logical module division data set can be analyzed and optimized to obtain the best data path design. This helps improve the performance and timing requirements of the circuit and optimize the transmission and processing efficiency of data. By classifying the flow of data in the optimal data path, the data flow between adjacent logic modules can be identified and determined. This helps optimize the layout and connection of the data path and improve the performance and data transmission efficiency of the chip. The construction of a microarchitecture with minimum footprint integration and minimum wiring length can optimize the spatial layout and wiring of the chip. By optimizing the layout and wiring, the chip's footprint can be reduced, the integration can be increased, and the path and length of signal transmission can be optimized, thereby improving the performance and efficiency of the chip. This helps to achieve the optimal design of the spatial hierarchy and improve the overall performance and functionality of the chip.

[0071] Preferably, step S28 comprises the following steps:

[0072] Step S281: constructing a data path graph with optimal performance for connecting flow module path data, thereby obtaining an optimal performance data path model, wherein the data path graph with optimal performance includes flow path construction, data width weighting, and key component distribution construction;

[0073] Step S282: performing control relationship analysis between chip functional modules based on the optimal performance data path model, thereby obtaining control relationship analysis data;

[0074] Step S283: performing timing constraint analysis on chip component data based on the optimal performance data path model and the control relationship analysis data, thereby obtaining a data path control logic model, wherein the timing constraint analysis includes clock control analysis, state machine analysis, and control signal analysis of each module;

[0075] Step S284: performing simulated high-level synthesis processing on the optimized circuit parameter mapping data based on the data path control logic model, thereby obtaining register transfer level performance data;

[0076] Step S285: performing a synthesized gate-level netlist power consumption prediction on the register transfer level performance data, thereby obtaining synthesized power consumption prediction data;

[0077] Step S286: constructing a key component hierarchy for the optimized circuit parameter mapping data based on the data path control logic model and according to the synthetic power consumption prediction data, thereby obtaining a hierarchical structure distribution model;

[0078] Step S287: Perform minimum occupied area integration and minimum wiring length micro-architecture construction on the hierarchical structure distribution model, thereby obtaining a spatial hierarchical structure optimization model.

[0079] The embodiment of the present invention constructs a data path diagram with optimal performance according to the data of the connection flow module path, constructs the flow path, determines the transmission path of the signal in the chip, considers factors such as the shortest path and the minimum delay, performs data width weighting, and allocates appropriate data width to each signal according to the importance and transmission requirements of the signal to balance performance and resource consumption, and constructs the distribution of key components, placing key components in appropriate positions to minimize signal transmission paths and delays. Based on the optimal performance data path model, the control relationship between the chip functional modules is analyzed, the data dependency relationship and timing requirements between the modules are considered, the transmission and interaction mode of the control signal is determined, and the control relationship analysis data is generated to describe the control relationship between each functional module and the corresponding signal transmission rules. Analyze data using the optimal performance data path model and control relationship, perform timing constraint analysis, perform clock control analysis, determine clock domain division and clock control strategy, ensure data is transmitted on the correct clock edge, perform state machine analysis, analyze and design modules that require state transitions, ensure correct control signal generation and transmission, perform control signal analysis for each module, determine the input and output control signals for each module to meet timing requirements and functional requirements, generate a data path control logic model, and describe the control logic and timing constraint rules of the data path. Use the data path control logic model to simulate advanced synthesis processing on the optimized circuit parameter mapping data, convert the circuit parameter mapping data into a register transfer level representation, including register transfer level data paths and control logic, perform simulated advanced synthesis processing, including timing optimization, resource mapping, logic optimization, etc., to obtain register transfer level performance data, including clock frequency, delay, power consumption and other indicators, for evaluation and optimization of chip design.

[0080] The present invention first constructs a data path diagram with optimal performance, and can design a data path model that meets the optimal performance requirements according to the connection flow module path data. Flow path construction, data width weighting and key component distribution construction help optimize the delay, bandwidth and key component position of the data path, thereby improving the performance and data transmission efficiency of the chip. Control relationship analysis can determine the control relationship and communication mode between the chip function modules. By performing control relationship analysis based on the optimal performance data path model, the control association between the modules can be established, and the transmission mode of the control signal can be determined, which is helpful for the optimization and adjustment of the system-level design. Timing constraint analysis can determine the timing relationship and clock control mode between different modules in the chip. By performing timing constraint analysis based on the optimal performance data path model and control relationship analysis data, the clock control, state machine and control signal of each module can be analyzed and optimized to ensure the correct operation of the data path and the satisfaction of the timing requirements. Simulation of advanced comprehensive processing can combine the data path control logic model with the optimized circuit parameter mapping data, perform advanced comprehensive processing, and generate performance data at the register transfer level. This helps to evaluate the performance and function of the chip at the register transfer level, and provides key data and analysis basis for subsequent steps. The power consumption prediction of the synthesized gate-level netlist can be used to estimate the power consumption based on the register transfer level performance data. By performing the power consumption prediction of the synthesized gate-level netlist based on the register transfer level performance data, the power consumption of the chip at the gate-level netlist level can be evaluated, providing a basis for power optimization in the subsequent steps. By constructing the key component hierarchy based on the data path control logic model and the synthesized power consumption prediction data, the key component layout of the circuit parameter mapping data can be optimized to ensure the reasonable distribution and layout of the key components in the chip. This helps to improve the overall performance and power efficiency of the circuit. By constructing the micro-architecture with minimum occupied area integration and minimum wiring length for the hierarchical distribution model, the spatial hierarchy of the chip can be optimized. This helps to reduce the physical area occupied and wiring length of the chip, improve the integration and signal transmission efficiency, and reduce power consumption and delay. The spatial hierarchy optimization model can provide guidance and basis for subsequent chip design and manufacturing. Based on the register transfer level performance data, the power consumption of the synthesized gate-level netlist is predicted. The data path and control logic of the register transfer level are converted into a gate-level netlist representation using a circuit design tool or simulator. The power consumption prediction analysis is performed, and the switching power consumption of the gate-level logic and the charging and discharging power consumption of the input and output capacitors are considered to predict the power consumption of the circuit. The synthesized power consumption prediction data is obtained, including the power consumption estimate of the entire circuit, which is used for subsequent optimization and analysis.Based on the data path control logic model and the synthetic power consumption prediction data, the key component hierarchy is constructed to identify and determine the key components in the circuit, such as high-power modules and frequently used modules, and the key components are organized and distributed in a hierarchical structure for subsequent optimization and layout. A hierarchical structure distribution model is constructed to describe the hierarchical relationship and corresponding distribution mode of the key components, providing a basis for the subsequent spatial hierarchy optimization. Based on the hierarchical structure distribution model, the minimum occupied area integration is carried out, that is, the layout tools are used to layout the components of each level to minimize the occupied area of ​​the chip, considering the location, layout rules and constraints of the key components, and optimizing the space utilization efficiency of the entire chip. The micro-architecture with the minimum wiring length is constructed, and the components of each level are connected to minimize the length of the signal transmission path. Considering the timing requirements of the signal, the delay and power consumption of the circuit, the performance and effect of the wiring are optimized, and the spatial hierarchy optimization model is obtained, including the layout and connection of the components, which is used for subsequent physical design and layout verification.

[0081] Preferably, step S3 comprises the following steps:

[0082] Step S31: performing register transfer level analysis based on the spatial hierarchy optimization model and performing gate-level circuit netlist conversion to obtain gate-level circuit netlist data;

[0083] Step S32: mapping the gate-level circuit netlist data to a logic device layout, thereby obtaining layout layout data;

[0084] Step S33: extracting delay information from the layout data to obtain delay parameter data;

[0085] Step S34: performing static timing verification on the delay parameter data, thereby obtaining static timing verification data;

[0086] Step S35: performing design rule correction and circuit rule correction on the spatial hierarchical structure optimization model according to the static timing verification data, thereby obtaining a hierarchical structure optimization correction model;

[0087] Step S36: Perform embedded spatial balance analysis based on the hierarchical structure optimization correction model to obtain embedded balance analysis data.

[0088] The embodiment of the present invention analyzes the register transfer level based on the spatial hierarchy optimization model, analyzes the spatial hierarchy optimization model, determines the register transfer level of each level, determines the data transmission path between registers, and establishes the dependency relationship between registers. The design of the register transfer level is converted into a gate-level circuit netlist representation, and the logic circuit elements (such as gates, triggers, etc.) are mapped into the gate-level netlist, and the connection relationship between them is established to obtain the gate-level circuit netlist data, including the logic function and connection relationship of the gate-level elements. Based on the gate-level circuit netlist data, the logic device layout mapping is performed, and the logic devices in the gate-level circuit netlist are mapped into the actual layout. Considering the size, shape, layout rules and other factors of the logic devices, the position allocation of the devices is performed, and the connection relationship between the logic devices is established to ensure the correct transmission of the signal. The layout optimization is performed to minimize the area, power consumption and signal delay of the chip, and the layout is optimized and adjusted considering the layout rules, the layout of the power line and the ground line, the timing constraints and other factors, and the layout is optimized and adjusted to obtain the layout layout data, including the position and connection information of the logic devices. Based on the layout data, delay information is extracted, and the delay of each signal path in the layout is analyzed. The propagation delay of the signal is calculated by considering factors such as the path length, capacitance, and resistance of the signal transmission. The delay information of each signal path is extracted, including the starting point, the end point, and the propagation delay, and the delay parameter data is obtained for subsequent static timing verification and design rule correction. Based on the delay parameter data, static timing verification is performed, and the timing constraints of the delay parameter data are verified to ensure that the time when the signal reaches the target point at the clock edge meets the design requirements. The timing path is analyzed to check whether there are timing violations (such as too long paths, violations of timing constraints, etc.), and static timing verification data is obtained, including the status and violation of the timing path, which is used for subsequent design rule correction and hierarchical structure optimization correction. Based on the static timing verification data, the design rules of the spatial hierarchy optimization model are corrected, the timing violations in the static timing verification data are analyzed, and the parts of the design rules that cause the violations are determined. For these problems, the design rules are corrected and adjusted to meet the timing constraints and performance requirements, and the circuit rules are corrected. According to the circuit rule violations in the static timing verification data, the circuit rules are corrected, for example, the layout rules, signal line width, power line and ground line planning are optimized to improve the performance and reliability of the circuit, and the hierarchical optimization correction model is obtained, including the corrected design rules and circuit rules, which are used for subsequent embedded space balance analysis.Based on the hierarchical optimization correction model, embedded space balance analysis is performed to analyze the space balance in the corrected hierarchical model. Factors such as power consumption distribution, signal transmission path length, and positional relationship of circuit modules are considered to evaluate the space balance of the embedded system. The spatial distribution and mutual relationship of each module in the embedded system are analyzed, and the space utilization efficiency and performance balance of the system are evaluated. According to the analysis results, optimization plans are proposed, such as rearrangement of modules, adjustment of the size of circuit modules, etc., to achieve better space balance.

[0089] The present invention firstly performs register transfer level analysis based on a spatial hierarchy optimization model, and can perform more detailed circuit analysis and optimization on the chip. Converting the design of the register transfer level into gate-level circuit netlist data can more directly represent the logical structure and function of the circuit, and the logic device layout mapping converts the gate-level circuit netlist data into actual layout layout data. By performing logic device layout mapping on the gate-level circuit netlist data, the position, layout and connection relationship of each logic device in the circuit can be determined, providing an accurate basis for the delay analysis and verification of the subsequent steps. Delay information extraction is to obtain the delay information of each path in the circuit based on the layout layout data. By performing delay information extraction on the layout layout data, the transmission delay of different paths, the signal arrival time and other timing related parameters can be obtained, and the static timing verification is to verify the timing performance of the circuit based on the delay parameter data. By performing static timing verification on the delay parameter data, the stability of the circuit under different operating conditions, whether the timing relationship and timing constraints are satisfied, and whether there are potential timing faults and conflicts can be analyzed. By correcting the spatial hierarchy optimization model based on static timing verification data, the design rules and circuit rules can be adjusted and corrected based on the verification results to improve the timing performance and stability of the circuit. The requirements and constraints of circuit design can be better met by the hierarchy optimization correction model. Embedded spatial balance analysis is an analysis of the spatial balance of the circuit based on the hierarchy optimization correction model. By performing embedded spatial balance analysis based on the hierarchy optimization correction model, the balance of the circuit layout, the length of the connection and the complexity of the wiring, as well as the impact on power consumption, timing and performance can be evaluated. This helps to optimize the layout structure of the circuit and improve the performance and reliability of the chip.

[0090] Preferably, step S36 includes the following steps:

[0091] Step S361: dividing the hierarchical structure optimization and correction model into three levels, thereby obtaining chip-level structure data, module-level structure data, and sub-module-level structure data;

[0092] Step S362: marking the chip-level structure data, the module-level structure data, and the sub-module-level structure data with shared resource nodes, thereby obtaining shared resource node data;

[0093] Step S363: using the random forest algorithm and according to the shared resource node data, the hierarchical structure optimization and correction model is iterated for optimal integration, thereby obtaining an optimized integrated hierarchical model;

[0094] Step S364: performing wiring level area balance on the optimized integrated level model, thereby obtaining a level structure balance model;

[0095] Step S365: Perform embedded space balance analysis based on the hierarchical balance model to obtain embedded balance analysis data, wherein the embedded space balance analysis includes resource utilization balance analysis at different levels, performance indicator balance analysis at different levels, module spacing balance analysis, and redundancy balance analysis.

[0096] The embodiment of the present invention analyzes the revised hierarchical structure model, determines the structural division of chip level, module level and submodule level, determines the module and submodule boundaries of each level, and establishes the hierarchical relationship between them, performs hierarchical division, and obtains chip level structural data, module level structural data and submodule level structural data. The structural data of each level is analyzed to identify nodes with shared resources, which can be logic units, storage units, clock networks, etc. The shared resource nodes are marked as sharable nodes, and their attributes and connection relationships are recorded. The shared resource node data is used as a training set, and the random forest algorithm is used to train and optimize the model, set the integration parameters, and control the degree of integration to balance performance and resource utilization. According to the results of the random forest algorithm, the hierarchical structure optimization correction model is iteratively optimized, and the allocation of shared resource nodes, the location and connection relationship of modules, etc. are adjusted to achieve an optimized integrated hierarchical model. The integrated hierarchical model is routed, considering the signal transmission path and resource allocation. According to the routing results, the area share and layout of modules and sub-modules at different levels are analyzed. According to the routing results, the position and layout of modules and sub-modules at different levels are adjusted to achieve the balance of the hierarchy. Factors such as area utilization, routing length, and signal transmission delay are considered to optimize the hierarchical balance model. The resource utilization balance at different levels is analyzed, including computing resources, storage resources, and communication resources. The performance index balance at different levels is analyzed, such as clock frequency, power consumption, and response time. The module spacing balance is analyzed to ensure that the distance between modules is appropriate to reduce signal transmission delay and power consumption. The redundancy balance is analyzed to avoid redundancy between modules and improve resource utilization and performance. The embedded space balance analysis results are sorted and summarized to generate embedded balance analysis data. The embedded balance analysis data can include resource utilization balance indicators, performance index balance indicators, module spacing indicators, and redundancy indicators.

[0097] The present invention first divides the hierarchical structure optimization correction model into three levels, so that the complex chip design can be decomposed into smaller modules and submodules, which is convenient for subsequent analysis and optimization. Obtaining chip-level structure data, module-level structure data and submodule-level structure data is helpful for independent processing and detailed analysis of designs at different levels, and improving the flexibility and manageability of the design. Shared resource node marking is to mark and identify shared resource nodes in chip-level structure data, module-level structure data and submodule-level structure data. By marking shared resource nodes, it can be determined which resources are shared and used in designs at different levels, providing a basis for subsequent optimization and resource management. Obtaining shared resource node data is helpful for optimizing resource utilization and layout effects of the design. Using a random forest algorithm and performing optimal integration iteration according to shared resource node data, the design of the hierarchical structure optimization correction model can be optimized. Through iterative optimization, the best hierarchical division and resource utilization scheme can be found to improve the overall performance and efficiency of the design. Obtaining an optimized integrated hierarchical model is helpful to further improve the comprehensive performance and resource utilization of the design. Wiring hierarchical area balance is to consider the area balance of different levels when wiring the optimized integrated hierarchical model. By balancing the routing density and area distribution at different levels, performance and signal integrity issues caused by overly concentrated or uneven routing can be avoided. Obtaining a hierarchical balance model helps optimize routing results and improve circuit reliability and performance. Embedded spatial balance analysis based on the hierarchical balance model can evaluate the balance of resource utilization, performance indicators, module spacing, and redundancy at different levels. By analyzing and optimizing these aspects, the spatial balance, performance, and resource utilization efficiency of the circuit can be further improved. Embedded balance analysis data provides designers with quantitative indicators and feedback.

[0098] Preferably, step S4 comprises the following steps:

[0099] Step S41: performing feature vector dimensionality reduction on the embedded balance analysis data, thereby obtaining balanced low-dimensional vector data;

[0100] Step S42: performing micro-architecture space utilization prediction based on the spatial hierarchy optimization model and the balanced low-dimensional vector data, thereby obtaining space utilization prediction data;

[0101] Step S43: Perform embedded learning migration on the spatial hierarchy optimization model according to the spatial utilization prediction data, so as to obtain a spatial utilization optimization model.

[0102] The embodiment of the present invention performs dimensionality reduction processing on the embedded balanced analysis data by using a dimensionality reduction algorithm, such as principal component analysis (PCA) or linear discriminant analysis (LDA), and determines the number of principal components retained or the dimension after dimensionality reduction according to the amount of information retained or the variance explanation ratio. The spatial hierarchy optimization model is designed to maximize the utilization of hardware resources. The model may include multiple levels, each level represents a different module or sub-module. The goal of micro-architecture space utilization prediction is to predict the space utilization of each module or sub-module on the actual hardware based on the balanced low-dimensional vector data. When making a prediction, a regression model or a deep neural network model can be used to predict the space utilization of each module or sub-module based on the input balanced low-dimensional vector data. The space utilization prediction data should include the space utilization information of each module or sub-module so that the subsequent optimization steps can use these data for decision-making and adjustment. The knowledge learned from the space utilization prediction data is transferred to the spatial hierarchy optimization model, which may include domain adaptation and knowledge distillation. Domain adaptation aims to adapt the model to new tasks by adjusting the parameters or feature representation of the model. Knowledge distillation aims to train a new model by taking the prediction results as the target so that the new model can learn the knowledge in the prediction data. Based on the model after learning transfer, a space utilization optimization model is obtained, which can better optimize the spatial hierarchy and improve the space utilization of chip design.

[0103] The present invention firstly reduces the dimension of the feature vector of the embedded balance analysis data, so that the original data can be converted into a low-dimensional vector, thereby reducing the dimension and complexity of the data. The balanced low-dimensional vector data after dimensionality reduction retains the most important features in the original data, which helps to improve the computing efficiency and reduce the demand for storage space. At the same time, dimensionality reduction can also remove noise and redundant information, and improve the effect of subsequent analysis and modeling. Prediction of micro-architecture space utilization based on the spatial hierarchy optimization model can estimate the space utilization of the micro-architecture according to the input balanced low-dimensional vector data. Such prediction data can help designers understand the space utilization of different parts and guide the optimization and adjustment of the design. By predicting the space utilization, the designer can evaluate and optimize the allocation of space resources in the design stage, and improve the efficiency and performance of the design. Embedded learning transfer of the spatial hierarchy optimization model based on the space utilization prediction data can use the prediction results to optimize and improve the original optimization model. Through learning transfer, the knowledge and experience that have been learned can be applied to the new space utilization optimization model to improve the performance and effect of the model. After obtaining the space utilization optimization model, it can be used to guide the subsequent design and optimization process to achieve better space resource utilization and performance.

[0104] Preferably, the present invention also provides a chip designed and manufactured by the chip design method for optimizing space utilization as described above.

[0105] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0106] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A chip design method for optimizing space utilization, characterized in that: The following steps are involved: Step S1: Obtain chip historical component data and register transfer level data; perform local optimal analysis on the chip historical component data to obtain local optimal component data; perform stochastic gradient analysis on the register transfer level data under the condition that timing constraints are satisfied to obtain optimized circuit parameter mapping data; Step S2: obtaining chip design index data and chip component data; performing local optimal matching of the local optimal component data and the chip design index data, thereby obtaining the optimal index component data; constructing a micro-architecture for the chip component data and the optimized circuit parameter mapping data according to the optimal index component data, thereby obtaining a spatial hierarchical structure optimization model; Step S2 includes the following steps: Step S21: Acquire chip design index data and chip component data; Step S22: constructing a thermal environment regression neural network for the local optimal component data and the chip design index data, thereby obtaining a thermal environment regression model; Step S23: performing dynamic power consumption prediction based on the thermal environment regression model, thereby obtaining dynamic power consumption prediction data; Step S24: performing local optimal matching of the dynamic power consumption prediction data and the chip design index data, thereby obtaining optimal index component data; Step S25: dividing the chip component data into logical modules according to the optimal index component data, thereby obtaining a logical module division data set; Step S26: performing optimal data path parameter analysis on the optimized circuit parameter mapping data and the logic module partition data set, thereby obtaining optimal data path data; Step S27: classifying the flow modes between adjacent logic modules for the optimal data path data, thereby obtaining the connection flow module path data; Step S28: integrating the connection flow module path data with the minimum occupied area and constructing a micro-architecture with the minimum wiring length, thereby obtaining a spatial hierarchical structure optimization model; Step S28 includes the following steps: Step S281: constructing a data path graph with optimal performance for connecting flow module path data, thereby obtaining an optimal performance data path model, wherein the data path graph with optimal performance includes flow path construction, data width weighting, and key component distribution construction; Step S282: performing control relationship analysis between chip functional modules based on the optimal performance data path model, thereby obtaining control relationship analysis data; Step S283: performing timing constraint analysis on chip component data based on the optimal performance data path model and the control relationship analysis data, thereby obtaining a data path control logic model, wherein the timing constraint analysis includes clock control analysis, state machine analysis, and control signal analysis of each module; Step S284: performing simulated high-level synthesis processing on the optimized circuit parameter mapping data based on the data path control logic model, thereby obtaining register transfer level performance data; Step S285: performing a synthesized gate-level netlist power consumption prediction on the register transfer level performance data, thereby obtaining synthesized power consumption prediction data; Step S286: constructing a key component hierarchy for the optimized circuit parameter mapping data based on the data path control logic model and according to the synthetic power consumption prediction data, thereby obtaining a hierarchical structure distribution model; Step S287: performing minimum occupied area integration and minimum wiring length micro-architecture construction on the hierarchical structure distribution model, thereby obtaining a spatial hierarchical structure optimization model; Step S3: performing embedded spatial balance analysis based on the spatial hierarchy optimization model, thereby obtaining embedded balance analysis data; Step S3 includes the following steps: Step S31: performing register transfer level analysis based on the spatial hierarchy optimization model and performing gate-level circuit netlist conversion to obtain gate-level circuit netlist data; Step S32: mapping the gate-level circuit netlist data to a logic device layout, thereby obtaining layout layout data; Step S33: extracting delay information from the layout data to obtain delay parameter data; Step S34: performing static timing verification on the delay parameter data, thereby obtaining static timing verification data; Step S35: performing design rule correction and circuit rule correction on the spatial hierarchical structure optimization model according to the static timing verification data, thereby obtaining a hierarchical structure optimization correction model; Step S36: performing embedded spatial balance analysis based on the hierarchical structure optimization correction model, thereby obtaining embedded balance analysis data; Step S36 includes the following steps: Step S361: dividing the hierarchical structure optimization and correction model into three levels, thereby obtaining chip-level structure data, module-level structure data, and sub-module-level structure data; Step S362: marking the chip-level structure data, the module-level structure data, and the sub-module-level structure data with shared resource nodes, thereby obtaining shared resource node data; Step S363: using the random forest algorithm and according to the shared resource node data, the hierarchical structure optimization and correction model is iterated for optimal integration, thereby obtaining an optimized integrated hierarchical model; Step S364: performing wiring level area balance on the optimized integrated level model, thereby obtaining a level structure balance model; Step S365: performing embedded space balance analysis based on the hierarchical structure balance model to obtain embedded balance analysis data, wherein the embedded space balance analysis includes resource utilization balance analysis at different levels, performance index balance analysis at different levels, module spacing balance analysis, and redundancy balance analysis; Step S4: Perform embedded learning migration on the spatial hierarchy optimization model according to the embedded balance analysis data, so as to obtain a spatial utilization optimization model.

2. The method for designing a chip with optimized space utilization according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: Acquire chip historical component data, wherein the chip historical component data includes component performance historical data, electrical parameter historical data, and process characteristic historical data; Step S12: clustering the component performance history data and the electrical parameter history data according to the process characteristic history data, thereby obtaining chip component clustering data, wherein the data clustering includes component material characteristic clustering and component connection timing characteristic clustering; Step S13: performing local optimal analysis of different components on the chip component clustering data, thereby obtaining local optimal component data, wherein the local optimal analysis of different components includes local optimal analysis of performance, local optimal analysis of power consumption, and local optimal analysis of area utilization, wherein the local optimal analysis of power consumption includes power consumption analysis at different temperatures and power consumption analysis at different workloads; Step S14: acquiring register transfer level data, wherein the register transfer level data includes circuit logic history data, circuit structure history data and time constraint history data; Step S15: performing random gradient analysis on the register transfer level data under the condition that the timing constraints are satisfied, thereby obtaining optimized circuit parameter mapping data.

3. The method for designing a chip for optimizing space utilization according to claim 2, characterized in that: Step S15 includes the following steps: Step S151: performing logic module identification on the circuit logic history data, thereby obtaining logic module data; Step S152: constructing component connection relationships for circuit logic history data according to logic module data, thereby obtaining a component connection relationship network model; Step S153: performing a signal transmission path relationship analysis between logic modules on the component connection relationship network model, thereby obtaining signal transmission path relationship data, wherein the signal transmission path relationship analysis between logic modules includes a signal input relationship analysis, an output relationship analysis, and a timing relationship analysis; Step S154: constructing a component logic diagram for the signal transmission path relationship data, thereby obtaining a component logic network model; Step S155: performing key component layout analysis on the circuit structure history data to obtain key component layout data, wherein the key component layout analysis includes logic module layout analysis, register layout analysis, and memory layout analysis; Step S156: constructing a component space model for the circuit structure history data according to the key component layout data, thereby obtaining a component space model, wherein the component space model construction includes relative position vector layout and wiring rule vector layout; Step S157: performing layout space constraint analysis between components on the component space model, thereby obtaining component layout constraint analysis data, wherein the layout space constraint analysis between components includes physical constraint analysis and signal transmission path length constraint analysis; Step S158: performing two-dimensional plane abstract mapping on the component space model according to the component layout constraint analysis data, thereby obtaining a layout space model; Step S159: performing stochastic gradient analysis on the component logic network model and the layout space model under the condition that the timing constraints are satisfied, so as to obtain optimized circuit parameter mapping data.

4. The method for designing a chip with optimized space utilization according to claim 3, characterized in that: Step S159 includes the following steps: According to the key component layout data, feature matching is performed on the component logic network model and the layout space model to obtain a circuit logic distribution model; Performing timing relationship constraint analysis on the time constraint history data based on the circuit logic distribution model, thereby obtaining timing relationship data, wherein the timing relationship data includes signal transmission delay relationship data, clock frequency relationship data and data path relationship data; Performing full convolution mapping of parameters on the circuit logic distribution model according to the signal transmission delay relationship data, the clock frequency relationship data, and the data path relationship data, thereby obtaining mapping parameter data; The mapping parameter data is subjected to random gradient analysis under the condition that the timing constraints are satisfied, thereby obtaining the optimized circuit parameter mapping data.

5. The method for designing a chip with optimized space utilization according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: performing feature vector dimensionality reduction on the embedded balance analysis data, thereby obtaining balanced low-dimensional vector data; Step S42: performing micro-architecture space utilization prediction based on the spatial hierarchy optimization model and the balanced low-dimensional vector data, thereby obtaining space utilization prediction data; Step S43: Perform embedded learning migration on the spatial hierarchy optimization model according to the spatial utilization prediction data, so as to obtain a spatial utilization optimization model.

6. A chip, characterized in that: The chip is designed and manufactured by the method for designing a chip with optimized space utilization as claimed in claim 1.

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