Preparation method of stacked forkplate transistor, stacked forkplate transistor and electronic device

Abstract

The present application provides a method for preparing a stacked forkplate transistor, a stacked forkplate transistor, and an electronic device. The invention provides a method for connecting power rails of a stacked forkplate transistor, a stacked forkplate transistor, a device, and an apparatus. The method includes: forming a first semiconductor structure on a substrate; forming a first power rail on the first semiconductor structure; forming a first dielectric wall structure on the first power rail; removing a second sacrificial layer and forming a first metal connection structure connected to the first power rail in a first source structure; forming a first metal interconnect layer on the second semiconductor structure and a third semiconductor structure; flipping the second and third semiconductor structures; removing a portion of the substrate and the shallow trench sacrificial layer until the second portions of a pair of active structures are exposed; forming a second dielectric wall structure between the second portions of the pair of active structures; and forming a second metal interconnect layer on the fourth and fifth semiconductor structures. The present application can improve the integration density of transistors.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a method for preparing a stacked forkplate transistor, a stacked forkplate transistor, and an electronic device. Background Art

[0002] As Moore's Law continues to deepen, further advancing transistor scaling is a hot topic in the industry. Stacked transistors, by integrating two or more layers of transistors vertically, further increase transistor integration density and become a key technology for further scaling integrated circuits.

[0003] When using a conventional monolithic solution to prepare stacked transistors, there is a problem of difficulty in increasing the integration density of the transistors. Summary of the Invention

[0004] The present application provides a method for preparing a stacked forkplate transistor, a stacked forkplate transistor, and an electronic device to improve the integration density of the transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked forkplate transistor, the method comprising: forming a first semiconductor structure on a substrate, the first semiconductor structure comprising: a pair of active structures and a shallow trench isolation layer, wherein the active structure comprises a first portion and a second portion, the first portion being farther away from the substrate than the second portion, and at least a first sacrificial layer and an isolation layer stacked in sequence are provided between the first portion and the second portion in a direction perpendicular to the substrate; the shallow trench isolation layer wraps the first portion and is flush with the first sacrificial layer; forming a first power rail on the first semiconductor structure, the first power rail being located between the first portions of the pair of active structures; forming a first dielectric wall structure on the first power rail; forming a second semiconductor structure and a third semiconductor structure based on the first portions of the pair of active structures, the second semiconductor structure comprising a first gate structure, a first source structure, and a first drain structure, and the third semiconductor structure comprising a second gate structure, a second source structure, and a second drain structure; the first The gate structure and the second gate structure are isolated by a first dielectric wall fork plate on the first dielectric wall structure; the isolation layer is removed, and a first metal connection structure connected to the first power rail is formed in the first source structure; a first metal interconnection layer is formed on the second semiconductor structure and the third semiconductor structure; the second semiconductor structure and the third semiconductor structure are flipped; a portion of the substrate and the shallow trench isolation layer is removed until the second portion of the pair of active structures is exposed; a second dielectric wall structure is formed between the second portions of the pair of active structures; a fourth semiconductor structure and a fifth semiconductor structure are formed based on the second portions of the pair of active structures, the fourth semiconductor structure including a third gate structure, a third source structure and a third drain structure, and the fifth semiconductor structure including a fourth gate structure, a third source structure and a fourth drain structure; the third gate structure and the fourth gate structure are isolated by the second dielectric wall fork plate on the second dielectric wall structure; and a second metal interconnection layer is formed on the fourth semiconductor structure and the fifth semiconductor structure.

[0006] In some possible implementations, after removing the isolation layer, the method further includes: forming a second metal connection structure connected to the first power rail in the second source structure.

[0007] In some possible embodiments, a second sacrificial layer is further provided between the first portion and the second portion in a direction perpendicular to the substrate, and the second sacrificial layer is closer to the second portion than the first sacrificial layer; after removing a portion of the substrate and the shallow trench isolation layer until the second portion of the pair of active structures is exposed, the above method further includes: forming a second power rail on another portion of the shallow trench isolation layer, and the above second power rail is located between the second portions of the pair of active structures; after forming the fourth semiconductor structure and the fifth semiconductor structure based on the second portions of the pair of active structures, the above method further includes: removing the second sacrificial layer, and forming a third metal connection structure connected to the second power rail in the third source structure.

[0008] In some possible implementations, after removing the second sacrificial layer, the method further includes: forming a fourth metal connection structure connected to the second power rail in the fourth source structure.

[0009] In some possible embodiments, forming a first power rail on a first semiconductor structure includes: depositing an oxide material on the first semiconductor structure to form a first insulating layer; depositing a metal material on the first insulating layer to form a first metal structure; etching the first metal structure to a preset height to form a second metal structure; etching an area of ​​the second metal structure outside the first portion of a pair of active structures to obtain a third metal structure located between the second portions of the pair of active structures; and depositing oxide on the third metal structure to form the first power rail.

[0010] In some possible embodiments, forming a first metal connection structure connected to the first power rail in the first source structure includes: depositing a semiconductor material on the first source structure to form an interlayer dielectric layer; etching the interlayer dielectric layer until the first power rail is exposed to form a first trench; and filling the first trench with a metal material to form the first metal connection structure.

[0011] In some possible implementations, after forming the first dielectric wall structure on the first power rail, the method further includes: forming a first dielectric wall fork plate on the first dielectric wall structure based on an isolation material.

[0012] In a second aspect, embodiments of the present application provide a stacked forkplate transistor, comprising: a second semiconductor structure, a third semiconductor structure, a fourth semiconductor structure, a fifth semiconductor structure, a first power rail, a first dielectric wall structure, a first dielectric wall forkplate, a second dielectric wall structure, and a second dielectric wall forkplate, wherein the first dielectric wall forkplate is located on the first dielectric wall structure, and the second dielectric wall forkplate is located on the second dielectric wall structure; the first power rail is located between the second semiconductor structure and the third semiconductor structure. The second semiconductor structure comprises a first gate structure, a first source structure, and a first drain structure; the third semiconductor structure comprises a second gate structure, a second source structure, and a second drain structure; the first gate structure and the second gate structure are isolated by the first dielectric wall forkplate; the fourth semiconductor structure comprises a third gate structure, a third source structure, and a third drain structure; the fifth semiconductor structure comprises a fourth gate structure, a fourth source structure, and a fourth drain structure; the third gate structure and the fourth gate structure are isolated by the second dielectric wall forkplate. The stacked forkplate transistor further includes at least one of the following: the second semiconductor structure further includes a first metal connection structure, the first metal connection structure is connected to the first source structure and the first power rail; the third semiconductor structure further includes a second metal connection structure, the second metal connection structure is connected to the second source structure and the first power rail.

[0013] In some possible embodiments, the stacked forkplate transistor further includes a second power rail, where the second power rail is located between the fourth semiconductor structure and the fifth semiconductor structure; the stacked forkplate transistor further includes at least one of the following: the fourth semiconductor structure further includes a third metal connection structure, where the third metal connection structure is connected to the third source structure and the second power rail; the fifth semiconductor structure further includes a fourth metal connection structure, where the fourth metal connection structure is connected to the fourth source structure and the second power rail.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a stacked fork-plate transistor as described in the above embodiment, wherein the stacked fork-plate transistor is disposed on the circuit board.

[0015] In this application, a first power rail is formed on a first semiconductor structure, a first dielectric wall structure is formed on the first power rail, and a first dielectric wall fork is formed on the first dielectric wall structure to isolate a second semiconductor from a third semiconductor. The second and third semiconductors are symmetrically arranged on either side of the first dielectric wall fork. The isolation layer vertically disposed between the first and second portions of the active structure is removed, and a first metal connection structure connected to the first power rail is formed in the first source structure of the second semiconductor. The first dielectric wall fork isolates the second and third semiconductors, thereby reducing the spacing between the symmetrically positioned devices on either side of the first dielectric wall fork and improving integration density. Furthermore, by arranging the first power rail at the first dielectric wall fork and using a wraparound connection from the bottom of the first source structure, resistance can be reduced.

[0016] Furthermore, the stacked forkplate transistor realizes the combination of the stacked transistor and the forkplate transistor, and further improves the integration density while achieving self-alignment between the second semiconductor and the fourth semiconductor and the third semiconductor and the fourth semiconductor.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 Schematic diagram of an implementation process of a method for preparing a stacked fork-plate transistor according to an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a structure of a stacked fork-plate transistor in an embodiment of the present application;

[0021] Figures 3 to 29 A schematic diagram of a preparation process of a stacked fork-plate transistor according to an embodiment of the present application;

[0022] The above pictures:

[0023] 10. Stacked forkplate transistor; 20. Active structure; 201. First portion of active structure; 202. Second portion of active structure; 21. First initial stacked structure; 21A. First isolation layer; 21B. First semiconductor layer; 22. Second initial stacked structure; 22A. Second isolation layer; 22B. Second semiconductor layer; 23. Intermediate layer; 231. First sacrificial layer; 231a. New first sacrificial layer; 232. Third isolation layer; 233. Second sacrificial layer; 24. Substrate; 251. First insulating layer; 252. Second insulating layer; 253. Third insulating layer; 261. First metal structure; 262. Second metal structure; 271. First power rail; 272. Second power rail; 280. Dielectric layer; 281. First dielectric wall structure; 282. Second dielectric wall structure; 291. First dielectric wall forkplate; 292. Second dielectric wall forkplate; 30. Shallow trench isolation layer ;31. Second semiconductor;311. First gate structure;312. First source structure;313. First drain structure;41. Third semiconductor;411. Second gate structure;412. Second source structure;413. Second drain structure;51. Fourth semiconductor;511. Third gate structure;512. Third source structure;513. Third drain structure;61. Fifth semiconductor;611. Fourth gate structure;612. Fourth source structure;613. Fourth drain structure;71. Interlayer dielectric layer;711. First trench;712. First metal interconnection structure;713. Second metal interconnection structure;715. First metal interconnection layer;714. Second metal interconnection layer;716. Third metal interconnection structure;717. Fourth metal interconnection structure;81. Patterned mask layer;821. First dielectric layer;822. Second dielectric layer;83. Pseudo-gate structure;a. Spacer layer. DETAILED DESCRIPTION

[0024] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0025] As Moore's Law continues to deepen, further scaling transistors beyond the gate-all-around FET (GAA) technology node is a hot topic in the industry. Stacked transistors, through three-dimensional transistor stacking, enable the integration of two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered a key technology for continuing integrated circuit scaling.

[0026] In one embodiment, there are two schemes for fabricating stacked transistors. The first scheme is a monolithic stacking scheme, and the second scheme is a sequential scheme.

[0027] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This means that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layers of transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0028] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding a wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection line. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of a high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonded wafer; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0029] The common technical difficulties faced by the above two solutions include: 1) the thermal stability of the lower layer devices when making the upper layer devices; 2) the performance of the upper layer devices under low thermal budget; (3) the metal interconnection of transistors between layers.

[0030] In order to solve the technical problems existing in the above two solutions, a self-aligned stacked transistor is proposed, which forms active areas of upper and lower layers of homologous transistors by etching, and realizes the production of stacked transistors on the front and back of the wafer by flipping the wafer to overcome the shortcomings of the above two solutions. The stacked transistor includes a stacked first transistor and a second transistor. The various terminals of the stacked transistor (such as source, drain and gate, etc.) are respectively connected to multiple power rails (Power Rail) and multiple signal lines. The traditional interconnection scheme is based on planar interconnection to arrange multiple power rails and multiple signal lines on the same interconnection layer (for example, M0 layer). Due to the large area of ​​the power rails, the planar area occupied by the multiple power rails formed is large, which limits the further miniaturization of the size of the semiconductor device 100.

[0031] A certain spacing must be maintained between the two types of transistors, N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS), that make up complementary metal oxide semiconductor (CMOS) logic to limit the capacitance that weakens device performance and affects power consumption, and to reduce interference between adjacent transistors. This spacing limits the scaling of nanosheet-based logic. Forksheet transistors are a way to break this limitation. The construction scheme of forksheets is to place transistors in pairs on both sides of a dielectric wall. The dielectric wall allows devices to be placed closely without causing capacitance problems. Designers can use the newly added space to shrink logic units, or use the existing space to make wider transistors for better performance.

[0032] However, current forksheets are based on a monolithic solution, which not only suffers from similar issues as the aforementioned monolithic stacked transistors, but also has certain limitations on transistor integration density. Furthermore, the interconnection of transistors requires power rails and signal lines to be placed on the M0 interconnect layer. The large area of ​​the power rails and the large number of signal lines occupy a large area on the M0 layer, limiting further scaling of semiconductor devices.

[0033] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a stacked fork-plate transistor to improve the integration density of the transistor.

[0034] In the embodiments of the present application, the stacked fork transistor can be applied to semiconductor devices such as memories and processors.

[0035] In some embodiments, a stacked forkplate transistor may include a second semiconductor structure, a third semiconductor structure, a fourth semiconductor structure, a fifth semiconductor structure, a first power rail, a first dielectric wall structure, a first dielectric wall forkplate, a second dielectric wall structure, and a second dielectric wall forkplate, wherein the first dielectric wall forkplate is located on the first dielectric wall structure and the second dielectric wall forkplate is located on the second dielectric wall structure; the first power rail is located between the second semiconductor structure and the third semiconductor structure; the second semiconductor structure includes a first gate structure, a first source structure, and a first drain structure; the third semiconductor structure includes a second gate structure, a second source structure, and a second drain structure; the first gate structure and the second gate structure are isolated by the first dielectric wall forkplate; the fourth semiconductor structure includes a third gate structure, a third source structure, and a third drain structure; the fifth semiconductor structure includes a fourth gate structure, a fourth source structure, and a fourth drain structure; the third gate structure and the fourth gate structure are isolated by the second dielectric wall forkplate.

[0036] In the embodiments of the present application, the second semiconductor, third semiconductor, fourth semiconductor, and fifth semiconductor in the stacked forkplate transistor can be transistors of the same type, such as any of the following: nanosheet field-effect transistors, fin-type field-effect transistors, planar transistors, etc. Specifically, as a forkplate transistor, the second and third semiconductors are located in the front region, and the fourth and fifth semiconductors are located in the back region. The second and third semiconductors can be transistors of the same type (such as NFETs or PFETs) or different types (such as NFETs and PFETs). Correspondingly, the fourth and fifth semiconductors can be transistors of the same type or different types. The embodiments of the present application do not specifically limit the types of the multiple transistors in the forkplate transistor in the front region or the back region.

[0037] Figure 2 The stacked fork plate transistor composed of nanosheet field effect transistors is combined below Figure 2 The structure of the stacked forkplate transistor shown is used to illustrate the method for preparing the stacked forkplate transistor provided in the embodiment of the present application.

[0038] Figure 1 This is a schematic diagram of an implementation flow of a method for connecting power rails of stacked fork-plate transistors in an embodiment of the present application, see Figure 1 As shown, the power rail connection method of the stacked fork plate transistors may include:

[0039] S101, forming a first semiconductor structure on a substrate.

[0040] The first semiconductor structure includes a pair of active structures and a shallow trench isolation layer.

[0041] It can be understood that the above-mentioned active structure includes a first part and a second part, the first part is farther away from the substrate than the second part, and at least a first isolation layer and a second isolation layer stacked in sequence are arranged between the first part and the second part; the shallow trench isolation layer wraps the first part and is flush with the first isolation layer.

[0042] In some embodiments, the first portion and the second portion may be composed of alternately stacked sacrificial layers and semiconductor layers. The first portion may also be referred to as a first stacking structure, and the second portion may also be referred to as a second stacking structure.

[0043] In some embodiments, a third isolation layer is further provided between the first portion and the second portion along a direction perpendicular to the substrate, and the third isolation layer is closer to the second portion than the first isolation layer.

[0044] In some embodiments, the shallow trench isolation layer material may be nitride, oxide (such as tetraethyl orthosilicate (TEOS)), or other semiconductor materials, which is not specifically limited in the embodiments of the present application.

[0045] In some embodiments, when the stacked forkplate transistor is a nanosheet field-effect transistor, the thickness of the silicon layer located on the substrate can be greater than the thickness of other silicon layers in the stack of active structures. The substrate is formed based on the bottom silicon layer of a pair of active structures, and material layers of different materials are deposited in sequence.

[0046] S102 , forming a first power rail on the first semiconductor structure.

[0047] The first power rail is located between the first portions of the pair of active structures.

[0048] In some embodiments, after forming a first semiconductor structure on a substrate, an oxide material is deposited on the first semiconductor structure to form a first insulating layer; a metal material is deposited on the first insulating layer to form a first metal structure; the first metal structure is etched to a preset height to form a second metal structure; an area of ​​the second metal structure outside the first portion of a pair of active structures is etched to obtain a third metal structure located between the second portions of the pair of active structures; and an oxide is deposited on the third metal structure to form a first power rail, wherein the first power rail is located between the first portions of the pair of active structures.

[0049] In some embodiments, the preset height is lower than the height of the first portion of the active structure, which is not limited here.

[0050] It is understood that the power rail is used to power the transistors. The purpose of providing the power rail is to subsequently connect to the first source metal to power the stacked forkplate transistors. In one example, the power rail can be VSS of the stacked forkplate transistors or VDD of the stacked forkplate transistors.

[0051] S103 , forming a first dielectric wall structure on the first power rail.

[0052] In some embodiments, after forming a first power rail on the first semiconductor structure, a dielectric material is deposited on the first power rail to form an initial dielectric wall structure, and the initial dielectric wall structure covering the first power rail is etched until the lower surfaces of the second semiconductor and the third semiconductor. The dielectric material deposited between the second semiconductor and the third semiconductor that is not removed forms the first dielectric wall structure.

[0053] It should be noted that when filling the dielectric material, the height of the initial dielectric wall structure between the pair of active structures can be made greater than the height of the initial dielectric wall structure outside the pair of active structures by controlling the film deposition rate and / or time. In this way, when etching back the initial dielectric wall structure, the initial dielectric wall structure outside the pair of active structures is completely removed, while the initial dielectric wall structure between the pair of active structures still remains. Of course, in other embodiments, the first dielectric wall structure can also be formed by etching the initial dielectric wall structure multiple times.

[0054] S104 , forming a second semiconductor structure and a third semiconductor structure based on the first portion of the pair of active structures.

[0055] In some embodiments, after forming a first dielectric wall structure on the first power rail, a second semiconductor structure and a third semiconductor structure are formed based on the first portion of a pair of active structures. The second semiconductor structure includes a first gate structure, a first source structure, and a first drain structure. The third semiconductor structure includes a second gate structure, a second source structure, and a second drain structure. The first gate structure and the second gate structure are isolated by a first dielectric wall fork plate on the first dielectric wall structure.

[0056] In some embodiments, after forming the first source / drain structure, an interlayer dielectric may be deposited on the first source / drain structure, thinned to the top layer of the first source / drain structure to form a first interlayer dielectric layer, and then a first source / drain metal may be formed in the first interlayer dielectric layer.

[0057] It should be noted that the first source / drain structure, the first source / drain metal and the first interlayer dielectric layer can all be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0058] In practical applications, the source / drain structure can be doped according to circuit design requirements to change the polarity of the semiconductor layer, thereby forming a P-type or N-type transistor.

[0059] S105 , removing the second isolation layer, and forming a first metal connection structure connected to the first power rail in the first source structure.

[0060] In some embodiments, after forming a second semiconductor structure and a third semiconductor structure based on a first portion of a pair of active structures, a semiconductor material is deposited on the first source structure to form an interlayer dielectric layer; the interlayer dielectric layer is etched until the first power rail is exposed to form a first trench; and a metal material is filled in the first trench to form a first metal connection structure.

[0061] In some embodiments, the above S105 may include forming a second metal connection structure connected to the first power rail in the second source structure.

[0062] It can be understood that one end of the first power rail connecting metal is connected to the first source metal in the first source-drain metal, and the other end is connected to the first power rail, so that the first power rail can supply power to the first transistor through the first power rail connecting metal.

[0063] In one example, the operations of forming the first source-drain metal on the first source-drain structure and forming the first power rail connecting metal on the first power rail can be performed simultaneously, and the metal material of the first source-drain metal and the metal material of the first power rail connecting metal can be the same.

[0064] S106 , forming a first metal interconnection layer on the second semiconductor structure and the third semiconductor structure.

[0065] It can be understood that after removing the second isolation layer and forming a first metal connection structure connected to the first power rail in the first source structure, a first metal interconnection layer is formed on the second semiconductor structure and the third semiconductor structure using a standard process based on circuit design requirements.

[0066] S107 , flipping the second semiconductor structure and the third semiconductor structure.

[0067] It can be understood that after the first metal interconnection layer is formed, the second semiconductor structure and the third semiconductor structure are flipped over.

[0068] S108 , removing a portion of the substrate and the shallow trench isolation layer until the second portion of the pair of active structures is exposed.

[0069] It can be understood that after flipping the second semiconductor structure and the third semiconductor structure, a portion of the substrate and the shallow trench isolation layer is removed until the second portion of the pair of active structures is exposed.

[0070] In some possible embodiments, after S108 , the method further includes: forming a second power rail on another portion of the shallow trench isolation layer, wherein the second power rail is located between the second portions of the pair of active structures.

[0071] S109 , forming a second dielectric wall structure between the second portions of the pair of active structures.

[0072] It can be understood that after forming the second power rail on the first semiconductor structure, a dielectric material is deposited on the second power rail, and the dielectric material covering the second power rail is etched to form a second dielectric wall structure.

[0073] S110 , forming a fourth semiconductor structure and a fifth semiconductor structure based on the second portion of the pair of active structures.

[0074] It can be understood that after the second dielectric wall structure is formed between the second portions of the pair of active structures, a fourth semiconductor structure and a fifth semiconductor structure are formed based on the second portions of the pair of active structures. The fourth semiconductor structure includes a third gate structure, a third source structure, and a third drain structure, and the fifth semiconductor structure includes a fourth gate structure, a third source structure, and a fourth drain structure. The third gate structure and the fourth gate structure are isolated by the second dielectric wall fork plate on the second dielectric wall structure.

[0075] In some embodiments, after forming a second power rail on the first semiconductor structure, a dielectric material is deposited on the second power rail, and the dielectric material covering the second power rail is etched until the lower surface of the fourth semiconductor and the fifth semiconductor. The dielectric material deposited between the fourth semiconductor and the fifth semiconductor that is not removed forms a second dielectric wall structure.

[0076] In some possible embodiments, after S110 , the method further includes: removing the third isolation layer, and forming a third metal connection structure connected to the second power rail in the third source structure.

[0077] In some possible embodiments, after S110 , the method further includes: removing the third isolation layer, and forming a fourth metal connection structure connected to the second power rail in the fourth source structure.

[0078] S111 , forming a second metal interconnection layer on the fourth semiconductor structure and the fifth semiconductor structure.

[0079] It is understandable that based on circuit design requirements, a second metal interconnection layer is formed on the fourth semiconductor structure and the fifth semiconductor structure using a standard process.

[0080] The first stacked transistor and the second stacked transistor are symmetrically arranged on both sides of the dielectric wall fork plate along the first direction, the first stacked transistor includes a second semiconductor and a fourth semiconductor self-aligned in the first direction, and the second stacked transistor includes a third semiconductor and a fifth semiconductor self-aligned in the first direction.

[0081] It is understood that after forming a pair of active structures, the front transistor can be prepared first and then the back transistor according to standard steps. The front transistor includes the second semiconductor and the third semiconductor, and the back transistor includes the fourth semiconductor and the fifth semiconductor.

[0082] In some embodiments, when the stacked forkplate transistor is a nanosheet field-effect transistor, the first part of the active structure and the second part of the active structure are columnar structures; the columnar structure is a stack formed by alternating deposition of silicon layers and silicon germanium layers; in the process of preparing the active structure, the nanosheet structure can be formed by selectively etching the silicon germanium layer in the above-mentioned stack.

[0083] In some other embodiments, when the stacked forkplate transistor is a fin field effect transistor, the first portion of the active structure and the second portion of the active structure are fin-shaped structures, wherein the number of fin-shaped structures is not specifically limited in the embodiments of the present application.

[0084] In yet other embodiments, when the stacked forkplate transistor is a planar transistor, the first portion of the active structure and the second portion of the active structure are bulk structures.

[0085] In the embodiment of the present application, the insulating material forming the shallow trench isolation structure can be any one of the following: silicon nitride (such as SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc.

[0086] In some possible embodiments, the above-mentioned S107 may include: forming a second semiconductor and a third semiconductor based on the first portion of the active structure; bonding the carrier wafer to the first surface of the second semiconductor and the third semiconductor away from the second portion of the active structure; flipping the wafer and removing a portion of the substrate until the second surface of the shallow trench isolation structure away from the first portion of the active structure is exposed; removing a portion of the shallow trench isolation structure that wraps the back active structure to expose the back active structure; and forming a fourth semiconductor and a fifth semiconductor based on the second portion of the active structure.

[0087] In some embodiments, before bonding the carrier wafer, an insulating material may be deposited on the surfaces of the second semiconductor and the third semiconductor to form an insulating layer, which is used to electrically isolate the second semiconductor, the third semiconductor, and the carrier wafer.

[0088] In some embodiments, during the process of removing the shallow trench isolation structure wrapping the back active structure, the remaining shallow trench isolation structure is not completely removed, but a certain thickness of shallow trench isolation structure is retained as a shallow trench isolation layer for isolating the front transistor and the back transistor.

[0089] In some possible embodiments, the formation of the second semiconductor and the third semiconductor based on the first part of the active structure may include: based on the first part of the active structure, sequentially forming the front spacer, the front source-drain structure and the front interlayer dielectric layer of the second semiconductor and the third semiconductor; removing the front pseudo-gate structure to expose the front gate region of the second semiconductor and the third semiconductor; depositing an isolation material in the first part of the front gate region to form a first dielectric wall fork plate; the first part corresponds to the first dielectric wall structure; depositing metal material in other areas of the front gate region except the first part to form the front gate structure of the second semiconductor and the third semiconductor, and the front gate structure is symmetrically arranged on both sides of the first dielectric wall fork plate; performing a back-end process on the front interlayer dielectric layer to form a first metal interconnection layer.

[0090] In some embodiments, the step of forming the front sidewall spacer may include: depositing an insulating material on the sidewall of the front dummy gate structure to form the front sidewall spacer.

[0091] In some embodiments, the steps of forming the front source-drain structure and the front interlayer dielectric layer may include: removing the first portion of the active structure by etching to provide source-drain grooves for the second semiconductor and the third semiconductor; using the front spacer as a mask, forming a strained material such as silicon germanium or silicon carbide in the source-drain grooves of the second semiconductor and the third semiconductor by selective epitaxial growth to fill the source-drain grooves of the second semiconductor and the third semiconductor; and then forming the front source-drain structure on the strained material by a heavy doping process; and then depositing an insulating material (such as silicon dioxide (SiO2)) on the first portion of the active structure and the first source structure, the first drain structure, the second source structure, and the second drain structure to form a front interlayer dielectric layer. The front interlayer dielectric layer may cover the first portion of the active structure and the first source structure, the first drain structure, the second source structure, and the second drain structure.

[0092] It should be noted that since the first semiconductor is a fork-plate transistor, when forming the front source-drain structure, the strained material can be controlled to grow separately on both sides of the first dielectric wall structure. The finally formed front source-drain structure is two parts symmetrically arranged on both sides of the first dielectric wall structure, one part is used as the source-drain structure in the second semiconductor, and the other part is used as the source-drain structure in the third semiconductor.

[0093] In some embodiments, the steps of forming the front gate structure may include: removing the front dummy gate structure to provide a front gate region for subsequent formation of the front gate structure; then, coating photoresist on the first dielectric wall structure and in the front gate region; developing the photoresist to form a photolithographic pattern aligned with the first dielectric wall structure; using the photoresist as a mask, depositing an isolation material on the dielectric fork plate structure to form a first isolation layer; then, removing the photoresist and depositing a metal material in the front gate region to form the front gate structure. The front gate structure is symmetrically disposed on both sides of the first dielectric wall fork plate.

[0094] In the embodiment of the present application, the metal materials of the front gate structure and the back gate structure may be the same or different; the metal materials used in the front gate structure and the back gate structure may include but are not limited to: tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and the materials of the front gate structure and the back gate structure can be selected according to actual conditions and are not limited to the metal materials listed above.

[0095] In some embodiments, a first metal interconnection layer is formed on the second semiconductor structure and the third semiconductor structure based on the first drain structure and the second drain structure.

[0096] In some embodiments, a first metal interconnection layer is formed on the second semiconductor structure and the third semiconductor structure based on the first drain structure, the second drain structure, and the second source structure.

[0097] In one possible embodiment, the formation of the fourth semiconductor and the fifth semiconductor of the first back transistor based on the second part of the active structure may include: depositing a third semiconductor material on the second part of the active structure to form a back dummy gate structure of the fourth semiconductor and the fifth semiconductor; based on the second part of the active structure, sequentially forming the back spacer, back source-drain structure and back interlayer dielectric layer of the fourth semiconductor and the fifth semiconductor; removing the back dummy gate structure to expose the back gate region of the fourth semiconductor and the fifth semiconductor; depositing an isolation material in the second part of the back gate region to form a second isolation structure; the second part corresponds to the second dielectric wall structure; depositing a metal material in other areas of the back gate region except the second part to form a back gate structure of the fourth semiconductor and the fifth semiconductor, and the back gate structures are symmetrically arranged on both sides of the second isolation structure; performing a back-end process on the back interlayer dielectric layer to form a second metal interconnection layer.

[0098] It should be noted that the second isolation structure is located on the second dielectric wall structure, and its horizontal height is consistent with the height of the back gate structure. The gate structures of the fourth and fifth semiconductors constitute the back gate structure, and the second isolation structure is used to isolate the gate structures of the fourth and fifth semiconductors.

[0099] In an embodiment of the present application, the third semiconductor material for preparing the front dummy gate structure and the back dummy gate structure may include but is not limited to: polycrystalline silicon (poly Si) or amorphous silicon, etc. The above third semiconductor material can be selected according to actual conditions and is not limited to the materials listed above.

[0100] In some embodiments, the step of forming the back sidewall spacer may include: depositing an insulating material on the sidewall of the back sidewall dummy gate structure to form the back sidewall spacer.

[0101] In the embodiment of the present application, the insulating material used for the back spacer and the front spacer can be the same material or different materials, and the embodiment of the present application does not specifically limit this.

[0102] In some embodiments, the steps of forming the aforementioned back-side source / drain structure and back-side interlayer dielectric layer may include: removing the second portion of the active structure by etching to provide source / drain grooves for the fourth semiconductor and the fifth semiconductor; using the back-side spacers as a mask, forming a strained material such as silicon germanium or silicon carbide in the source / drain grooves of the fourth semiconductor and the fifth semiconductor by selective epitaxial growth to fill the source / drain grooves of the fourth semiconductor and the fifth semiconductor; and then forming the back-side source / drain structure on the strained material by a heavy doping process; and then depositing an insulating material (such as silicon dioxide (SiO2)) on the second portion of the active structure and the third source structure, the third drain structure, the fourth source structure, and the fourth drain structure to form a back-side interlayer dielectric layer. The back-side interlayer dielectric layer may cover the second portion of the back-side active structure and the third source structure, the third drain structure, the fourth source structure, and the fourth drain structure.

[0103] It should be noted that since the first semiconductor is a fork-plate transistor, when forming the back source-drain structure, the strained material can be controlled to grow separately on both sides of the second dielectric wall structure. The ultimately formed back source-drain structure is composed of two parts symmetrically arranged on both sides of the second dielectric wall structure, one part serving as the source-drain structure in the fourth semiconductor, and the other part serving as the source-drain structure in the fifth semiconductor.

[0104] In some embodiments, the steps of forming the back gate structure may include: removing the back dummy gate structure to provide a back gate region for subsequent formation of the back gate structure; then, coating a photoresist on the second dielectric wall structure and in the back gate region; developing the photoresist to form a photolithographic pattern aligned with the second dielectric wall structure; using the photoresist as a mask, depositing an isolation material on the dielectric fork plate structure to form a second isolation layer; then, removing the photoresist and depositing a metal material in the back gate region to form the back gate structure. The back gate structures are symmetrically arranged on both sides of the second isolation structure.

[0105] In some embodiments, a second metal interconnection layer is formed on the fourth semiconductor structure and the fifth semiconductor structure based on the third drain structure and the fourth drain structure.

[0106] In some embodiments, a second metal interconnection layer is formed on the fourth semiconductor structure and the fifth semiconductor structure based on the third drain structure, the fourth drain structure, and the fourth source structure.

[0107] Below, the stacked fork plate transistor provided in the embodiment of the present application is described by taking the first semiconductor as a nanosheet field effect transistor as an example. Figure 2 This is a schematic diagram of a structure of stacked fork-plate transistors in an embodiment of the present application. Figure 2 (a) is the design layout of the stacked forkplate transistor. It should be noted that, for ease of understanding, the design layout only shows the nanosheet structure, gate structure, and source-drain structure; (b) is a cross-sectional view of the stacked forkplate transistor along the cross-sectional direction of the gate structure (i.e., AA' direction); (c) is a cross-sectional view of the stacked forkplate transistor along the cross-sectional direction of the source-drain structure (i.e., BB' direction); (d) is a cross-sectional view of the stacked forkplate transistor along the cross-sectional direction of the nanosheet structure (i.e., CC' direction).

[0108] See also Figure 2 As shown, the stacked forkplate transistor 10 includes a second semiconductor structure 31 , a third semiconductor structure 41 , a fourth semiconductor structure 51 , a fifth semiconductor structure 61 , a first power rail 271 , a first dielectric wall structure 281 , a first dielectric wall forkplate 291 , a second dielectric wall structure 282 and a second dielectric wall forkplate 292 .

[0109] See also Figure 2 As shown, in the AA' direction and the BB' direction, the first dielectric wall structure 281 is located in the middle of the front nanosheet structure of the front transistor, that is, the front nanosheet structure is symmetrically arranged on both sides of the first dielectric wall structure 281; similarly, the second dielectric wall structure 282 is located in the middle of the back nanosheet structure of the back transistor, that is, the back nanosheet structure is symmetrically arranged on both sides of the second dielectric wall structure 282.

[0110] The second semiconductor structure 31 includes a first gate structure 311, a first source structure 312, and a first drain structure 313; the third semiconductor structure 41 includes a second gate structure 411, a second source structure 412, and a second drain structure 413; the first gate structure 311 and the second gate structure 411 are isolated from each other by a first dielectric wall fork plate 291; the fourth semiconductor structure 51 includes a third gate structure 511, a third source structure 512, and a third drain structure 513; the fifth semiconductor structure 61 includes a fourth gate structure 611, a fourth source structure 612, and a fourth drain structure 613; the third gate structure 511 and the fourth gate structure 611 are isolated from each other by a second dielectric wall fork plate 292; the first dielectric wall fork plate 291 is located on the first dielectric wall structure 281, and the second dielectric wall fork plate 292 is located on the second dielectric wall structure 282; and the first power rail 271 is located between the second semiconductor structure 31 and the third semiconductor structure 41.

[0111] In some possible embodiments, the stacked fork transistor may further include at least one of the following: the second semiconductor structure 31 further includes a first metal connection structure 712, and the first metal connection structure 712 is connected to the first source structure 312 and the first power rail 271; the third semiconductor structure 41 further includes a second metal connection structure 713, and the above-mentioned second metal connection structure 713 is connected to the second source structure 412 and the first power rail 271.

[0112] In some possible implementations, the stacked forkplate transistor may further include an intermediate isolation layer. The intermediate isolation layer includes a first sacrificial layer 231, a third isolation layer 232, and may also include a second sacrificial layer 233. The intermediate isolation layer is located between the front nanosheet structure and the back nanosheet structure and is used to isolate the front nanosheet structure from the back nanosheet structure.

[0113] In some possible embodiments, the stacked fork plate transistor may further include: a first dielectric wall fork plate 291; the first dielectric wall fork plate 291 is arranged on the first dielectric wall structure 281, and the first gate structure 311 and the second gate structure 411 of the front transistor are symmetrically arranged on both sides of the first dielectric wall fork plate 291; a second dielectric wall fork plate 292; the second dielectric wall fork plate 292 is arranged on the first dielectric wall structure 281, and the third gate structure 511 and the fourth gate structure 611 of the back transistor are symmetrically arranged on both sides of the second dielectric wall fork plate 292.

[0114] In combination with the above preparation method, Figure 2 The fabrication process of the stacked forkplate transistor 10 is described below. Figure 2 The stacked fork plate transistor 10 shown can be Figures 3 to 29 The process shown is prepared Figures 3 to 29Schematic diagram of a preparation process of stacked fork-plate transistors in an embodiment of the present application.

[0115] In one example, taking the stacked forkplate transistor 10 as a nanosheet field effect transistor, the manufacturing process of the stacked forkplate transistor 10 may include the following steps:

[0116] It should be noted that different steps (ie, different processes) in the following examples may use AA' direction, BB' direction, CC' direction, or different combinations of the above three directions to illustrate the fabrication process of the stacked fork transistor 10 according to structural changes.

[0117] The first step is to deposit semiconductor materials in an overlapping manner on the substrate 24 to form an initial stacked structure.

[0118] In some embodiments, the material of substrate 24 includes a semiconductor material, such as a single-element semiconductor material (e.g., silicon (Si) or germanium (Ge)), a III-V compound semiconductor material (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP)), a II-VI compound semiconductor material (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe)), an organic semiconductor material, or other semiconductor materials known in the art. This embodiment will be described using a silicon substrate as an example.

[0119] See also Figure 3 As shown, the initial stacked structure includes a second initial stacked structure 22, an intermediate sacrificial layer 23, and a first initial stacked structure 21 stacked sequentially in a first direction. The first initial stacked structure 21 includes alternating first isolation layers 21A and first semiconductor layers 21B. The second initial stacked structure 22 includes alternating second isolation layers 22A and second semiconductor layers 22B. The intermediate layer 23 includes a second sacrificial layer 233, a third isolation layer 232, and a second sacrificial layer 233. The first direction is the epitaxial growth direction, perpendicular to the substrate 24.

[0120] It should be noted that the material of the third isolation layer 232 includes sacrificial layer materials such as silicon oxide, polysilicon, photoresist, and highly doped silicon germanium.

[0121] Step 2: forming a patterned mask layer 81 on the initial stacked structure.

[0122] See also Figure 4 As shown, in Figure 3 On the basis of the structure shown, a patterned mask layer 81 is formed by depositing a dielectric material and performing photolithography or etching on the deposited dielectric material.

[0123] Step 3: Using the patterned mask layer 81 as an etching mask, the initial stacked structure is etched down to the substrate 24 to form a pair of active structures 20 .

[0124] See also Figure 5 As shown, in Figure 4 Based on the structure shown, the initial stacked structure is etched using the patterned mask layer 81 as an etching mask until the substrate 24 is exposed, thereby forming a first trench. Here, the number of first trenches can be one or more, and the first trenches can divide the initial stacked structure into at least a pair of active structures 20. The active structure 20 includes a first portion 201 and a second portion 202, with an unetched portion of the intermediate sacrificial layer 23 between the first portion 201 and the second portion 202.

[0125] In some embodiments, the etching process for the initial stack structure includes at least one of dry etching and wet etching.

[0126] Step 4: Deposit a sacrificial material on the substrate 24 and perform chemical-mechanical planarization (CMP) until the patterned mask layer 81 is exposed to form an initial shallow trench isolation (STI) layer 30A.

[0127] See also Figure 6 As shown, in Figure 5 On the basis of the structure shown, a sacrificial material is filled into the first trench, and a planarization process is performed until the patterned mask layer 81 is exposed, thereby forming an initial STI 30A.

[0128] Step 5: Etch back the initial STI 30A to remove the patterned mask layer 81 (see Figure 7 shown).

[0129] Step 6: Etch the initial STI 30A until the third isolation layer 232 to expose the first portion 201 of the active structure 20 .

[0130] See also Figure 8 As shown, in Figure 7 Based on the structure shown, the initial STI 30A is etched back until the sidewalls of the remaining third isolation layer 232 are exposed to form the STI 30. In some embodiments, the etching back of the initial STI 30A may stop at the bottom surface of the first sacrificial layer 231 or between the bottom and top surfaces of the third isolation layer 232. When the etching stops between the bottom and top surfaces of the third isolation layer 232, a portion of the sidewalls of the third isolation layer 232 is also exposed.

[0131] Step 7: depositing oxide on the STI 30 and the first portion 211 to form a first insulating layer 251 .

[0132] See also Figure 9 As shown, in Figure 8 On the basis of the structure shown, oxide is deposited to form a first insulating layer 251 covering the STI 30 and the first portion 201 .

[0133] Step 8: depositing a metal material on the first insulating layer 251 and performing CMP on the first insulating layer 251 to form a first metal structure 261 .

[0134] See also Figure 10 As shown, in Figure 9 On the basis of the structure shown, a metal material is deposited and CMP is performed to the first insulating layer 25 , thereby forming a first metal structure 261 . Here, the first metal structure 261 provides a basis for forming a first power rail 271 .

[0135] Step 9: Etch the first metal structure 261 to a predetermined height to form a second metal structure 262 .

[0136] See also Figure 11 As shown, in Figure 10 Based on the structure shown, when etching the first metal structure 261, by controlling the etching rate and / or time, the remaining first metal structure 261 can be stopped at a certain height, i.e., the height of the first power rail 271. For example, the remaining first metal structure 261 stops between the top surface and the bottom surface of the first sacrificial layer 231, i.e., the surface of the first power rail 271 relatively away from the STI 30 is located between the third isolation layer 232 and the lowermost first semiconductor layer 21B, so that the subsequent first power rail is located between the new first sacrificial layer 231a and the first portion 201.

[0137] Step 10: deposit a layer of silicon oxide on the second metal structure 262 by an atomic layer deposition process to form a second insulating layer 252 .

[0138] See also Figure 12 As shown, in Figure 11 On the basis of the structure shown, a layer of silicon oxide is deposited by an atomic layer deposition process to form a second insulating layer 252 covering the first power rail 271 and the first portion 2012 .

[0139] Step 11: forming a dielectric layer 280 on the second insulating layer 252 .

[0140] See also Figure 13 As shown, in Figure 12 On the basis of the structure shown, a dielectric wall material is filled to form a dielectric layer 280, and the surface of the dielectric layer 280 is higher than the surface of the first portion 201. Here, the dielectric layer 280 provides a foundation for the subsequent formation of a first dielectric wall structure 281.

[0141] Step 12: Etch the dielectric layer 280 and retain the portion between the pair of active structures 20 to form a first dielectric wall 281 .

[0142] See also Figure 14 As shown, in Figure 13 Based on the structure shown, the dielectric layer 280 is etched back by strictly controlling the isotropic etching rate and time to form a first dielectric wall 281. In some embodiments, the surface of the first dielectric wall 281 is located between the bottom surface and the top surface of the uppermost second isolation layer 22A.

[0143] Step 13: Etch the second insulating layer 252 to expose the first portion 201 and a portion of the second metal structure 262 outside the pair of active structures 20 .

[0144] See also Figure 15 As shown, in Figure 14 Based on the structure shown, the second insulating layer 252 covering the sidewalls and top surface of the first portion 201 is etched until it is substantially flush with the surface of the first dielectric wall 281. At this point, the second insulating layer 252 remains between the first dielectric wall 281 and the first portion 201 of the pair of active structures 20. While etching the second insulating layer 252 covering the sidewalls and top surface of the first portion 201, the second insulating layer 252 covering the portion of the second metal structure 262 outside the pair of active structures 20 can also be etched.

[0145] Step 14: Etch the second metal structure 262 outside the pair of active structures 20 to form a first power rail 271. Here, the first power rail 271 is located between the first portion 201 of the pair of active structures 20, and above the first power rail 271 is a first dielectric wall structure 281 (see FIG. Figure 16 shown).

[0146] Step 15: forming an interlayer dielectric (ILD) layer 82 at the position where the second metal structure 262 is etched, so that the ILD layer 82 replaces the portion of the second metal structure 262 etched in step 13.

[0147] See also Figure 17 As shown, in Figure 16 Based on the structure shown, an ILD material is deposited on the first insulating layer 251, the active structure 20 and the first dielectric wall 281 outside the pair of active structures 20, and then CMP is performed so that the ILD layer 82 replaces the etched portion of the second metal structure 262 on the outer side of the active structure 20.

[0148] Step 16: Deposit a layer of oxide to form a third insulating layer 253.

[0149] See also Figure 18 As shown, in Figure 17 On the basis of the structure shown, a layer of oxide is deposited by an ALD process to form a third insulating layer 253 covering the ILD layer 82 , the first portion 201 and the first dielectric wall 281 .

[0150] Step 17: Deposit polysilicon material on the third insulating layer 253 to form a dummy gate structure 83 (see Figure 19 shown).

[0151] It should be noted that Figure 19 The cross-sectional view along the dotted line CC' is obtained by cutting along the preset formation position of the channel, and the dotted line CC' is perpendicular to the dotted line AA'. Figure 20 The cross-sectional view along the dotted line BB' is obtained by cutting along the preset formation position of the source / drain. Figure 20 There is no dummy gate structure 83 formed above the structure corresponding to the dotted line BB', and the direction of the dotted line BB' is parallel to the direction of the dotted line AA'. The dotted line BB' direction and the dotted line CC' direction will not be described in detail below.

[0152] Step 18: Remove the first isolation layer 21A, the second isolation layer 22A and the first sacrificial layer 231 in the active structure 20, and fill the position where the first sacrificial layer 231 is removed with isolation material to form a new first sacrificial layer 231a (see Figure 20 shown).

[0153] Step 19: Based on the first portion 201 , epitaxially grow a first source structure 312 and a first drain structure 313 .

[0154] See also Figure 21 As shown, in Figure 20 Based on the structure shown, the isolation material on the surface is etched until the first portion 201 of the active structure 20 is exposed, and the first portion 201 is etched to form at least two grooves spaced apart in a direction D perpendicular to and pointing to the substrate 24. At least two grooves extend downward to the surface of the new first sacrificial layer 231a or into the new first sacrificial layer 231a. Two adjacent grooves expose opposite ends of the new first sacrificial layer 231a along the direction D. Epitaxial growth is performed on the exposed opposite ends to form the following: Figure 23 The first source structure 312 and the first drain structure 313 are shown. The second semiconductor layer 22B located between the first source structure 312 and the first drain structure 313 forms a channel of the front transistor.

[0155] Step 20: Remove the dummy gate structure 83 to form the first dielectric wall fork 291 and the first gate structure 311 .

[0156] See also Figure 22 As shown, in Figure 21 Based on the structure shown, a thin film deposition process and a chemical mechanical polishing process can be used to form a second interlayer dielectric layer 822, and the material of the second interlayer dielectric layer 822 includes silicon oxide; part of the dummy gate structure 83 and the retained second isolation layer 22A are removed, and metal material is filled in the position where the dummy gate structure 83 and the retained second isolation layer 22A are removed, and a flattening treatment is performed to form an initial gate; the initial gate is etched to form a gate isolation trench, and the gate isolation trench is filled with gate isolation material to form a first dielectric wall fork plate 291. The first dielectric wall fork plate 291 separates the initial gate into a first gate structure 311 and a second gate structure 411. At this time, the gate structures of a pair of front transistors can be prepared at the same time, and physical isolation is achieved through the first dielectric wall fork plate 291.

[0157] In some embodiments, the first gate structure is physically isolated from the first source structure 312 and the first drain structure 313 by a spacer layer a to avoid direct contact and leakage.

[0158] It should be noted that before filling the metal material at the locations where the dummy gate structure 83 and the second isolation layer 22A are removed, one or more gate dielectric layers may be formed using an atomic layer deposition process. The gate dielectric layer may be made of a dielectric material. In this example, a gate dielectric layer made of a high-k dielectric material is used as an example.

[0159] At this point, the preparation of a pair of front-side transistors is completed.

[0160] Step 21: forming an interlayer dielectric layer 71 on the source structure, and etching the interlayer dielectric layer 71 to form an initial first groove 711A.

[0161] See also Figure 23 As shown, in Figure 22 Based on the structure shown, an ILD material is deposited on the source structure to form an interlayer dielectric layer 71. Based on the location of the power connection in the layout, the interlayer dielectric layer 71 is etched until it stops at the second dielectric layer 82, forming a relatively wide initial first trench 711A. In one example, the power connection is located on the side of the first source structure 312.

[0162] In some embodiments, the interlayer dielectric layer 71 covers the second dielectric layer 82 and the first source structure 312. In some embodiments, based on different types of transistors, the second source structure 412 or the second drain structure 413 may be located on the same side of the channel as the first source structure 312. In this example, the first source structure 312 and the second source structure 412 are located on the same side of the channel.

[0163] Step 22: Etch the second dielectric layer 82 and the remaining third isolation layer 232 to form a first trench 711 .

[0164] See also Figure 24 As shown, in Figure 23 Based on the structure shown, the initial first groove 711A is further etched to remove the second dielectric layer 82, the retained third isolation layer 232, and the insulating layer around the first power rail 27 to expose the first power rail 27. In this way, a conductive channel (i.e., the first groove 711) is formed between the first source structure 312 and the first power rail 27.

[0165] Step 23: Fill the first trench 711 with metal material to form a first metal connection structure 712 connecting the first source structure 312 and the first power rail 27. Then, through the back-end process, a first metal interconnection layer 715 is formed to connect the second source structure 412 (see Figure 25 shown).

[0166] At this point, the first source structure 312 is connected to the first power rail 27 at the side of the first source structure 312 , and the first source structure 312 connected to the first power rail 27 does not need to be led out again.

[0167] In some embodiments, the first power rail 27 is connected to the first source structure 312 through the first metal connection structure 712 and to the second source structure 412 through the second metal connection structure 713. Figure 26 The first power rail 27 is connected to the first source structure 312 through the first metal connection structure 712 or connected to the second source structure 412 through the second metal connection structure 713, as shown in FIG. Figure 26 Of course, in other embodiments, as shown in (b) or (c). Figure 26 As shown in (d), the first metal interconnection structure 712 and the second metal interconnection structure 713 may be omitted, and the first power rail 27 is connected to other logic circuits, which is not specifically limited in the embodiment of the present disclosure.

[0168] Step 24: Bond the semiconductor structure to a wafer carrier and flip the wafer (see Figure 27 shown).

[0169] Step 25: Remove the substrate 24 and the STI 30 until the second portion 202 of the pair of active structures 20 is exposed (see Figure 28 shown).

[0170] Step 26: Following the steps 7 to 23 above, use the same process to prepare the back-side transistors, the second power rail 272, and the second metal interconnect layer 714. Further, a third metal interconnect structure 716 and / or a fourth metal interconnect structure 717 may be prepared (see Figure 29 shown).

[0171] At this point, the stacked fork transistor 10 in which the first semiconductor is a nanosheet field effect transistor is completed.

[0172] In an embodiment of the present application, when the front transistor and the back transistor are planar transistors or fin-type field-effect transistors, except that the front active structure and the back active structure are different from the front active structure and the back active structure of the stacked fork-plate transistor composed of the above-mentioned nanosheet field-effect transistors, the other structures are the same as the stacked fork-plate transistor composed of the above-mentioned nanosheet field-effect transistors; accordingly, except that the preparation process of the front active structure and the back active structure is different, the preparation process of the remaining structures is the same as the preparation process shown in the above-mentioned example, and the embodiment of the present application will not go into details about this.

[0173] In the embodiment of the present application, the front active structure is symmetrically arranged on both sides of the dielectric fork-plate structure, the back active structure is symmetrically arranged on both sides of the dielectric fork-plate structure, and the front transistor includes a first front transistor and a second front transistor symmetrically arranged on both sides of the dielectric fork-plate structure, and the back transistor includes a first back transistor and a second back transistor symmetrically arranged on both sides of the dielectric fork-plate structure. This can reduce the spacing between the symmetrically placed devices on both sides of the dielectric fork-plate structure and improve the integration density.

[0174] Furthermore, the stacked forkplate transistor realizes the combination of stacked transistors and forkplate transistors, further improving the integration density while achieving self-alignment of the front transistors and the back transistors.

[0175] The present application provides a semiconductor device, comprising: the specific definition of the power rail of the stacked fork plate transistor in the above embodiment can be found in the above embodiment. Figure 2 The stacked fork plate transistors shown are not described in detail here.

[0176] The present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the stacked fork plate transistor. The specific definition of the stacked fork plate transistor can be found in the above Figure 2 The stacked fork plate transistors shown are not described in detail here.

[0177] In the description of this application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine different embodiments or examples described in this application and features of different embodiments or examples without contradiction.

[0178] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for preparing a stacked fork-plate transistor, characterized in that: include: A first semiconductor structure is formed on a substrate, the first semiconductor structure comprising: a pair of active structures and a shallow trench isolation layer, wherein the active structure comprises a first portion and a second portion, the first portion being farther away from the substrate than the second portion, and at least a first sacrificial layer and an isolation layer stacked in sequence are disposed between the first portion and the second portion in a direction perpendicular to the substrate; the shallow trench isolation layer wraps around the first portion and is flush with the first sacrificial layer; forming a first power rail on the first semiconductor structure, the first power rail being located between first portions of the pair of active structures; forming a first dielectric wall structure on the first power rail; Based on the first portion of the pair of active structures, a second semiconductor structure and a third semiconductor structure are formed, wherein the second semiconductor structure includes a first gate structure, a first source structure, and a first drain structure, and the third semiconductor structure includes a second gate structure, a second source structure, and a second drain structure; the first gate structure and the second gate structure are isolated by a first dielectric wall fork on the first dielectric wall structure; removing the isolation layer and forming a first metal connection structure connected to the first power rail in the first source structure; forming a first metal interconnection layer on the second semiconductor structure and the third semiconductor structure; flipping the second semiconductor structure and the third semiconductor structure; removing a portion of the substrate and the shallow trench isolation layer until a second portion of the pair of active structures is exposed; forming a second dielectric wall structure between second portions of the pair of active structures; Based on the second portion of the pair of active structures, a fourth semiconductor structure and a fifth semiconductor structure are formed, wherein the fourth semiconductor structure includes a third gate structure, a third source structure, and a third drain structure, and the fifth semiconductor structure includes a fourth gate structure, a fourth source structure, and a fourth drain structure; the third gate structure and the fourth gate structure are isolated by a second dielectric wall cross plate on the second dielectric wall structure; A second metal interconnection layer is formed on the fourth semiconductor structure and the fifth semiconductor structure.

2. The method according to claim 1, characterized in that After removing the isolation layer, the method further includes: A second metal contact structure connected to the first power rail is formed in the second source structure.

3. The method according to claim 1, characterized in that A second sacrificial layer is further provided between the first portion and the second portion along a direction perpendicular to the substrate, and the second sacrificial layer is closer to the second portion than the first sacrificial layer; After removing a portion of the substrate and the shallow trench isolation layer until the second portion of the pair of active structures is exposed, the method further includes: forming a second power rail on another portion of the shallow trench isolation layer, the second power rail being located between the second portions of the pair of active structures; After forming a fourth semiconductor structure and a fifth semiconductor structure based on the second portion of the pair of active structures, the method further includes: The second sacrificial layer is removed, and a third metal connection structure connected to the second power rail is formed in the third source structure.

4. The method according to claim 3, characterized in that After removing the second sacrificial layer, the method further includes: A fourth metal contact structure connected to the second power rail is formed in the fourth source structure.

5. The method according to claim 1, wherein The forming of a first power rail on the first semiconductor structure comprises: depositing oxide on the first semiconductor structure to form a first insulating layer; depositing a metal material on the first insulating layer to form a first metal structure; Etching the first metal structure to a predetermined height to form a second metal structure; Etching a region of the second metal structure outside the first portion of the pair of active structures to obtain a third metal structure located between the second portions of the pair of active structures; Oxide is deposited on the third metal structure to form the first power rail.

6. The method according to claim 1, characterized in that The forming of a first metal connection structure connected to the first power rail in the first source structure includes: depositing a semiconductor material on the first source structure to form an interlayer dielectric layer; Etching the interlayer dielectric layer until the first power rail is exposed to form a first groove; A metal material is filled in the first groove to form the first metal connection structure.

7. The method according to claim 1, characterized in that After forming a first dielectric wall structure on the first power rail, the method further includes: The first dielectric wall fork plates are formed on the first dielectric wall structure based on an isolation material.

8. A stacked forkplate transistor, characterized in that The stacked forkplate transistor is prepared by the method according to any one of claims 1 to 7; the stacked forkplate transistor comprises: a second semiconductor structure, a third semiconductor structure, a fourth semiconductor structure, a fifth semiconductor structure, a first power rail, a first dielectric wall structure, a first dielectric wall forkplate, a second dielectric wall structure, and a second dielectric wall forkplate, wherein the first dielectric wall forkplate is located on the first dielectric wall structure, and the second dielectric wall forkplate is located on the second dielectric wall structure; the first power rail is located between the second semiconductor structure and the third semiconductor structure; The second semiconductor structure includes a first gate structure, a first source structure, and a first drain structure; the third semiconductor structure includes a second gate structure, a second source structure, and a second drain structure; the first gate structure and the second gate structure are isolated by the first dielectric wall fork; the fourth semiconductor structure includes a third gate structure, a third source structure, and a third drain structure; the fifth semiconductor structure includes a fourth gate structure, a fourth source structure, and a fourth drain structure; the third gate structure and the fourth gate structure are isolated by the second dielectric wall fork; The stacked forkplate transistor further comprises at least one of the following: The second semiconductor structure further includes a first metal connection structure connected to the first source structure and the first power rail; The third semiconductor structure further includes a second metal contact structure connected to the second source structure and the first power rail.

9. The stacked forkplate transistor according to claim 8, wherein: The stacked forkplate transistor further includes a second power rail located between the fourth semiconductor structure and the fifth semiconductor structure; The stacked forkplate transistor further comprises at least one of the following: The fourth semiconductor structure further includes a third metal connection structure connected to the third source structure and the second power rail; The fifth semiconductor structure further includes a fourth metal connection structure connected to the fourth source structure and the second power rail.

10. An electronic device, characterized in that: include: A circuit board and the stacked forkplate transistor according to claim 8 or 9, wherein the stacked forkplate transistor is arranged on the circuit board.

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