Post-etching processing method for improving copper loss of through hole array region in semiconductor device
By introducing reducing plasma to treat the copper surface in semiconductor devices, the copper loss problem in high-density via array regions was solved, improving electrical performance and reliability, and increasing manufacturing yield.
Patent Information
- Application Number
- CN202511063018.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-11
AI Technical Summary
In semiconductor manufacturing, the copper loss problem in high-density via array regions is difficult to solve effectively in post-etching processes, leading to a decline in electrical performance and reliability. Existing technologies have narrow process windows, which affect manufacturing yield.
Abnormal via areas are identified by automatic surface inspection, the cause of copper loss is analyzed and confirmed, and a reducing plasma treatment is introduced on the copper surface in addition to the conventional post-etching process, including the use of hydrogen and nitrogen plasma, to repair copper surface damage and form a passivation layer to prevent corrosion.
It significantly reduces copper loss defects in high-density via array regions, expands the process window, and improves device reliability and manufacturing yield.
Smart Images
Figure CN120933236A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and more particularly to a post-etch treatment method for metal interconnect structures. More specifically, it relates to a post-etch treatment (PET) method for improving copper loss in high-density via array regions during back-end of line (BEOL) processes. Background Technology
[0002] In modern integrated circuit manufacturing, as device feature sizes continue to shrink and integration density continues to increase, the width of metal interconnects within the chip also decreases accordingly. This leads to a significant increase in current density within the interconnects, making copper (Cu), the mainstream interconnect material, more susceptible to electromigration and chemical corrosion during processing (such as etching), posing a severe challenge to device performance and reliability.
[0003] In BEOL (Block Array of Interconnects) technology, a dual damascene process is typically used to construct multilayer metal interconnect structures. Electrical connections between different metal layers are achieved through vertical via structures. Specifically, in critical areas, such as the Power Management Unit (PMU) area or input / output (I / O) area, to meet the requirements of high current carrying capacity, high-density via array structures are usually designed and fabricated, i.e., multiple vias arranged in parallel within a local area.
[0004] In a typical dual damascene process (e.g., Partial ViaFirst with Metal Hard Mask), forming the via structure usually involves an All-In-One Etch (AIO Etch) step. This step etches the via and the trench pattern above it in a dielectric layer (such as an ultra-low dielectric constant material, ULK), ultimately exposing the underlying copper metal layer (Mx). Following the AIO etching, a post-etching (PET) step is typically performed to remove etching residues or polymers (e.g., CFx-type polymers) formed on the sidewalls and bottom during the etching process. In the prior art, the PET step often employs plasma containing, for example, carbon monoxide (CO) and / or carbon dioxide (CO2).
[0005] However, the inventors discovered that high-density via arrays exhibit different behavior during AIO etching and subsequent processing compared to single via structures. Due to the high pattern density and aspect ratio of the via array region, etching residues and polymers are more likely to accumulate at the bottom of the vias, making them difficult to remove effectively. More seriously, during AIO etching, the exposed copper surface may react with etching gases (such as fluorine-containing gas CF4), forming a damaged surface layer (e.g., possibly containing substances such as CuFxOy). In the subsequent wet stripping step (typically using a solution containing hydrofluoric acid HF to remove residual oxides or etch stop layers), this damaged copper surface or residual polymer may be more susceptible to chemical erosion, leading to corrosion of the copper at the bottom of the vias, forming pits, i.e., copper loss defects.
[0006] Such copper loss defects will be identified as abnormal via images in subsequent wafer defect inspections (e.g., automated surface inspection, ASI inspection). In severe cases, this may lead to unreliable connection between upper and lower metal layers, which will have a serious adverse impact on the electrical performance, long-term reliability and final product yield of the device.
[0007] Although the existing AIO Etch process includes a PET step, the conventional CO / CO2 plasma PET treatment conditions are still insufficient to suppress copper loss in high-density via array regions, resulting in a limited process window.
[0008] Therefore, there is an urgent need to develop an improved post-etching process that can more effectively process high-density via array structures, especially improving the condition of the bottom copper surface, in order to reduce copper loss in subsequent wet stripping processes and improve device reliability and manufacturing yield. Summary of the Invention
[0009] This invention aims to solve at least some of the problems existing in the prior art. As described in the background art, in semiconductor back-end metal interconnect processes, especially when manufacturing high-density via array structures using dual damascene processes, after integrated etching and before the wet stripping step, the copper metal layer at the bottom of the via is prone to corrosion in subsequent processing (especially wet stripping) due to etching residues, polymer accumulation, and damage to the copper surface caused by the etching itself (e.g., the formation of substances such as CuFxOy), resulting in copper loss defects.
[0010] While existing technologies include post-etching processes, typically using CO / CO2 plasma to remove polymers, their effectiveness in suppressing copper loss in high-density via array regions is limited. They also have narrow process windows and are prone to via defects, which in turn affect the electrical performance, reliability, and manufacturing yield of devices.
[0011] Therefore, one object of the present invention is to provide an improved post-etching process that can effectively improve the copper loss problem in high-density via array regions.
[0012] To achieve the above and other related objectives, the present invention provides a post-etching process for improving copper loss in a via array region of a semiconductor device, the semiconductor device comprising a via structure formed by an integrated etching process, the via structure exposing an underlying copper metal layer, comprising:
[0013] Step 1: Perform automatic surface inspection on the wafer that has undergone integrated etching process to identify abnormal via areas;
[0014] Step 2: Analyze the abnormal via region using analytical tools to confirm that the anomaly is caused by copper loss in the copper metal layer at the bottom of the via structure; and
[0015] Step 3: After the integrated etching process and before the subsequent wet stripping process, an enhanced post-etching process is performed on the wafer. The enhanced post-etching process includes treating the surface of the copper metal layer exposed by the via structure with reducing plasma.
[0016] Preferably, in step two, the analytical tool includes at least one of scanning electron microscope, transmission electron microscope, and energy-dispersive X-ray spectroscopy.
[0017] Preferably, in step two, it is confirmed that the copper loss manifests as corrosion, pitting, or discontinuity on the surface of the copper metal layer.
[0018] Preferably, in step two, the analysis further includes using energy-dispersive X-ray spectroscopy to confirm that the abnormal via region is free from contamination by any abnormal impurity elements other than those introduced by the process.
[0019] Preferably, in step three, the reducing plasma is used to passivate the surface of the copper metal layer and / or reduce the copper-containing oxides or copper-containing fluorides formed on the surface of the copper metal layer during the integrated etching process.
[0020] Preferably, in step three, the reducing plasma contains hydrogen gas.
[0021] Preferably, in step three, the plasma further comprises nitrogen gas.
[0022] Preferably, in step three, the N2:H2 gas volume ratio in the plasma is between 1:1 and 3:1, the total gas flow rate is 0-600 sccm, and the radio frequency power ranges from 0-400 W.
[0023] Preferably, in step three, prior to performing the enhanced post-etching process, a first post-etching process using plasma containing carbon monoxide and / or carbon dioxide is first performed to remove residual polymer generated during the integrated etching process.
[0024] Preferably, the method further includes performing automatic surface inspection again after executing step three, and confirming that the number of abnormal vias has decreased compared with the inspection results of step one.
[0025] Preferably, the through-hole structure is a high-density through-hole array structure.
[0026] Preferably, the method is applied to the back-end metal interconnect process of semiconductor devices.
[0027] As described above, the post-etching process method of the present invention for improving copper loss in via array regions of semiconductor devices has the following beneficial effects:
[0028] This invention identifies copper loss issues in the via array region through defect localization analysis. Based on the conventional post-etching process for polymer removal, it introduces or enhances the step of treating the copper surface with reducing plasma, effectively passivating and repairing the exposed copper surface, reducing its corrosion risk in subsequent wet processing, thereby significantly reducing copper loss defects in the high-density via array region, expanding the process window, and improving device reliability and manufacturing yield. Attached Figure Description
[0029] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.
[0030] Figure 2 The diagram shows a schematic representation of the through-hole array region of the present invention.
[0031] Figure 3 The diagram shown illustrates the method of locating frequently occurring defect regions using wafer diagrams and chip stacking diagrams according to the present invention.
[0032] Figure 4 The diagram shown is a schematic representation of the through-hole layout pattern density of the present invention.
[0033] Figure 5 The diagram shows the analysis of abnormal through-hole areas using analysis tools according to the present invention.
[0034] Figure 6 The diagram shown is a schematic representation of the EDS analysis results of this invention.
[0035] Figure 7 The diagram shows the detection results of lot 1 in this invention;
[0036] Figure 8The diagram shows the detection results of lot 2 of the present invention. Detailed Implementation
[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0038] Please see Figure 1 This application provides a method for improving the via array region (e.g., in semiconductor devices) Figure 2 (As shown) A post-etching process for copper loss, wherein the semiconductor device includes a via structure formed by an integrated etching process, the via structure exposing an underlying copper metal layer, comprising the following steps:
[0039] Step 1: Perform Automated Surface Inspection (ASI) on the wafers processed by the integrated etching process to identify abnormal via regions. This step enables early detection of potential process problems, particularly locating defect areas that may be caused by improper post-etching processing. Please refer to [link to relevant documentation]. Figure 3 For example, defect-prone areas (weak areas) can be located using wafer map distribution and die stack diagrams.
[0040] Step 2: Analyze the abnormal via area using analytical tools to confirm that the anomaly is caused by copper loss in the copper metal layer at the bottom of the via structure. This confirmation step forms the basis for subsequent optimization solutions, ensuring the targeted nature of the improvement measures.
[0041] In some embodiments, in step two, the analytical tools include at least one of scanning electron microscopy (SEM), transmission electron microscopy (TEM), and energy-dispersive X-ray spectroscopy (EDS). For example, see [link to relevant documentation]. Figure 5 SEM can be used to observe the surface morphology of abnormal areas, and SEM observation combined with, for example Figure 4 The layout shown identifies anomalies occurring in the via array structure; cross-sectional analysis using TEM allows for more precise observation of the microstructure at the bottom of the vias; and elemental composition is analyzed using EDS.
[0042] In some embodiments, in step two, it is confirmed that copper loss manifests as corrosion, pitting, or discontinuity on the surface of the copper metal layer. For example... Figure 5As shown in the TEM images, obvious corrosion or cavitation is observed in the copper layer at the bottom of the via, which directly affects the electrical performance and reliability of subsequent devices. Therefore, accurate identification of this type of morphology is crucial. By precisely locating the specific manifestations of copper loss, we can better understand the mechanism of defect formation.
[0043] In some embodiments, step two, the analysis further includes using energy-dispersive X-ray spectroscopy to confirm that the anomalous via region is free from contamination by other anomalous impurity elements besides process-introduced elements (such as F and C from etching gases or O from plasma processing). Figure 6 The EDS analysis results confirmed that the defects were mainly due to a decrease in copper content, with no obvious foreign abnormal elements present. This helps to eliminate interference from other potential sources of contamination and focuses the root cause of the problem on the impact of etching and post-processing on the copper itself, thereby ensuring the correctness of the subsequent optimization direction.
[0044] Step 3: After the integrated etching process and before the subsequent wet stripping process, an enhanced post-etching process is performed on the wafer. The enhanced post-etching process includes treating the copper metal layer surface exposed by the via structure with reducing plasma.
[0045] In some embodiments, in step three, prior to performing the enhanced post-etching process, a first post-etching process (i.e., conventional PET) using plasma containing carbon monoxide (CO) and / or carbon dioxide (CO2) is first performed to remove residual polymers (e.g., CFx polymers) generated during the integrated etching process. This helps to remove most etching byproducts initially, creating better conditions for subsequent enhancement treatments on the copper surface and preventing residual polymers from interfering with subsequent reduction passivation.
[0046] In some embodiments, in step three, following the first post-etching process described above, a reducing plasma treatment is applied to the surface of the copper metal layer exposed by the via structure. This is a key improvement of the method, aiming to address the problem that the copper surface still suffers damage or is easily corroded after conventional PET treatment.
[0047] In some embodiments, in step three, reducing plasma is used to passivate the surface of the copper metal layer and / or reduce copper-containing oxides or copper-containing fluorides (such as CuFxOy) formed on the surface of the copper metal layer during the integrated etching process. This treatment can effectively repair the damage to the copper surface caused by etching, such as reducing the damaged copper compounds to metallic copper, and forming a more stable and corrosion-resistant passivation layer on the copper surface, thereby significantly improving the copper surface's tolerance to subsequent wet treatments (such as wet stripping with HF), effectively expanding the wet stripping process window, and reducing copper loss.
[0048] In some embodiments, in step three, the reducing plasma contains hydrogen (H2). Hydrogen has a strong reducing ability and can effectively react with oxides or fluorides (such as CuFxOy) on the copper surface, reducing them and restoring the pure surface state of the copper or forming a hydrogen passivation layer, thereby improving the surface state of the copper.
[0049] In some embodiments, in step three, in addition to hydrogen, the plasma further contains nitrogen (N2). In this case, nitrogen can be used as a carrier gas or dilution gas to adjust the concentration and reaction rate of the hydrogen plasma for better process control. Furthermore, nitrogen may also participate in the treatment of the copper surface under plasma conditions, for example, by assisting in the formation of a passivation layer through slight nitriding to further enhance the corrosion resistance of the copper surface, or by stabilizing the plasma discharge.
[0050] In some embodiments, in step three, the specific process parameters involved in the enhanced post-etching process (e.g., but not limited to: gas flow rate, reaction chamber pressure, plasma power, processing time, wafer temperature) can be optimized and selected through conventional experimental design based on factors such as the specific plasma etching equipment model used, reaction chamber conditions, and the specific dimensions (e.g., aspect ratio, density) of the chip technology node and via structure being processed, in order to achieve the best copper loss improvement effect.
[0051] For example, in step three, the gas volume ratio of N2:H2 in the plasma is between 1:1 and 3:1, the total gas flow rate is 0-600 sccm, and the radio frequency power ranges from 0-400 W.
[0052] In some embodiments, the method further includes performing automated surface inspection (ASI) again after step three to confirm that the number of abnormal vias has decreased compared to the results of step one. Figure 7 and Figure 8 As shown in the effect verification section, the effectiveness of the method of the present invention can be intuitively evaluated by comparing the ASI detection results before and after optimization (e.g., comparing the number of defects in BSL and PET Splits). The significant reduction in the number of abnormal vias directly proves that the enhanced post-etching process successfully suppressed the generation of copper loss defects, which helps to improve the yield of the entire wafer manufacturing process and ultimately improve the reliability and performance of chip products.
[0053] In some embodiments, the via structure is a high-density via array structure. This method is particularly suitable for improving the more severe copper loss problem caused by factors such as high pattern density, easy accumulation of etching byproducts, and greater difficulty in controlling plasma processing uniformity in such structures. For example, dense via arrays are widely used in PMU power regions or I / O regions.
[0054] In some embodiments, the method is applied to back-end metal interconnect (BEOL) processes for semiconductor devices, particularly to dual damascene processes. This allows the method to be well-compatible with and integrated into existing mainstream copper interconnect manufacturing processes, such as inserting or replacing / enhancing the existing PET step after AIO Etch and before the Wet Strip step, demonstrating good process applicability and industrial application value.
[0055] In summary, the embodiments of the present invention confirm the copper loss problem in the via array region through defect localization analysis, and introduce or enhance the step of treating the copper surface with reducing plasma on the basis of conventional post-etching process to remove polymer, effectively passivating and repairing the exposed copper surface, reducing its corrosion risk in subsequent wet processing, thereby significantly reducing copper loss defects in the high-density via array region, expanding the process window, and improving device reliability and manufacturing yield.
[0056] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0057] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A post-etching process method for improving copper loss in a via array region of a semiconductor device, the semiconductor device comprising a via structure formed by an integrated etching process, the via structure exposing an underlying copper metal layer, characterized in that, At least including: Step 1: Perform automatic surface inspection on the wafer that has undergone integrated etching process to identify abnormal via areas; Step 2: Analyze the abnormal via region using analytical tools to confirm that the anomaly is caused by copper loss in the copper metal layer at the bottom of the via structure; and Step 3: After the integrated etching process and before the subsequent wet stripping process, an enhanced post-etching process is performed on the wafer. The enhanced post-etching process includes treating the surface of the copper metal layer exposed by the via structure with reducing plasma.
2. The post-etching process method for improving copper loss in via array regions of semiconductor devices according to claim 1, characterized in that: In step two, the analytical tools include at least one of scanning electron microscopy, transmission electron microscopy, and energy-dispersive X-ray spectroscopy.
3. The post-etching process for improving copper loss in via array regions of semiconductor devices according to claim 1 or 2, characterized in that: In step two, it is confirmed that the copper loss manifests as corrosion, pitting, or discontinuity on the surface of the copper metal layer.
4. The post-etching process method for improving copper loss in via array regions of semiconductor devices according to claim 2, characterized in that: In step two, the analysis also includes using energy-dispersive X-ray spectroscopy to confirm that the abnormal via region is free from contamination by any abnormal impurity elements other than those introduced by the process.
5. The post-etching process method for improving copper loss in via array regions of semiconductor devices according to claim 1, characterized in that: In step three, the reducing plasma is used to passivate the surface of the copper metal layer and / or reduce the copper oxides or copper fluorides formed on the surface of the copper metal layer during the integrated etching process.
6. The post-etching process for improving copper loss in via array regions of semiconductor devices according to claim 1, characterized in that: In step three, the reducing plasma contains hydrogen gas.
7. The post-etching process method for improving copper loss in via array regions of semiconductor devices according to claim 6, characterized in that: In step three, the plasma further contains nitrogen gas.
8. The post-etching process for improving copper loss in via array regions of semiconductor devices according to claim 7, characterized in that: In step three, the N2:H2 gas volume ratio in the plasma is between 1:1 and 3:1, the total gas flow rate is 0-600 sccm, and the radio frequency power ranges from 0-400 W.
9. The post-etching process method for improving copper loss in via array regions of semiconductor devices according to claim 1, characterized in that: In step three, prior to performing the enhanced post-etching process, a first post-etching process using plasma containing carbon monoxide and / or carbon dioxide is first performed to remove residual polymer generated during the integrated etching process.
10. The post-etching process for improving copper loss in via array regions of semiconductor devices according to claim 1, characterized in that: The method further includes performing automatic surface inspection again after step three, and confirming that the number of abnormal vias has decreased compared with the inspection results of step one.
11. The post-etching process for improving copper loss in via array regions of semiconductor devices according to claim 1, characterized in that: The through-hole structure is a high-density through-hole array structure.
12. The post-etching process method for improving copper loss in via array regions of semiconductor devices according to claim 1, characterized in that: The method is applied to the back-end metal interconnect process of semiconductor devices.