Method for preparing cross-layer interconnect structure, cross-layer interconnect structure and semiconductor device

Abstract

The present application provides a method for preparing a cross-layer interconnect structure, a cross-layer interconnect structure and a semiconductor device. The method includes: providing a semiconductor substrate; forming one or more interconnect units on the semiconductor substrate; wherein each interconnect unit is prepared by sequentially performing the following steps: sequentially depositing a shallow trench isolation structure and a first dielectric layer on the semiconductor substrate; etching the first dielectric layer to form a first groove, and depositing a metal material in the first groove to form a first metal structure; forming a first metal interconnect layer on the first metal structure; flipping and removing the semiconductor substrate to expose the shallow trench isolation structure; forming a second dielectric layer on the shallow trench isolation structure; etching the second dielectric layer, the shallow trench isolation structure and the first dielectric layer until the first metal structure is exposed to form a second groove, and depositing a metal material in the second groove to form a second metal structure; forming a second metal interconnect layer on the second metal structure.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a method for preparing a cross-layer interconnect structure, a cross-layer interconnect structure and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some stacked transistor manufacturing schemes, in order to achieve interlayer interconnection between upper and lower layers of transistors, a field region needs to be set inside a standard transistor unit to form a field region direct connection structure. However, this will increase the area of ​​the standard transistor unit, which is not conducive to the miniaturization of the integrated circuit. Summary of the invention

[0004] The present application provides a method for preparing a cross-layer interconnect structure, a cross-layer interconnect structure and a semiconductor device to realize a standard structure for directly connecting stacked transistors across layers, thereby eliminating the need to increase the area of ​​the standard transistor unit and effectively improving the integration of the integrated circuit.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a cross-layer interconnect structure, the method comprising: providing a semiconductor substrate; forming one or more interconnect units on the semiconductor substrate; wherein each interconnect unit is prepared by sequentially performing the following steps: sequentially depositing a shallow trench isolation structure and a first dielectric layer on the semiconductor substrate; etching the first dielectric layer to form a first groove, and depositing a metal material in the first groove to form a first metal structure; forming a first metal interconnect layer on the first metal structure, the first metal interconnect layer being used to connect a third metal interconnect layer of a stacked transistor; flipping and removing the semiconductor substrate to expose the shallow trench isolation structure; forming a second dielectric layer on the shallow trench isolation structure; etching the second dielectric layer, the shallow trench isolation structure and the first dielectric layer until the first metal structure is exposed to form a second groove, and depositing a metal material in the second groove to form a second metal structure; forming a second metal interconnect layer on the second metal structure, the second metal interconnect layer being used to connect a fourth metal interconnect layer of the stacked transistor; wherein the first metal structure and the second metal structure constitute a first direct connection structure, the first direct connection structure connecting the first metal interconnect layer and the second metal interconnect layer.

[0006] In some possible embodiments, along a first direction, a first simulated gate structure is formed on a first side of a first dielectric layer, and a second simulated gate structure is formed on a first side of a second dielectric layer; the first simulated gate structure and the second simulated gate structure are arranged relative to each other; based on the first simulated gate structure, a first single diffusion isolation structure is formed; based on the second simulated gate structure, a second single diffusion isolation structure is formed; the first single diffusion isolation structure and the second single diffusion isolation structure are used to isolate the first direct connection structure from other external structures.

[0007] In some possible embodiments, along the first direction, a third pseudo-gate structure is formed on the second side of the first dielectric layer, and a fourth pseudo-gate structure is formed on the second side of the second dielectric layer; the third pseudo-gate structure and the fourth pseudo-gate structure are arranged relatively to each other; based on the third pseudo-gate structure, a third single diffusion isolation structure is formed; on the fourth pseudo-gate structure, a fourth single diffusion isolation structure is formed; the first single diffusion isolation structure, the second single diffusion isolation structure, the third single diffusion isolation structure and the fourth single diffusion isolation structure are all used to isolate the first direct connection structure from other external structures.

[0008] In some possible embodiments, along the first direction, a fifth quasi-gate structure is formed on the second side of the first dielectric layer, and a sixth quasi-gate structure is formed on the second side of the second dielectric layer; the fifth quasi-gate structure and the sixth quasi-gate structure are arranged relatively to each other; a shallow trench isolation structure between the fifth quasi-gate structure and the sixth quasi-gate structure is etched to form a first through hole; a metal material is deposited in the first through hole to form a through-layer through hole structure; wherein the fifth quasi-gate structure, the through-layer through hole structure and the sixth quasi-gate structure are connected to form a second direct connection structure; the second direct connection structure is used to connect the first metal interconnection layer and the second metal interconnection layer; the second direct connection structure is also used to separate two adjacent interconnection units.

[0009] In some possible implementations, a shallow trench isolation structure and a first dielectric layer are sequentially deposited on a semiconductor substrate, including: providing a semiconductor substrate; etching the semiconductor substrate to form an active structure; removing the active structure using a fin-cut process; and sequentially depositing an oxide material and a dielectric material on the semiconductor substrate after the fin-cut process to form a shallow trench isolation structure and a first dielectric layer.

[0010] In a second aspect, an embodiment of the present application provides a cross-layer interconnect structure, which includes: one or more interconnect units, wherein each interconnect unit includes: a first direct connection structure; a first metal interconnect layer, arranged at a first end of the first direct connection structure; a second metal interconnect layer, arranged at a second end of the first direct connection structure; the second end and the first end are two ends arranged opposite to each other in a second direction; the first direct connection structure is used to connect the first metal interconnect layer and the second metal interconnect layer.

[0011] In some possible embodiments, the cross-layer interconnect structure further includes: a first metal interconnect layer includes a plurality of first metal wires, the plurality of first metal wires extend along a first direction and are arranged at intervals along a third direction; the third direction is perpendicular to the first direction and the second direction; the second metal interconnect layer includes a plurality of second metal wires, the plurality of second metal wires extend along the first direction and are arranged at intervals along the third direction; a projection of the first direct connection structure toward the first metal interconnect layer overlaps or partially overlaps with at least one first metal wire, and a projection of the first direct connection structure toward the second metal interconnect layer overlaps or partially overlaps with at least one second metal wire; the first direct connection structure is used to connect a first metal wire in the first metal interconnect layer to a second metal wire in the second metal interconnect layer.

[0012] In some possible implementations, the first direct connection structure includes a first metal structure and a second metal structure, and the first metal structure is connected to the second metal structure.

[0013] In some possible implementations, the interconnection unit further includes: a fifth single diffusion partition structure arranged on a first side of the first direct connection structure along a first direction, the fifth single diffusion partition structure being used to isolate the first direct connection structure from other external structures, and the first direction is perpendicular to the second direction.

[0014] In some possible implementations, the interconnection unit further includes: a sixth single diffusion partition structure disposed along the first direction on the second side of the first direct connection structure, the sixth single diffusion partition structure being used to isolate the first direct connection structure from other external structures.

[0015] In some possible embodiments, the interconnection unit also includes: a second direct connection structure arranged on the second side of the first direct connection structure along the first direction; the second direct connection structure includes a fifth pseudo-gate structure, a through-layer via structure and a sixth pseudo-gate structure, and the fifth pseudo-gate structure, the through-layer via structure and the sixth pseudo-gate structure are connected; the second direct connection structure is used to connect the first metal interconnection layer and the second metal interconnection layer.

[0016] In some possible implementations, the width of the first metal structure in the first direction matches the width of the first dielectric layer in the first direction; the width of the second metal structure in the first direction matches the width of the second dielectric layer in the first direction.

[0017] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a cross-layer interconnect structure as described in the above embodiment.

[0018] In the embodiment of the present application, by forming two interlayer dielectric layers, and forming a first metal structure and a second metal structure connected in the two interlayer dielectric layers, a first direct connection structure can be formed inside the cross-layer interconnect structure; the first metal interconnect layer and the second metal interconnect layer are connected through the first direct connection structure, the first metal interconnect layer is connected to the third metal interconnect layer of the stacked transistor, and the second metal interconnect layer is connected to the fourth metal interconnect layer of the stacked transistor, so that the third metal interconnect layer and the fourth metal interconnect layer of the stacked transistor can be directly connected through the first direct connection structure. It can be seen that the embodiment of the present application provides a new wiring scheme by forming a cross-layer interconnect structure for cross-layer direct connection of stacked transistors, thereby effectively improving the integration of integrated circuits without increasing the area of ​​standard transistor units.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0021] Figure 1 A schematic diagram of a structure of a stacked transistor in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of a first structure of a cross-layer interconnect structure in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of an implementation process of a method for preparing a cross-layer interconnect structure in an embodiment of the present application;

[0024] Figures 4 to 17 A schematic diagram of a preparation process of a cross-layer interconnect structure according to an embodiment of the present application;

[0025] Fig.18 is a schematic diagram of a second structure of a cross-layer interconnect structure in an embodiment of the present application;

[0026] Fig.19 A schematic diagram of a third structure of a cross-layer interconnect structure in an embodiment of the present application;

[0027] Fig. 20 is a schematic diagram of a fourth structure of a cross-layer interconnect structure in an embodiment of the present application;

[0028] Fig.21 is a schematic diagram of a fifth structure of the cross-layer interconnect structure in an embodiment of the present application;

[0029] Fig. 22is a schematic diagram of a sixth structure of a cross-layer interconnect structure in an embodiment of the present application;

[0030] Fig.23 for Fig. 22 The cross-layer interconnect structure is a schematic cross-sectional view along the gate structure.

[0031] The above figures: 10, cross-layer interconnect structure; 11, field region; 111, first metal structure; 112, first metal interconnect layer; 113, first dielectric layer; 114, lower pseudo-gate structure; 115, first single diffusion partition structure; 116, third single diffusion partition structure; 117, fifth pseudo-gate structure; 12, field region direct connection structure; 121, second metal structure; 122, second metal interconnect layer; 123, second dielectric layer; 124, upper pseudo-gate structure; 125, second single diffusion partition structure; 126, fourth single diffusion partition structure 1. a first quasi-gate structure; 127. a sixth quasi-gate structure; 13. a first direct connection region; 14. a second direct connection region; 15. a third direct connection region; 16. a fourth direct connection region; 17. a fifth direct connection region; 18a. a first interconnection unit; 18b. a second interconnection unit; 18c. a third interconnection unit; 20. a semiconductor substrate; 21. a fin-shaped structure; 22. a shallow trench isolation structure; 23. a first polysilicon structure; 24. a first side wall; 25. a carrier wafer; 26. a first insulating layer; 27. a second side wall; 28. a second groove; 29. ​​a through-layer via structure. DETAILED DESCRIPTION

[0032] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0033] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0034] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic scheme, and the second is a sequential scheme.

[0035] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0036] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the wafer on top of the already manufactured lower transistor, and the two transistors are stacked vertically. However, the temperature needs to be strictly controlled during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection lines. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.

[0037] In order to solve the technical problems existing in the above two solutions, a self-aligned stacked transistor is proposed. The active areas of the upper and lower layers of the same source transistors are formed by etching, and the stacked transistors are made on the front and back sides of the wafer by flipping the wafer to overcome the shortcomings of the above two solutions.

[0038] However, in some solutions for preparing stacked transistors, in order to achieve interlayer interconnection between upper and lower layers of transistors, a field region needs to be provided inside a standard transistor unit to form a field region direct connection structure.

[0039] For example, Figure 1 Schematic diagram of a structure of a stacked transistor in an embodiment of the present application. Figure 1 (a) is a top view of a stacked transistor. It should be noted that, for ease of understanding, only the fin structure, the gate structure, the source-drain structure, and the field region direct connection structure are shown in the top view; Figure 1 (b) is along Figure 1 A cross-sectional view along the dashed line AA' in (a); Figure 1 (c) is along Figure 1 Cross-sectional view along the dotted line BB' in (a).

[0040] Reference Figure 1 As shown, the area in the dotted box is the field region 11 of the stacked transistor, and a field region direct connection structure 12 is formed in the field region 11. The cross-layer connection of the stacked transistor is achieved through the field region direct connection structure 12. However, when forming the field region direct connection structure 12, it is necessary to form a formed field region in the standard transistor through a fin cutting process. The new field region will increase the area of ​​the standard transistor unit, which is not conducive to the size reduction of the integrated circuit. In addition, inter-layer interconnection cannot be achieved for the area outside the standard transistor unit, so it is impossible to optimize the length of the back-end metal line according to the results of layout and wiring.

[0041] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a cross-layer interconnect structure, so as to provide a standard structure for directly connecting stacked transistors across layers, thereby eliminating the need to increase the area of ​​the standard transistor unit and effectively improving the integration of the integrated circuit.

[0042] Figure 2 Schematic diagram of the first structure of the cross-layer interconnection structure in the embodiment of the present application. Figure 2 (a) is a top view of a cross-layer interconnect structure. It should be noted that, for ease of understanding, only the pseudo-gate structure, the interconnect unit, the metal interconnect structure, the direct connection structure and the source-drain vias are shown in the top view; Figure 2 (b) is along Figure 2 A cross-sectional view along the dashed line AA' in (a); Figure 2 (c) is along Figure 2 Cross-sectional view along the dotted line BB' in (a).

[0043] See also Figure 2 As shown, the cross-layer interconnect structure 10 includes one or more interconnect units, wherein each interconnect unit includes two layers, upper and lower layers, corresponding to the positions of the upper and lower layers of transistors in the stacked transistors, respectively. The first metal structure 111 and the second metal structure 121 in the cross-layer interconnect structure 10 are connected to form a first direct connection structure, so that cross-layer transmission of signals can be performed.

[0044] In one embodiment, the cross-layer interconnect structure 10 further includes a first metal interconnect layer 112 and a second metal interconnect layer 122. The first metal interconnect layer 112 is connected to the first metal structure 111, and the second metal interconnect layer 122 is connected to the second metal structure 121. The first metal interconnect layer 112 and the second metal interconnect layer 122 can be connected to the metal interconnect layer in the stacked transistor. The signal in the stacked transistor can be transmitted to the metal interconnect layer in the cross-layer interconnect structure 10 through the metal interconnect layer in the stacked transistor, and then the cross-layer transmission is realized through the first direct connection structure in the cross-layer interconnect structure.

[0045] Reference Figure 2In (b) and (c), the first direct connection area 13 and the second direct connection area 14 in the cross-layer interconnect structure 10 can be seen respectively. In the first direct connection area 13 and the second direct connection area 14, the first metal structure 111 and the second metal structure 121 (constituting the first direct connection structure) connect the M0 signal metal line in the first metal interconnect layer 112 to the M0 signal metal line in the second metal interconnect layer 122, thereby connecting the M0 metals of the upper and lower layers.

[0046] Figure 3 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a cross-layer interconnect structure 10 in an embodiment of the present application, see Figure 3 As shown, the method for preparing the cross-layer interconnect structure 10 may include:

[0047] Providing a semiconductor substrate and forming one or more interconnection units on the semiconductor substrate;

[0048] Each interconnection unit is prepared by sequentially performing the following steps:

[0049] S301: depositing a shallow trench isolation structure and a first dielectric layer on a semiconductor substrate in sequence;

[0050] S302: etching the first dielectric layer to form a first groove, and depositing a metal material in the first groove to form a first metal structure;

[0051] S303: forming a first metal interconnection layer on the first metal structure, where the first metal interconnection layer is used to connect to a third metal interconnection layer of the stacked transistor;

[0052] S304: flipping the wafer and removing the semiconductor substrate to expose the shallow trench isolation structure;

[0053] S305: forming a second dielectric layer on the shallow trench isolation structure;

[0054] S306: etching the second dielectric layer, the shallow trench isolation structure, and the first dielectric layer until the first metal structure is exposed to form a second groove, and depositing a metal material in the second groove to form a second metal structure;

[0055] S307: forming a second metal interconnection layer on the second metal structure, where the second metal interconnection layer is used to connect to a fourth metal interconnection layer of the stacked transistor.

[0056] The first metal structure and the second metal structure constitute a first direct connection structure, and the first direct connection structure connects the first metal interconnection layer and the second metal interconnection layer.

[0057] It should be noted that Figure 3 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 3 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0058] Figures 4 to 17 FIG. 1 is a schematic diagram of a preparation process of a cross-layer interconnect structure 10 according to an embodiment of the present application. For ease of understanding, Figures 4 to 17 (a) shows the Figure 2 The cross-sectional view along the dashed line AA'. Figures 4 to 17 (b) shows the Figure 2 The cross-sectional view along the dotted line BB' Figures 2 to 17 The preparation method of the cross-layer interconnect structure 10 provided in the embodiment of the present application and the prepared cross-layer interconnect structure 10 are exemplarily described.

[0059] In step S301, refer to Figure 7 , a shallow trench isolation structure 22 and a first dielectric layer 113 are sequentially deposited on the semiconductor substrate 20 .

[0060] It is understandable that the shallow trench isolation structure 22 and the first dielectric layer 113 may be sequentially formed on the semiconductor substrate 20 through a deposition process.

[0061] The semiconductor substrate 20 may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0062] Here, a plurality of active structures may be formed on the semiconductor substrate 20 , or a plurality of active structures may not be formed on the semiconductor substrate 20 , and this embodiment of the present application does not specifically limit this.

[0063] It should be noted that when several active structures are formed on the semiconductor substrate 20, before forming the shallow trench isolation structure 22 and the first dielectric layer 113, the active structures on the semiconductor substrate 20 need to be removed to form a field region, thereby forming the shallow trench isolation structure 22 and the first dielectric layer 113 in the field region.

[0064] In one embodiment, a shallow trench isolation structure 22 and a first dielectric layer 113 are sequentially deposited on a semiconductor substrate 20, including: providing a semiconductor substrate 20; etching the semiconductor substrate 20 to form an active structure; removing the active structure using a fin cutting process; and sequentially depositing an oxide material and a dielectric material on the semiconductor substrate 20 after the fin cutting process to form a shallow trench isolation structure 22 and a first dielectric layer 113.

[0065] It is understandable that after the active structure is formed, the active structure inside the cross-layer interconnect structure 10 is cut away to form a field region inside the cross-layer interconnect structure 10, thereby using the field region to form an interconnect unit to achieve cross-layer interconnection between upper and lower layers of transistors in the field region.

[0066] Reference Figure 4 As shown, a semiconductor substrate 20 is provided, and a plurality of fin structures 21 standing upright on the semiconductor substrate may be formed on the semiconductor substrate 20 .

[0067] In one embodiment, a fin structure 21 is formed on a semiconductor substrate 20, including: forming a semiconductor epitaxial layer on the surface of the semiconductor substrate 20 through an epitaxial growth process; etching the semiconductor epitaxial layer to a certain depth in the semiconductor epitaxial layer or to the surface of the semiconductor substrate or to a certain depth in the substrate, thereby forming a plurality of fin structures 21.

[0068] It should be noted that while the wafer is processed to form the cross-layer interconnect structure 10, stacked transistors can be prepared at other locations at the same time. The fin structure 21 here can be used to form the active structure of the stacked transistor. In the preparation process of the cross-layer interconnect structure 10, forming the fin structure 21 on the semiconductor substrate 20 is not a necessary process step.

[0069] It can be understood that in the embodiment of the present application, since the upper and lower layers of transistors in the stacked transistor share the fin structure 21, that is, the first active structure of the lower layer transistor and the second active structure of the upper layer transistor are formed by the same etching process. Therefore, when forming the fin structure 21 on the semiconductor substrate 20, a larger etching depth can be used. For example, the depth of the etched fin structure 21 can be greater than 100nm.

[0070] Reference Figure 5 As shown, when a fin structure 21 is formed on a semiconductor substrate 20, in order to prepare a cross-layer interconnect structure 10, a fin cutting process is required to remove the fin structure 21 in the area corresponding to the cross-layer interconnect structure 10. After the removal, the fin structure 21 does not exist in the cross-sectional view along the AA' direction and the cross-sectional view along the BB' direction.

[0071] See also Figure 6 As shown, on the surface of the semiconductor substrate after the fin cutting process, an insulating material can be first deposited, and a chemical mechanical planarization process is used to remove the top surface of the insulating material until the top surface of the fin-shaped structure 21 is exposed, thereby forming a shallow trench isolation structure 22 (STI) whose top surface is flush with the top surface of the fin-shaped structure 21, and the shallow trench isolation structure 22 is further etched back to a certain depth so that the height of the shallow trench isolation structure 22 is related to the height required for preparing the upper transistor.

[0072] Here, the insulating material forming the shallow trench isolation structure 22 may be any one of the following: silicon nitride (SiN, Si 3 N 4 ), silicon dioxide (SiO 2 ) or silicon oxycarbide (SiCO), etc.

[0073] It can be understood that after the shallow trench isolation structure 22 is formed, an interlayer dielectric material may be deposited on the shallow trench isolation structure 22 to obtain the first dielectric layer 113 .

[0074] In some embodiments, a standard semiconductor manufacturing process can be used to form first polysilicon structures 23 and first dielectric layers 113 alternately arranged along a first direction on the shallow trench isolation structure 22. At the same time, a first sidewall 24 is formed between the first polysilicon structure 23 and the first dielectric layer 113.

[0075] In the embodiment of the present application, there are multiple first polysilicon structures 23, and at least two of the multiple first polysilicon structures 23 are located at the edge portions of both sides of the cross-layer interconnect structure 10. There can be one or more first dielectric layers 113, see Figure 5 As shown, a first dielectric layer 113 is shown.

[0076] In one embodiment, the method for forming the first polysilicon structure 23 and the first sidewall 24 may include: a deposition process may be used to deposit materials such as silicon dioxide on the surface of the shallow trench isolation structure 22 to form a dielectric layer. Subsequently, at least one of polysilicon, amorphous silicon, germanium (Ge), silicon germanium (SiGe), and silicon carbon (SiC) is deposited on the surface of the dielectric layer to form the first polysilicon structure 23. The first sidewall 24 is then formed on the sidewalls of each first polysilicon structure 23 by a sidewall process to prevent the sidewalls of the first polysilicon structure 23 from being damaged in the subsequent preparation process. The material of the sidewall may be silicon oxide, silicon nitride, or a multilayer material such as silicon oxide-silicon nitride-silicon oxide.

[0077] In the embodiment of the present application, after the first polysilicon structure 23 is formed, the first dielectric layer 113 is formed. An insulating material is deposited between two adjacent first polysilicon structures 23 to cover the shallow trench isolation structure 22 and the first polysilicon structure 23. Then, the insulating material above the first polysilicon structure 23 is removed by chemical mechanical polishing or etching to form the first dielectric layer 113. The top of the first dielectric layer 113 is flush with the top of the first polysilicon structure 23.

[0078] The first dielectric layer 113 is formed by chemical vapor deposition or high aspect ratio trench filling process (HARP). HARP can enhance the isolation effect of the first dielectric layer 113.

[0079] See also Figure 7As shown, a patterned mask layer (not shown) is formed on the first dielectric layer 113, and the first polysilicon structure 23 is etched using the mask layer until an opening is formed. Insulating material and metal material are deposited in the opening to form a lower layer pseudo-gate structure 114 (i.e., a first pseudo-gate structure and a third pseudo-gate structure) on both sides of the first dielectric layer 113 along a first direction.

[0080] Here, a fifth pseudo-gate structure may also be formed on the second side of the first dielectric layer 113 .

[0081] In one embodiment, the simulated gate structure includes: a simulated gate dielectric layer and a simulated gate electrode layer. The materials of the simulated gate dielectric layer and the simulated gate electrode layer can be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0082] Exemplarily, the pseudo-gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0083] Exemplarily, the simulated gate electrode layer may be composed of multiple layers of electrode materials, each layer of which includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0084] In one example, the pseudo-gate dielectric layer may include: a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0085] In step S302, see Figure 8 As shown, based on the first dielectric layer 113 , a first metal structure 111 is formed.

[0086] The first metal structure 111 may be a source-drain metal in a lower structure. The lower structure referred to here refers to a structure located in the lower layer after the cross-layer interconnect structure is prepared.

[0087] It should be noted that, for ease of explanation, the source-drain metals mentioned in the embodiments of the present application are abbreviations, specifically referring to source metals and / or drain metals. In addition, the source-drain structure, source-drain grooves, etc. are similar to the source-drain metals, where "source-drain" is an abbreviation for "source and / or drain".

[0088] In one embodiment, the first dielectric layer 113 is etched to form a first groove, and a metal material is deposited in the first groove to form a first metal structure. Here, the top surface of the first metal structure 111 is flush with the top surface of the first dielectric layer 113 .

[0089] See also Fig. 9As shown, the first pseudo-gate structure and the third pseudo-gate structure are removed to form a first single diffusion break structure 115 (Single diffusion break, SDB) and a third single diffusion break structure 116 at the edge of the cross-layer interconnect structure.

[0090] The first single diffusion isolation structure 115 and the third single diffusion isolation structure 116 can electrically isolate the cross-layer interconnect structure from external structural components.

[0091] It can be understood that the first pseudo-gate structure and the third pseudo-gate structure located at the edge are removed by an etching process, and an insulating material is deposited at the removed position to form the first single diffusion partition structure 115 and the third single diffusion partition structure 116. In this process, the first single diffusion partition structure 115 and the third single diffusion partition structure 116 are formed by self-alignment based on the position of the pseudo-gate structure, which effectively improves the preparation efficiency.

[0092] Exemplarily, the insulating material forming the first single diffusion isolation structure 115 may be silicon nitride (SiN).

[0093] In step S303, see Fig.10 As shown, after forming the first single diffusion isolation structure 115 and the third single diffusion isolation structure 116, a first metal interconnection layer 112 may be formed over the first metal structure 111, the first single diffusion isolation structure 115, and the third single diffusion isolation structure 116. Here, the first metal structure 111 may be connected to the metal line in the first metal interconnection layer 112.

[0094] It is understandable that the first metal interconnection layer 112 can be formed on the first metal structure 111, the first single diffusion isolation structure 115 and the third single diffusion isolation structure 116 through the back-end process of semiconductor preparation (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.).

[0095] Furthermore, the stacked transistor includes a third metal interconnection layer and a fourth metal interconnection layer, wherein the first metal interconnection layer is used to connect the third metal interconnection layer in the stacked transistor.

[0096] In one embodiment, the third metal interconnection layer and the first metal interconnection layer may be prepared using the same preparation process.

[0097] In some embodiments, the first metal interconnection layer 112 includes: a first interconnection sublayer and a second interconnection sublayer, wherein the first interconnection sublayer is in direct contact with the first metal structure 111 and can also be understood as M0 metal; the second interconnection sublayer is in direct contact with the first interconnection sublayer and can also be understood as M1 metal.

[0098] It can be understood that the M0 metal is connected to the first metal structure 111 .

[0099] In some embodiments, a fifth quasi-gate structure is formed on the second side of the first dielectric layer 113. The fifth quasi-gate structure is used to separate two adjacent interconnection units. Therefore, there is no need to generate a single diffusion isolation structure based on the fifth quasi-gate structure, thereby effectively reducing the difficulty of preparing the cross-layer interconnection structure 10.

[0100] In step S304, see Fig.11 As shown, the structure formed in step S303 can be bonded to the carrier wafer 25. Then, the structure is flipped so that the semiconductor substrate 20 is located at the upper part, which is convenient for subsequent use to prepare the upper structure of the cross-layer interconnect structure 10. Fig.12 As shown, the semiconductor substrate 20 may be removed by polishing or chemical mechanical planarization to expose the shallow trench isolation structure 22 .

[0101] In one embodiment, an insulating material (such as silicon oxide) may be deposited on the first metal interconnection layer 112 to form a first insulating layer 26 , and the first insulating layer 26 is bonded to the carrier wafer 25 .

[0102] In step S305 , an interlayer dielectric material may be deposited on the shallow trench isolation structure 22 to form a second dielectric layer 123 .

[0103] It should be noted that the position of the second dielectric layer 123 may correspond to the position of the first dielectric layer 113 .

[0104] In some embodiments, reference Fig.13 A second dielectric layer 123 and an upper pseudo-gate structure 124 (i.e., a second pseudo-gate structure and a fourth pseudo-gate structure) arranged alternately in a first direction can be formed on the shallow trench isolation structure 22 by using a standard semiconductor manufacturing process. A second sidewall 27 is formed between the second dielectric layer 123 and the upper pseudo-gate structure 124.

[0105] It is understandable that the steps of forming the second dielectric layer 123 and the upper pseudo-gate structure 124 may refer to the steps of forming the first dielectric layer 113 and the lower pseudo-gate structure 114 , and will not be described again for the sake of brevity.

[0106] The position of the upper pseudo gate structure 124 may correspond to the position of the lower pseudo gate structure 114. That is, the position of the first pseudo gate structure may correspond to the position of the second pseudo gate structure, and the position of the third pseudo gate structure may correspond to the position of the fourth pseudo gate structure.

[0107] Reference Fig.14 , the second quasi-gate structure and the fourth quasi-gate structure are removed to form a second single diffusion isolation structure 125 and a fourth single diffusion isolation structure 126 .

[0108] It is understandable that the steps of forming the second single diffusion partition structure 125 and the fourth single diffusion partition structure 126 may refer to the steps of forming the first single diffusion partition structure 115 and the third single diffusion partition structure 116, and will not be repeated here for the sake of brevity.

[0109] In some embodiments, a fifth quasi-gate structure is formed on the second side of the first dielectric layer 113 , and a sixth quasi-gate structure is formed on the second side of the second dielectric layer 123 ; the current interconnection unit can be separated from other interconnection units based on the fifth quasi-gate structure and the sixth quasi-gate structure.

[0110] It should be noted that a simulated gate structure may be formed between the multiple interconnection units, or a simulated gate structure may not be formed, and the embodiments of the present application do not specifically limit this.

[0111] In one embodiment, before forming the sixth pseudo-gate structure on the second side of the second dielectric layer 123, a shallow trench isolation structure between the fifth pseudo-gate structure and the sixth pseudo-gate structure may be etched to form a first through hole. Subsequently, a metal material is deposited in the first through hole to form a through-layer through hole structure connecting the fifth pseudo-gate structure and the sixth pseudo-gate structure.

[0112] The fifth pseudo-gate structure, the through-layer via structure and the sixth pseudo-gate structure are connected to form a second direct connection structure.

[0113] It can be understood that a conductive path is formed by using the metal material in the pseudo-gate structure and the metal material in the through-layer via structure, so that the second direct connection structure is used to connect the first metal interconnection layer and the second metal interconnection layer in the subsequent step. The second direct connection structure provides a new solution for realizing the direct connection of the upper and lower metal interconnection layers.

[0114] In step S306, refer to Fig.17 , the second dielectric layer 123 , the shallow trench isolation structure 22 and the first dielectric layer 113 are etched until the first metal structure 111 is exposed to form a second groove 28 ; and a metal material is deposited in the second groove 28 to form a second metal structure 121 .

[0115] It is understandable that by opening holes in the second dielectric layer 123 and the first dielectric layer 113, the first metal structure 111 prepared before flipping can be exposed, thereby forming the second groove 28. Based on the second groove 28, the second metal structure 121 can be formed.

[0116] In some embodiments, reference Fig.15 As shown, a second groove 28 with a larger top and a smaller bottom can be formed in the second dielectric layer 123 and the first dielectric layer 113. Fig.16As shown, the source-drain metal grooves in the upper structure are formed by etching, so that the shape of the upper portion of the second groove 28 is the same as the shape of the first metal structure 111 .

[0117] It should be noted that here the execution Fig.16 The steps shown are because the layout of the standard transistor unit is directly used when preparing the cross-layer interconnect structure 10, so no new layout is required, which effectively reduces the complexity of preparation.

[0118] In step S307, refer to Figure 2 As shown, in Fig.17 After forming the second metal structure 121, a second metal interconnection layer 122 may be formed on the second metal structure 121, the second single diffusion isolation structure 125, and the fourth single diffusion isolation structure 126. Here, the second metal structure 121 may be connected to the metal line in the second metal interconnection layer 122. The second metal interconnection layer 122 is connected to the fourth metal interconnection layer of the stacked transistor.

[0119] For example, after forming the second metal interconnection layer 122, the signal metal lines (M0signal) in the two metal interconnection layers may be connected via a cross-layer interconnection structure.

[0120] The first metal structure 111 and the second metal structure 121 are connected to form a first direct connection structure. The first direct connection structure is used to connect the metal lines in the first metal interconnection layer 112 and the second metal interconnection layer 122. The first metal interconnection layer 112 is connected to the third metal interconnection layer of the stacked transistor, and the second metal interconnection layer 122 is connected to the fourth metal interconnection layer of the stacked transistor, so that in the layout and wiring process of the stacked transistor, the upper and lower metal interconnection layers of the stacked transistor can be connected to the two metal interconnection layers of the cross-layer interconnection structure 10 respectively, and then the first direct connection structure and the second direct connection structure in the cross-layer interconnection structure are used to realize the cross-layer transmission of the signal.

[0121] It should be noted that the first direct connection structure and the second direct connection structure can be connected to the signal metal wire in the metal interconnection layer, and can also be connected to the power supply metal wire in the metal interconnection layer, and the embodiment of the present application does not make specific limitations on this.

[0122] For example, Fig.18 Schematic diagram of the second structure of the cross-layer interconnection structure in the embodiment of the present application. Fig.18 (a) is a top view of a cross-layer interconnect structure. It should be noted that, for ease of understanding, only the pseudo-gate structure, the interconnect unit, the metal interconnect structure, the direct connection structure, the upper source-drain vias, and the lower source-drain vias are shown in the top view; Fig.18 (b) is along Fig.18 A cross-sectional view along the dashed line AA' in (a); Fig.18 (c) is along Fig.18 A cross-sectional view along the dashed line BB' in (a); Fig.18 (d) is along Fig.18 Cross-sectional view along the dotted line CC' in (a).

[0123] Reference Fig.18 As shown in (b), (c) and (d) in FIG. 1 , the width of the first metal structure 111 can be freely set in the AA' direction, so that the first metal structure 111 can connect the power supply metal line in the metal interconnection layer. The power supply metal line in the lower metal interconnection layer can be connected to the signal metal line in the upper metal interconnection layer through the first metal structure 111 and the second metal structure 121.

[0124] Reference Fig.18 In (b), (c) and (d), the third direct connection area 15, the fourth direct connection area 16 and the fifth direct connection area 17 in the cross-layer interconnect structure 10 can be seen respectively. In the third direct connection area 15, the fourth direct connection area 16 and the fifth direct connection area 17, the first metal structure 111 and the second metal structure 121 (constituting the first direct connection structure) connect the back M0 power supply metal line to the front M0 signal metal line to achieve the connection of the upper and lower M0 metals.

[0125] In the embodiment of the present application, by forming two interlayer dielectric layers, and forming a first metal structure and a second metal structure connected in the two interlayer dielectric layers, a first direct connection structure can be formed inside the cross-layer interconnect structure; the first metal interconnect layer and the second metal interconnect layer are connected through the first direct connection structure, the first metal interconnect layer is connected to the third metal interconnect layer of the stacked transistor, and the second metal interconnect layer is connected to the fourth metal interconnect layer of the stacked transistor, so that the third metal interconnect layer and the fourth metal interconnect layer of the stacked transistor can be directly connected through the first direct connection structure. It can be seen that the embodiment of the present application provides a new wiring scheme by forming a cross-layer interconnect structure for cross-layer direct connection of stacked transistors, thereby effectively improving the integration of integrated circuits without increasing the area of ​​standard transistor units.

[0126] Combine the following Figure 3 The preparation method shown briefly describes various structures of the cross-layer interconnect structure in the embodiments of the present application. Fig.19 A schematic diagram of a third structure of a cross-layer interconnect structure in an embodiment of the present application; Fig. 20 is a schematic diagram of a fourth structure of a cross-layer interconnect structure in an embodiment of the present application; Fig.21 is a schematic diagram of a fifth structure of the cross-layer interconnect structure in an embodiment of the present application; Fig. 22 Schematic diagram of the sixth structure of the cross-layer interconnection structure in the embodiment of the present application. Figures 19 to 22They are all top views of cross-layer interconnect structures. It should be noted that for ease of understanding, the top views only show the pseudo-gate structure, dielectric layer structure, metal interconnect structure, direct connection structure, through-layer via structure and source-drain via / gate via.

[0127] Reference Figures 2 to 22 As shown, the cross-layer interconnect structure 10 in the example of the present application includes: one or more interconnect units, wherein each interconnect unit includes: a first direct connection structure, a first metal interconnect layer 112 and a second metal interconnect layer 122 .

[0128] The first metal interconnection layer 112 is disposed at the first end of the first direct connection structure; the second metal interconnection layer 122 is disposed at the second end of the first direct connection structure; the second end and the first end are two ends disposed opposite to each other in the second direction. The second direction is the preparation direction of the cross-layer interconnection structure 10.

[0129] See also Figures 1 to 22 As shown, the first direct connection structure is arranged in the dielectric layer structure, and is used to connect the first metal interconnection layer 112 and the second metal interconnection layer 122, so as to realize cross-layer interconnection between the upper and lower metal interconnection layers.

[0130] In one embodiment, the interconnection unit further includes: a single diffusion partition structure disposed on both sides of at least one first direct connection structure along the first direction, the single diffusion partition structure being used to isolate the first direct connection structure from other external structures.

[0131] It is understandable that as a standard unit for realizing cross-layer signal transmission, the cross-layer interconnect structure needs to form a single diffusion isolation structure at its edge to ensure that the signal is transmitted across layers at least by the first direct connection structure in the middle of the cross-layer interconnect structure.

[0132] There may be one or more interconnection units in the cross-layer interconnection structure 10. In order to realize multiple interconnection units, the cross-layer interconnection structure 10 may appropriately increase its width in the first direction.

[0133] See also Fig.19 As shown, the cross-layer interconnect structure 10 forms three interconnect units between three contact poly pitches (CPP), each of which includes a first direct connection structure, so that multiple interconnect lines are realized by using one cross-layer interconnect structure.

[0134] In some embodiments, the first metal interconnect layer 112 includes a plurality of first metal lines extending along a first direction and arranged at intervals along a third direction; the third direction is perpendicular to the first direction and perpendicular to the second direction.

[0135] The second metal interconnection layer 122 includes a plurality of second metal lines extending along the first direction and arranged at intervals along the third direction.

[0136] It can be understood that the single diffusion structure or the pseudo-gate structure located on both sides of the first direct connection structure in the first direction can limit the position of the first direct connection structure in the first direction, making it difficult for the first direct connection structure to be freely arranged in the first direction but can be freely arranged in the second direction. Accordingly, a plurality of metal wires can be arranged at intervals in the second direction, so that different metal wires can be connected as the first direct connection structure is freely arranged in the second direction, thereby adapting to a variety of different wiring schemes.

[0137] The projection of the first direct connection structure toward the first metal interconnection layer 112 overlaps or partially overlaps with at least one first metal line, and the projection of the first direct connection structure toward the second metal interconnection layer 122 overlaps or partially overlaps with at least one second metal line; the first direct connection structure is at least used to connect a first metal line in the first metal interconnection layer 112 with a second metal line in the second metal interconnection layer 122.

[0138] It can be understood that the first direct connection structure at least connects a first metal line and a second metal line, so that a signal can be transmitted from the first metal interconnection layer 112 to the second metal interconnection layer 122 across layers.

[0139] In some embodiments, the first direct connection structure includes a first metal structure 111 and a second metal structure 121, and the first metal structure 111 is connected to the second metal structure 121. The projection of the first metal structure 111 toward the first metal interconnection layer 112 overlaps or partially overlaps with at least one first metal line; the projection of the second metal structure 121 toward the second metal interconnection layer 122 overlaps or partially overlaps with at least one second metal line.

[0140] In some embodiments, the interconnection unit further includes: a fifth single diffusion partition structure disposed on a first side of the first direct connection structure along a first direction, the fifth single diffusion partition structure being used to isolate the first direct connection structure from other external structures. The first direction is perpendicular to the second direction.

[0141] The fifth single diffusion partition structure includes a first single diffusion partition structure 115 and a third single diffusion partition structure 116 .

[0142] In some embodiments, the interconnection unit further includes: a sixth single diffusion partition structure disposed along the first direction on the second side of the first direct connection structure, the sixth single diffusion partition structure being used to isolate the first direct connection structure from other external structures.

[0143] The sixth single diffusion partition structure includes a second single diffusion partition structure 125 and a fourth single diffusion partition structure 126 .

[0144] In some embodiments, the interconnection unit further includes: a second direct connection structure disposed along the first direction on the second side of the first direct connection structure; wherein the second direct connection structure includes a fifth quasi-gate structure, a through-layer via structure 29, and a sixth quasi-gate structure. The fifth quasi-gate structure, the through-layer via structure 29, and the sixth quasi-gate structure are connected.

[0145] The second direct connection structure is used to connect the first metal interconnection layer 112 and the second metal interconnection layer 122 .

[0146] It is understandable that the second direct connection structure can be arranged on the second side of the first direct connection structure. The fifth pseudo-gate structure, the through-layer via structure 29 and the sixth pseudo-gate structure in the second direct connection structure are all formed of metal materials, so that the second direct connection structure can connect the first metal interconnection layer 112 and the second metal interconnection layer 122.

[0147] For example, see Fig. 22 As shown, the cross-layer interconnect structure 10 includes three interconnect units, wherein each interconnect unit includes a first direct connection structure. In the first interconnect unit 18a, that is, the interconnect unit located on the leftmost side in the first direction, a fifth single diffusion partition structure is formed on the first side of the first direct connection structure, and a second direct connection structure is formed on the second side of the first direct connection structure; in the second interconnect unit 18b, that is, the interconnect unit located in the middle in the first direction, the first side of the first direct connection structure is adjacent to the second direct connection structure of the first interconnect unit 18a, and a second direct connection structure is formed on the second side of the first direct connection structure; in the third interconnect unit 18c, that is, the interconnect unit located on the rightmost side in the first direction, the first side of the first direct connection structure is adjacent to the second direct connection structure of the second interconnect unit 18b, and a sixth single diffusion partition structure is formed on the second side of the first direct connection structure.

[0148] It can be seen that in Fig. 22 The cross-layer interconnect structure 10 shown forms three first direct connection structures between three contact gate pitches, thereby forming a total of five direct connection structures between the three contact gate pitches, thereby realizing multiple interconnection lines by using one cross-layer interconnect structure.

[0149] Fig.23 for Fig. 22 The cross-layer interconnect structure is a schematic cross-sectional view along the gate structure. Fig.23 As shown, the second direct connection structure includes a fifth pseudo-gate structure 117, a through-layer via structure 29 and a sixth pseudo-gate structure 127. The through-layer via structure 29 is formed by opening a second through hole in the shallow trench isolation structure and depositing a metal material. Through the fifth pseudo-gate structure 117, the through-layer via structure 29 and the sixth pseudo-gate structure 127, the metal wires in the upper and lower metal interconnect layers can be connected.

[0150] In some embodiments, the width of the first metal structure 111 in the first direction matches the width of the first dielectric layer 113 in the first direction; the width of the second metal structure 121 in the first direction matches the width of the second dielectric layer 123 in the first direction.

[0151] For example, see Fig. 20 As shown, for a cross-layer interconnect structure whose width in the first direction is greater than two contact gate pitches, the pseudo-gate structure inside the cross-layer interconnect structure 10 may not be fabricated. Fig.21 As shown, the resistance of the direct connection structure can also be reduced by not forming a pseudo-gate structure inside the cross-layer interconnect structure and increasing the width of the first metal structure 111 or the second metal structure 121 .

[0152] In the embodiment of the present application, a cross-layer interconnection structure is designed specifically for directly connecting the upper and lower metal wires. During the layout and routing process, the upper and lower metal wires can be connected through the cross-layer interconnection structure. The cross-layer interconnection structure is conducive to reducing the total length of the back-end metal wires and reducing the load size of the back-end process. In addition, for a variety of different interconnection scenarios, such as scenarios where multiple interconnection lines are required to be connected, Figures 19 to 22 Any of the structures shown is optimized for wiring.

[0153] In particular, if the upper or lower layer wiring resources are tight, you can also use Fig.18 The structure in the embodiment connects the power supply metal line on the wiring-constrained side with the signal metal line on the other side, and utilizes the wiring resources on the other side to realize the power delivery network (PDN), which helps to alleviate the wiring congestion problem on the wiring-constrained side.

[0154] In one or more of the above-mentioned embodiments of preparing a cross-layer interconnect structure, the cross-layer interconnect structure is also self-aligned, which solves the long-standing problems of complex processes and alignment difficulties in the existing mainstream technical solutions for stacking transistors, and promotes the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are interconnected through the cross-layer interconnect structure, which greatly releases metal wiring resources without changing the extremely miniaturized 4T track unit design.

[0155] Finally, the solution of realizing upper and lower transistors by flipping the wafer is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar transistors, FinFET, GAA Nanosheet and even vertical transistors (VTFET), without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for development.

[0156] The present application embodiment provides a semiconductor device, including: a cross-layer interconnect structure as described in the above embodiment. The specific definition of the cross-layer interconnect structure can be found in the above Figure 2 , Figures 19 to 22 The cross-layer interconnection structure shown will not be described in detail here.

[0157] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above cross-layer interconnect structure. The specific definition of the cross-layer interconnect structure can be found in the above Figure 2 Figures 19 to 22 The structure shown is not described in detail here.

[0158] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0159] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a cross-layer interconnect structure, characterized in that: include: Providing a semiconductor substrate; forming one or more interconnect units on the semiconductor substrate; Each interconnection unit is prepared by sequentially performing the following steps: Depositing a shallow trench isolation structure and a first dielectric layer in sequence on a semiconductor substrate; Etching the first dielectric layer to form a first groove, and depositing a metal material in the first groove to form a first metal structure; forming a first metal interconnection layer on the first metal structure, wherein the first metal interconnection layer is used to connect to a third metal interconnection layer of the stacked transistor; Flipping and removing the semiconductor substrate to expose the shallow trench isolation structure; forming a second dielectric layer on the shallow trench isolation structure; Etching the second dielectric layer, the shallow trench isolation structure and the first dielectric layer until the first metal structure is exposed to form a second groove, and depositing a metal material in the second groove to form a second metal structure; forming a second metal interconnection layer on the second metal structure, wherein the second metal interconnection layer is used to connect to a fourth metal interconnection layer of the stacked transistor; Wherein, the first metal structure and the second metal structure constitute a first direct connection structure, and the first direct connection structure connects the first metal interconnection layer and the second metal interconnection layer; The method further comprises: Along a first direction, a first quasi-gate structure is formed on a first side of the first dielectric layer, and a second quasi-gate structure is formed on a first side of the second dielectric layer; the first quasi-gate structure and the second quasi-gate structure are arranged opposite to each other; Based on the first pseudo-gate structure, forming a first single diffusion isolation structure; Based on the second pseudo-gate structure, forming a second single diffusion isolation structure; The first single diffusion partition structure and the second single diffusion partition structure are used to isolate the first direct connection structure from other external structures.

2. The method according to claim 1, characterized in that: The method further comprises: Along the first direction, a third quasi-gate structure is formed on the second side of the first dielectric layer, and a fourth quasi-gate structure is formed on the second side of the second dielectric layer; the third quasi-gate structure and the fourth quasi-gate structure are arranged opposite to each other; Based on the third pseudo-gate structure, forming a third single diffusion isolation structure; Based on the fourth pseudo-gate structure, a fourth single diffusion isolation structure is formed; The first single diffusion partition structure, the second single diffusion partition structure, the third single diffusion partition structure and the fourth single diffusion partition structure are all used to isolate the first direct connection structure from other external structures.

3. The method according to claim 1, characterized in that: The method further comprises: Along the first direction, a fifth quasi-gate structure is formed on the second side of the first dielectric layer, and a sixth quasi-gate structure is formed on the second side of the second dielectric layer; the fifth quasi-gate structure and the sixth quasi-gate structure are arranged opposite to each other; Etching a shallow trench isolation structure between the fifth pseudo-gate structure and the sixth pseudo-gate structure to form a first through hole; Depositing a metal material in the first through hole to form a through-layer through hole structure; Among them, the fifth pseudo-gate structure, the through-layer via structure and the sixth pseudo-gate structure are connected to form a second direct connection structure; the second direct connection structure is used to connect the first metal interconnection layer and the second metal interconnection layer; the second direct connection structure is also used to separate two adjacent interconnection units.

4. The method according to claim 1, characterized in that The step of sequentially depositing a shallow trench isolation structure and a first dielectric layer on a semiconductor substrate comprises: Providing a semiconductor substrate; Etching the semiconductor substrate to form an active structure; Removing the active structure by using a fin cutting process; An oxide material and a dielectric material are sequentially deposited on the semiconductor substrate after the fin cutting process to form the shallow trench isolation structure and the first dielectric layer.

5. A cross-layer interconnect structure, prepared using the preparation method according to any one of claims 1 to 4, characterized in that: include: One or more interconnected units, wherein each interconnected unit comprises: First direct structure; A first metal interconnect layer, disposed at a first end of the first direct connection structure; A second metal interconnection layer is disposed at a second end of the first direct connection structure; the second end and the first end are two ends disposed opposite to each other in a second direction; The first direct connection structure is used to connect the first metal interconnection layer and the second metal interconnection layer; The interconnection unit further includes: a fifth single diffusion partition structure disposed on a first side of the first direct connection structure along a first direction, the fifth single diffusion partition structure being used to isolate the first direct connection structure from other external structures, the first direction being perpendicular to the second direction; A sixth single diffusion partition structure is disposed along the first direction on the second side of the first direct connection structure, and the sixth single diffusion partition structure is used to isolate the first direct connection structure from other external structures.

6. The structure according to claim 5, characterized in that The first metal interconnection layer includes a plurality of first metal lines, the plurality of first metal lines extend along a first direction and are arranged at intervals along a third direction; the third direction is perpendicular to the first direction and perpendicular to the second direction; The second metal interconnect layer includes a plurality of second metal lines extending along the first direction and arranged at intervals along the third direction; The projection of the first direct connection structure toward the first metal interconnection layer overlaps or partially overlaps with at least one first metal line, and the projection of the first direct connection structure toward the second metal interconnection layer overlaps or partially overlaps with at least one second metal line; The first direct connection structure is used to connect the first metal line in the first metal interconnection layer to the second metal line in the second metal interconnection layer.

7. The structure according to claim 5, characterized in that The first direct connection structure includes a first metal structure and a second metal structure, and the first metal structure is connected to the second metal structure.

8. The structure according to claim 5, characterized in that The interconnection unit further includes: A second direct connection structure disposed along a first direction on a second side of the first direct connection structure; The second direct connection structure includes a fifth pseudo-gate structure, a through-layer via structure and a sixth pseudo-gate structure, and the fifth pseudo-gate structure, the through-layer via structure and the sixth pseudo-gate structure are connected; The second direct connection structure is used to connect the first metal interconnection layer and the second metal interconnection layer.

9. The structure according to claim 7, characterized in that The width of the first metal structure in the first direction matches the width of the first dielectric layer in the first direction; The width of the second metal structure in the first direction matches the width of the second dielectric layer in the first direction.

10. A semiconductor device, characterized in that: include: A cross-layer interconnect structure as claimed in any one of claims 5 to 9.

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