A digital calibration circuit for TIADC sampling time error

Abstract

The present invention provides a digital calibration circuit for TIADC sampling time errors, which relates to the field of analog-to-digital converters. The TIADC in this circuit includes multiple sequentially connected clocks, sampling switches, and quantization conversion modules. The clocks generate divided-frequency clocks. The sampling switches are triggered by the rising edge of the corresponding divided-frequency clocks to conduct, thereby sampling input data. The quantization conversion module quantizes the sampled data to obtain digital code values and sends them to a digital calibration module. The digital calibration module processes the digital code values to obtain mismatch information for each sampling switch and, based on the mismatch information, determines a compensation code value for the corresponding circuit to be calibrated. A time error compensation circuit compensates the corresponding clocks based on the compensation code values, ensuring that the time delay from the divided-frequency clocks generated by each clock to the corresponding sampling switches is equal. The present invention achieves sampling time error calibration within the full bandwidth region.

Description

Technical Field

[0001] The present invention relates to the field of analog-to-digital converters, and in particular to a digital calibration circuit, system and electronic equipment for TIADC sampling time error. Background Art

[0002] Analog-to-digital converters (ADCs) bridge the gap between analog and digital systems and are a crucial component of modern signal processing systems. They are widely used in communications, radar, test equipment, and other fields. Time-interleaved analog-to-digital converters (TIADCs) can overcome the performance limitations of single ADC devices, exponentially increasing system sampling frequencies and meeting the high-speed, wideband requirements of various industries. Furthermore, at the same sampling frequency, TIADCs offer significant advantages over single ADCs in terms of cost and power consumption. However, TIADCs can suffer from DC mismatch, gain mismatch, and sampling time mismatch between their multiple sub-ADCs, which can introduce noise and interfere with TIADC performance. While there are established and simple methods for correcting DC and gain mismatch in TIADCs, reliable extraction and stable calibration of sampling time deviations are more challenging. This is particularly true given that many current research papers rely on single-tone calibration schemes, while actual ADCs are primarily used for wideband or multi-tone signals. Therefore, when TIADCs are used in full-bandwidth scenarios, sampling time error calibration is crucial for accurately and stably extracting mismatch information based on different communication signal types.

[0003] Various methods have been proposed for calibrating sampling time mismatch errors in TIADCs. The earliest, proposed by Jamal et al. in 2002, involved extracting sampling time offsets based on correlation calculations, but this approach was not scalable to more channels or even arbitrary channels. In 2006, Chung-Yi Wang et al. proposed performing zero detection between channels to extract sampling offsets, but this approach was not ideal at high frequencies. In 2014, Luke Wang proposed extracting sampling offsets by calculating the absolute difference between two and four channels (or, in other words, the statistical characteristics of the data's symbol distribution), but this approach imposed certain constraints on the input frequency band. In 2015, Dengquan Li extended correlation extraction to eight channels using background calibration. In 2017, Hamidreza Mafi et al. extracted sampling errors based on the probability density curve (CDF) of adjacent channel data output by the ADC. This approach required extensive statistical data, and even with the expansion of the channel count, some frequencies remained uncalibrated. In 2018, Hyun-Wook Kang added an additional reference ADC channel to the TIADC analog side for calibration. This approach limited the performance of the ref channel and also increased ADC resources.

[0004] There are two main shortcomings: the multi-channel expansion is limited, the number of channels is strongly correlated with the calibration error extraction, and it cannot be expanded arbitrarily. Even the calibration reference standard is fixed, and the calibration requires complex process requirements; the calibration error extraction is limited to the extraction formula, and there are certain constraints on the input signal frequency range of the TIADC, otherwise it will not converge normally. Summary of the Invention

[0005] The object of the present invention is to provide a digital calibration circuit for TIADC sampling time error, so as to realize sampling time error calibration in the full bandwidth region.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] A digital calibration circuit for TIADC sampling time error comprises: a TIADC analog-to-digital converter, a digital calibration module, and a time error compensation circuit; the TIADC analog-to-digital converter comprises a multi-channel quantization circuit; the quantization circuit comprises a clock, a sampling switch, and a quantization conversion module connected in sequence; wherein one quantization circuit is a reference circuit; and the quantization circuits other than the reference circuit are circuits to be calibrated;

[0008] The clock is used to generate a frequency-divided clock;

[0009] The sampling switch is used to be turned on when triggered by the rising edge of the corresponding frequency-divided clock, thereby sampling the input data and sending the sampled data to the corresponding quantization conversion module;

[0010] The quantization conversion module is used to quantize the received sampled data to obtain a digital code value, and send the digital code value to the digital calibration module;

[0011] The digital calibration module includes a multi-channel sampling error extraction and statistics module and a process control and iteration module connected in sequence;

[0012] The multi-channel sampling error extraction and statistics module is used to process the digital code value output by the circuit to be calibrated to obtain mismatch information of the sampling switch of each circuit to be calibrated;

[0013] The process control and iteration module is used to determine the compensation code value of the corresponding circuit to be calibrated according to the mismatch information;

[0014] The time error compensation circuit is used to compensate the corresponding clock according to the compensation code value, so that the time delay from the divided clock generated by each clock to the corresponding sampling switch is equal.

[0015] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0016] The present invention provides a digital calibration circuit for TIADC sampling time error, comprising: a TIADC analog-to-digital converter, a digital calibration module, and a time error compensation circuit; the TIADC analog-to-digital converter comprises a multi-channel quantization circuit; the quantization circuit comprises a clock, a sampling switch, and a quantization conversion module connected in sequence; wherein, one quantization circuit is a reference circuit; the quantization circuits other than the reference circuit are circuits to be calibrated; the clock is used to generate a divided-frequency clock; the sampling switch is used to be turned on when triggered by the rising edge of the corresponding divided-frequency clock, thereby sampling input data and sending the sampled data to the corresponding quantization conversion module; the quantization conversion module is used to receive the received The sampled data is quantized to obtain digital code values, which are then sent to a digital calibration module. The digital calibration module includes a multi-channel sampling error extraction and statistics module and a process control and iteration module, which are connected in sequence. The multi-channel sampling error extraction and statistics module processes the digital code values output by the circuit to be calibrated to obtain mismatch information about the sampling switches of each circuit to be calibrated. The process control and iteration module determines the compensation code value for the corresponding circuit to be calibrated based on the mismatch information. The time error compensation circuit compensates the corresponding clock based on the compensation code value to equalize the time delay from the divided clock generated by each clock to the corresponding sampling switch. This invention achieves sampling time error calibration within the full bandwidth region. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0018] Figure 1 Schematic diagram of the digital calibration circuit for TIADC sampling time error provided by the present invention;

[0019] Figure 2 This is a schematic diagram of the multi-channel time interleaving principle of TIADC;

[0020] Figure 3 Schematic diagram of the multi-phase sampling clock characteristics of TIADC;

[0021] Figure 4 Schematic diagram of the mapping relationship between x[n] and y[n] before and after combining the sampling data of TIADC;

[0022] Figure 5 Schematic diagram of error extraction implementation of relevant formula A-reference Sub-ADC0 for application example;

[0023] Figure 6Schematic diagram of the time distance between ideal sampling and actual sampling;

[0024] Figure 7 Schematic diagram of error extraction implementation of relevant formula B-reference Sub-ADC0 for application example;

[0025] Figure 8 Schematic diagram of error extraction implementation of C-reference Sub-ADC0 for application example;

[0026] Figure 9 For example, the error extraction implementation diagram of the relevant formula F-reference Sub-ADC0-k fixed is shown;

[0027] Figure 10 For example, the following formula is used: F-reference Sub-ADC0-error extraction implementation diagram for different k values;

[0028] Figure 11 A schematic diagram of the process and iterative module implementation of Sub-ADC0 as an application example benchmark;

[0029] Figure 12 As an example, the FFT performance optimization results of the 8-channel TIADC formula F, k=3 before and after calibration are shown;

[0030] Figure 13 This is a diagram showing the simultaneous iterative convergence process of 7-channel calibration values for 8-channel TIADC as an example.

[0031] Figure 14 As an example, the FFT performance optimization results of the 4-channel TIADC formula D before and after k=j-1 calibration are shown;

[0032] Figure 15 As an example application, a schematic diagram of the time-sharing iterative convergence process of the calibration values of 3 channels using a 4-channel TIADC is shown;

[0033] Figure 16 For example, the following diagram shows the error extraction implementation with fixed k1 / k2 values, using the relevant formula A1-reference SubADC0;

[0034] Figure 17 Schematic diagram for error extraction based on the application example related formula D1-reference SubADC0-k1 / k2 value difference;

[0035] Figure 18 Schematic diagram of calibration implementation for error extraction algorithm formula shared by all channels;

[0036] Figure 19 As an example application, a schematic diagram of a shared error extraction implementation using 4-channel TIADC, formula B1, reference SubADC0, and fixed k1 / k2 is provided.

[0037] Figure 20 As an application example, the FFT performance optimization results of a 4-channel TIADC injected with dual tones and observed at 4 times the fs are shown;

[0038] Figure 21 As an application example, the FFT performance diagram of a 4-channel picosecond sampling error mismatch TIADC before calibration is shown.

[0039] Figure 22 As an example, the 4-channel TIADC formula C is used, and the FFT performance optimization results after k1=2 / k2=0 single-formula calibration are shown;

[0040] Figure 23 As an example, the 4-channel TIADC formula C, k1=2 / k2=0 single-formula calibration iterative convergence process diagram is shown;

[0041] Figure 24 As an example, the 4-channel TIADC formula D is used. The FFT performance optimization results after calibration of the two sub-formulas k1=2 / k2=3 are shown.

[0042] Figure 25 This is an application example showing the FFT performance optimization results of an 8-channel TIADC injected with dual tones and observed at 4 times the fs.

[0043] Figure 26 As an example, the 8-channel TIADC formula B, k1=1 / k2=0 single formula calibration results before and after the FFT performance optimization diagram;

[0044] Figure 27 As an example, the 8-channel TIADC formula B is used, and the FFT performance optimization results after calibration of the two sub-formulas k1=1 / k2=3 are shown. DETAILED DESCRIPTION

[0045] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0046] The object of the present invention is to provide a digital calibration circuit for TIADC sampling time error, so as to realize sampling time error calibration in the full bandwidth region.

[0047] In order to overcome the shortcomings of the existing technology, the present invention provides multiple TIADC sampling clock mismatch error extraction methods of the same type applicable to any number of channels, and provides a TIADC calibration scheme for any number of channels, which solves the problem of the calibration being constrained by the frequency range of the TIADC input signal and can be applied to the full bandwidth area. The present invention also reduces the complexity of the calibration process and implementation. The control logic from error extraction to compensation in the present invention is scalable to any channel, the reference benchmark can be arbitrarily selected, the digital implementation complexity is low, and the calibration of the TIADC is ultimately achieved with low resources. The sampling error extraction scheme of the two-formula combination can solve the problem of the calibration being constrained by the frequency range of the TIADC input signal and can be applied to any Nyquist zone, or even across the Nyquist zone. The present invention is very suitable for background tracking and calibration of TIADC analog devices that change with PVT.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] like Figure 1 As shown, the digital calibration circuit for TIADC sampling time error provided by the present invention includes: a TIADC analog-to-digital converter, a digital calibration module and a time error compensation circuit; the TIADC analog-to-digital converter includes multiple quantization circuits; the quantization circuits include a clock, a sampling switch and a quantization conversion module connected in sequence; wherein, one quantization circuit is a reference circuit; and the quantization circuits other than the reference circuit are circuits to be calibrated.

[0050] The clock is used to generate a frequency-divided clock.

[0051] The sampling switch is used to be turned on when triggered by the rising edge of the corresponding frequency-divided clock, so as to sample the input data and send the sampled data to the corresponding quantization conversion module.

[0052] The quantization conversion module is used to quantize the received sampling data to obtain a digital code value, and send the digital code value to the digital calibration module.

[0053] In practical applications, the digital calibration circuit for TIADC sampling time error of the present invention comprises a TIADC analog-to-digital converter, a digital calibration module, and a time error compensation circuit. Based on the TIADC hybrid digital-analog calibration scheme, the present invention proposes two core digital modules for digital sampling error calibration: an arbitrary multi-channel sampling error extraction and statistics module, and a process control and iteration module. These two modules of the present invention are suitable for hybrid digital-analog calibration schemes. The scope of protection of the present invention is not limited to hybrid digital-analog calibration schemes but also includes fully digital calibration schemes.

[0054] The TIADC digital-to-analog converter of the present invention is constructed in detail as follows: Figure 2 As shown, there are M sampling (S / H) channel sub-ADCs and data combiners. Figure 3 As shown, the clocks for the M-way ADCs are generated by multiple clocks of the total CLK, named CLK_PH j (where j = 1, 2, ..., M), its CLK_PH2 is delayed by one CLK cycle time T compared to CLK_PH1, ...., CLK_PH of M paths M Compared to CLK_PH M-1 Delay one CLK cycle time T, CLK_PH1 compared to CLK_PH M Delay one CLK cycle time T, ..... The M-way TIADC is triggered by the rising edge of multiple clocks CLK_PH to control the S / H switch module to turn on, and the input signal X(t) analog signal is sampled in turn, and then quantized by the Sub-ADC. j The output data stream is {…, y j [n-2], y j [n-1], y j [n],y j [n+1],y j [n+2], ...}, where j = 1 / 2 / ...M. The digital code values quantized by the M-channel TIADC are y1[n], y2[n], ..., y m [n] (where n = ..., -2, -1, 0, 1, ... time axis), the data combining MUX selector is equivalent to combining M parallel data into serial data, and finally TIADC outputs the combined data stream of x[n], as detailed in Figure 4 As shown in the figure, TIADC performs high-speed quantization every T time interval, and each Sub-ADC j The quantization time interval is MT, which achieves a method of keeping the rate of a single ADC unchanged but increasing the rate of the overall TIADC by M times.

[0055] The digital calibration module includes a multi-channel sampling error extraction and statistics module and a process control and iteration module which are connected in sequence.

[0056] The multi-channel sampling error extraction and statistics module is used to process the digital code value output by the circuit to be calibrated to obtain mismatch information of each sampling switch of the circuit to be calibrated.

[0057] In practical applications, the sampling error extraction and statistics module of the M channel converts the M-channel data y1[n], y2[n], ..., y m[n] (where n = ..., -2, -1, 0, 1, ... time axis) is processed by digital operations on multiple channels, and then a certain amount of data is statistically averaged to obtain the clock CLK_PH of each sampling switch. j (j=1 / 2 / … / M) mismatch information ΔE, its M channel Sub-ADC2 to Sub-ADC m The sampling time mismatch error ΔE is sequentially instantiated as ΔE2 / ΔE3 / … / ΔE m The present invention proposes a method for digitally extracting sampling errors, the core of which is mathematical operation processing, which will be described in detail later.

[0058] The process control and iteration module is used to determine the corresponding compensation code value of the circuit to be calibrated according to the mismatch information.

[0059] In practical applications, the source of TIADC sampling switch mismatch is multiple clocks CLK_PH j The precise sampling time interval between the two is not the ideal period T, so the industry often uses two methods to compensate for the sampling error of TIADC: compensation modules such as derivative filters in the digital domain are used for compensation, which is called a full digital calibration solution; multiple clocks CLK_PH in the analog domain are used for compensation. j (j=1 / 2 / … / M) to adjust the delay and realize the fundamental correction of the sampling time interval, which is called the digital-analog hybrid solution. , which is not linearly proportional to the actual compensation code value C, so the calibration needs to add a process control and iteration module to search for the optimal compensation code value C. m The compensation code value C is instantiated as C2 / C3 / … / C m . Iterative function implementation The optimal match search to the compensation code value C requires a certain digital process to ensure the optimal value search process of C for each channel. The sampling error extraction method is strongly related to the iteration module and is also the core module of the calibration. The present invention has a detailed implementation description of this module.

[0060] The time error compensation circuit is used to perform compensation in the corresponding equation according to the compensation code value, so that the time delay from the divided clock generated by each clock to the corresponding sampling switch is equal.

[0061] In practical applications, such as Figure 1 As shown, the compensation code value of the M channel is C2 / C3 / … / C m The delay adjustment circuit of the analog circuit, that is, the time error compensation circuit, is sent in sequence to make the divided clock CLK_PH generated by the multiple clocks of all sub-channels j To the Sub-ADC jThe delay of the SH module circuit (sampling switch) is consistent, that is, its CLK_PH j The sampling time interval between them is fixed to an ideal T, and finally an analog-to-digital hybrid calibration scheme is realized, where j=1 / 2 / … / M.

[0062] As an optional implementation, the digital calibration circuit for TIADC sampling time error provided by the present invention further includes a digital combining module; the digital combining module is connected to each of the quantization circuits; the digital combining module is used to combine all the digital code values.

[0063] The principle of the digital calibration circuit for TIADC sampling time error of the present invention is described below based on specific embodiments. Example

[0064] 1. The implementation of the sampling error extraction and statistics module for any multiple channels in this embodiment is described.

[0065] The TIADC quantized input data of the M channel to this module has the following characteristics: m The sampling interval between y1[n] and y2[n] is T, the sampling interval between y1[n] and y2[n] is T, ..., y m The sampling interval between y[n] and y1[n+1] is T, y m [n-1] and y m The sampling interval of y1[n] is MT, ..., the sampling interval of y1[n] and y1[n+1] is MT. Usually, the digital clock is the accompanying clock of a single Sub-ADC (the cycle time is MT). y1[n+1] is the output of y1[n] after a digital clock beat delay, where n is a time axis equal to ..., -2, -1, 0, 1, ...

[0066] When used for M-channel TIADC error extraction, assuming that Sub-ADC1 is selected as the reference circuit (uncalibrated), a sampling error extraction formula based on the correlation principle is expressed as follows:

[0067] Sampling delay error of Sub-ADC2 channel: .

[0068] Sampling delay error of Sub-ADC3 channel: .

[0069] …….

[0070] Sub-ADC m Channel sampling delay error: .

[0071] Sub-ADC2 to Sub-ADC mThe formula is implemented in detail in the digital circuit as Figure 5 As shown, A register that delays a digital clock. The sampling delay error of each Sub-ADC channel is the difference between the previous data and the next data, which is then multiplied by the current channel number to obtain the relevant value data stream. Finally, the relevant value data stream is accumulated for a time window and the average output error is calculated. It can be summarized that for any sub-channel Sub-ADC, the universal sampling error extraction formula is based on the time axis representation of x[n]:

[0072] Formula A.

[0073] Its n=…, -2, -1, 0, 1, ... time axis, the theoretical sampling time distance between x[n-1] and x[n] is T, and the theoretical sampling time distance between x[n] and x[n+1] is T. Error extraction formula A is a general and universal formula based on the extraction of any one of the M-way TIADC. Figure 4 The figure shows that x[n] with the time axis applied has been mapped to y1[n]. In theory, x[n] can be mapped to any sub-channel. The patent protection is not limited to all channels, but to each channel extraction method.

[0074] The mechanism of the related calibration formula A is as follows Figure 6 As shown: T1à the time distance between the moment before sampling x[n-1] and the current sampling x[n]; T2à the time distance between the moment after sampling x[n+1] and the current sampling x[n]; the dotted line is the ideal sampling time; when there are only two sampling time distances T1=T2, the output correlation error Therefore, the correlation extraction formula A can be extended to any number of TIADC channels. When the number of channels M is determined, the total number of sampling time deviations is M: T1, T2, T3, ... T m , currently select Sub-ADC0 as the benchmark (sampling multi-phase clock CLK_PH1 is not adjusted), then T1+T2+T3+…+T m =M×T, so the sampling time deviation adjustment of M-1 channels can always achieve T1=T2=T3=…=T m =T calibration adjustment, that is, the sampling time error is calibrated. Therefore, the relevant formula A does not depend on the reference selection. For example, changing the reference to Sub-ADC m , then the related formula A is rewritten as follows:

[0075] Sampling delay error of Sub-ADC1 channel: .

[0076] Sampling delay error of Sub-ADC2 channel: .

[0077] …….

[0078] Sub-ADC m-1 Channel sampling delay error: .

[0079] The present invention protects the expanded application of the relevant formula A benchmark change.

[0080] The second related formula characterization of the sampling time deviation extraction protected by the present invention and its implementation application are as follows:

[0081] Formula B.

[0082] On the time axis, n = ..., -2, -1, 0, 1, ..., the theoretical sampling time distance between x[n-1] and x[n] is T, and the theoretical sampling time distance between x[n] and x[n+1] is T.

[0083] Usually the TIADC quantized signal x[n] is a wide-sense stationary random signal. , so the expanded calculation of formula B is:

[0084] .

[0085] Derivation and expansion explain the relationship between formula B and formula A The difference is 2 times, that is, the effect of extracting sampling error is equivalent. The error extraction implementation of formula B applicable to the M-channel TIADC is shown in Figure 7 As shown, similarly, the formula B does not depend on the benchmark selection, and the present invention protects the expanded application of the benchmark change of the relevant formula B.

[0086] Compared with the correlation calculation of formula B, which requires square processing and consumes digital implementation resources, the third correlation formula for sampling time deviation extraction protected by the present invention is characterized and implemented as follows:

[0087] Formula C.

[0088] On the time axis, n = ..., -2, -1, 0, 1, ..., the theoretical sampling time distance between x[n-1] and x[n] is T, and the theoretical sampling time distance between x[n] and x[n+1] is T.

[0089] Formula C uses absolute value to significantly reduce digital design cost and does not use multiplier resources. The error extraction implementation of Formula C for TIADC with M channels is shown in Figure 8 As shown, abs is the absolute value operation. Similarly, the formula C does not depend on the benchmark selection. The patent protects the expansion and application of the benchmark change of the relevant formula C.

[0090] The three processing algorithms A, B, and C used for sampling error extraction and statistics have the same characteristics. j of The formulas derived from the previous and next beat data (sampling time interval T) and the current channel data are called the 1T spacing sampling error extraction formula, where j = 1 / 2 / 3…M. The actual 1T spacing TIADC sampling time error extraction is only a special case. This paper proposes a multi-T spacing sampling error extraction implementation, namely the general expressions of the three detailed expansions of formulas A, B, and C are as follows:

[0091] Formula D.

[0092] Formula E.

[0093] Formula F.

[0094] Where x[n] is the digital code value at the current time n; x[nk] is the digital code value at the time nk; k is the number of sampling cycles; x[n+k] is the digital code value at the time n+k; E is the expected mathematical statistics of a piece of data; and ΔE is the mismatch information of the sampling switch.

[0095] In formula D / E / F, k=...-3, -2, -1, 1, 2, 3..., a non-zero integer, and k≠a multiple of M, where M is the number of sampling channels of the TIADC, and n=..., -2, -1, 0, 1,..., on the time axis. The theoretical sampling time distance between x[nk] and x[n] is k×T, and the theoretical sampling time distance between x[n] and x[n+k] is k×T.

[0096] The error extraction implementation of formula D / E / F for TIADC with M channels is similar to that of A / B / C. The present invention implements formula F in detail, and all sub-channels use a detailed digital implementation scheme with k=3, see Figure 9 In addition, the present invention applies a detailed digital implementation scheme of the channel differentiation k parameter of Formula F, setting its Sub-ADC j k=j-1 (j=1 / 2 / 3…M), see Figure 10 The implementation block diagram is shown in the figure. Please refer to the following instantiation formula for specific implementation:

[0097] Sampling delay error of Sub-ADC2 channel: .

[0098] Sampling delay error of Sub-ADC3 channel: .

[0099] …….

[0100] Sampling delay error of Sub-ADCm channel: .

[0101] The k values of the instantiated M sub-channels can be different for each channel or the same, and can both be used to extract error information of the sampling clock.

[0102] Similarly, the three formulas D / E / F do not rely on the selection of the benchmark, and the patent protects the expansion and application of the benchmark changes of the relevant formulas D / E / F.

[0103] In summary, the above formulas A / B / C are subsets of formulas D / E / F with all k=1. The present invention proposes a multi-T time interval error extraction scheme that is applicable to variable references and can be extended to TIADCs with any M channels. It can also resolve the problem of calibration error extraction being constrained by the TIADC input frequency.

[0104] 2. Description of the implementation of the process control and iteration modules in this embodiment.

[0105] TIADC calibration value of the M channel: The analog circuit compensation code corresponding to the compensation of each Sub-ADCj is C j , adjustable CLK_PH j The sampling delay of the clock (where j = 1 / 2 / 3…M), that is, the compensation of Sub-ADC2 corresponds to C2, …, and the compensation of Sub-ADCM corresponds to C M .

[0106] The present invention provides an iterative method for analog compensation of any channel based on the error extraction scheme of multi-T time interval, Sub-ADC j The iterative formula is:

[0107] .

[0108] in, The mismatch information (error extraction and statistical output value) of the sampled switches of the jth circuit to be calibrated in the tth iteration; is the compensation code value used in the tth round iteration (the compensation value used in the current round), The iteration compensation code value used in the t+1th iteration (the iteration compensation value used in the next round); is the adjustment step factor for each iteration, sign is the symbol value of the data, where j=1 / 2 / 3…M, but j is not the reference path. The reference path of this module needs to be consistent with that selected by the error extraction module.

[0109] The present invention implements an iterative implementation based on the specific application of the iterative formula with a reference of Sub-ADC1, as shown in Figure 11 As shown, the compensation values of the non-reference roads can be updated iteratively at the same time, i.e., C2, C3, ..., Cm All are based on their own statistical ΔE2, ΔE3, ..., ΔE m Perform iterative adjustments at the same time. Figure 11 Each channel can also be refreshed independently in time-sharing iterations. For example, independent step-by-step refresh: the benchmark is Sub-ADC1, and the first round of statistics is ΔE2, ΔE3, ..., ΔE m Only the C2 value of Sub-ADC2 is adjusted, and the other calibration values remain unchanged; the second round of statistics ΔE2, ΔE3, ..., ΔE m Only the C3 value of Sub-ADC3 is adjusted, and the other calibration values remain unchanged; ...; In the M-1 round, ΔE2, ΔE3, ..., ΔE m Value, only adjust Sub-ADC m C m The rest of the calibration values are kept; in the Mth round, ΔE2, ΔE3, ..., ΔE m Only the C2 value of Sub-ADC2 is adjusted, and the other calibration values remain unchanged; ... In the 2M-2 round, ΔE2, ΔE3, ..., ΔE m value, only adjust the C of Sub-ADCm m The remaining calibration values are maintained, allowing for real-time, continuous, adaptive, and iterative tracking. Furthermore, the above two iterative formulas are also suitable for refreshing the digital compensation coefficients for full digital compensation. The present invention protects but is not limited to the above example implementation process; the iterative adjustment sequence can be expanded and applied to a wider range of applications as long as it complies with the iterative formula.

[0110] The example shows an M=8-channel TIADC with sampling bias. The error extraction method uses the relevant formula F, the benchmark Sub-ADC0, and the k=3 multi-T spacing. The calibration iteration process uses a 7-way simultaneous iteration method and injects a single tone fin / fs=0.47. The FFT performance optimization before and after calibration is as follows: Figure 12 As shown in the figure, the calibration error and calibration value iterative convergence process of 7 channels are as follows: Figure 13 shown.

[0111] The TIADC with M=4 channels has sampling deviation. Using the relevant formula D, the benchmark Sub-ADC0, Sub-ADC j The error extraction method of multi-T spacing with k=j-1 (j=1 / 2 / 3...M) is used. The calibration iteration process adopts a 3-way time-sharing iteration method, injects a single tone fin / fs=0.18, and optimizes the FFT performance before and after calibration. Figure 14 As shown, the three-channel calibration error and calibration value iterative convergence process are as follows: Figure 15 shown. Example

[0112] 1. This embodiment describes the implementation of the sampling error extraction and statistics module for any multiple channels.

[0113] The TIADC quantized input data of the M channel to this module has the following characteristics: m The sampling interval between y1[n-1] and y1[n] is T, the sampling interval between y1[n] and y2[n] is T, ..., y m The sampling interval between y[n] and y1[n+1] is T. Therefore, y m [n-1] and y m The sampling interval of y1[n] is MT, …, the sampling interval of y1[n] and y1[n+1] is MT. Usually the digital clock is the accompanying clock of a single Sub-ADC (the cycle time is MT), then y1[n+1] is the output of y1[n] after a digital clock beat delay, where n = …, -2, -1, 0, 1, …time axis.

[0114] Usually, the M-channel TIADC error extraction module is based on the calculation and statistical acquisition of the relevant mathematical formula between the data. The present invention mainly improves the scheme based on this type of relevant formula. Based on the time axis representation of any sub-path x[n] (see Figure 4 The example shown is =x[n] time axis characteristics) its general sampling error extraction formula is as follows:

[0115] Formula A1.

[0116] Its n=…, -2, -1, 0, 1, ... time axis; x[n] can be the data of any channel; x[n-1] is the data before the adjacent data of x[n], and the sampling time distance is theoretically T; x[n+2] is the data after the two adjacent data of x[n], and the sampling time distance is theoretically 2T; ΔE(n) is the sampling time error common to each sub-channel; E{*} is its mathematical statistical expectation, that is, the mathematical average value of a data stream.

[0117] Assuming that Sub-ADC1 is selected as the reference channel (uncalibrated), the sampling error extraction formula for each sub-channel of the M TIADCs implemented according to Formula A is expressed as follows:

[0118] Sampling delay error of Sub-ADC2 channel: .

[0119] Sampling delay error of Sub-ADC3 channel: .

[0120] …….

[0121] Sub-ADC j Channel sampling delay error: .

[0122] …….

[0123] Sub-ADC m Channel sampling delay error: .

[0124] Sub-ADC2 to Sub-ADC m The detailed implementation circuit of the formula is as follows Figure 6 As shown, its z -1 The digital register is a digital clock delay, which is the clock of a single sub-ADC (with a cycle time of MT). The sampling delay error extraction of each sub-ADC channel can be divided into two sets of digital correlation formulas.

[0125] The two sets of related formulas in the error extraction formula A1 can respectively realize the extraction of sampling errors. The selection of positive and negative signs in the formula can be used to avoid the problem of limited extraction of related formulas for some ADC input frequency points and frequency bands, so that the sampling time error can be extracted as much as possible, that is, the constraint on the frequency range of the TIADC input signal during calibration is resolved.

[0126] The correlation extraction formula A1 can be extended to any TIADC path and is not dependent on the reference selection. For example, the reference is changed to Sub-ADC. m , then the related formula A1 can be rewritten as follows:

[0127] Sampling delay error of Sub-ADC1 channel: .

[0128] Sampling delay error of Sub-ADC2 channel: .

[0129] …

[0130] Sub-ADC m-1 Channel sampling delay error: .

[0131] The present invention protects the expanded application of the benchmark change of the correlation formula.

[0132] Formula A for sampling error extraction and statistics of its Sub-ADC j of There are two related formulas, the first formula y j [n]·(y j-1 [n]-y j+1 [n]) are derived from the multiplication of the difference between the previous and next beat data (the sampling time distance is T) and the current channel data, which is called 1T; the following formula y j [n]·(y j-2[n]-y j+2 [n]) is derived from the difference between the two preceding and following data (sampling time interval is 2T) and the current channel data, which is called 2T. Therefore, Formula A1 is essentially a combination of multi-interval sampling error formulas, or a combination of two-equation correlation formulas. The sampling time error extraction of Formula A1 is only a special type of two-equation correlation formula combination. The present invention proposes a universal and scalable sampling error extraction formula for any sub-path x[n]:

[0133] Formula B1.

[0134] Expand formula B1 to a square formula combination:

[0135] Formula C1.

[0136] Usually x[n] is a wide-sense stationary random signal. , that is, the expected value of the average power (or autocorrelation) of a data stream of a certain length is the same whether it is observed one beat earlier or one beat later, with n = ..., -2, -1, 0, 1, ... time axis. Therefore, the expanded calculation of formula C is:

[0137] .

[0138] The derivation shows that the ΔE of formula C1 and formula B1 differ by a factor of 2, that is, the effects of the two in extracting sampling errors are equivalent.

[0139] The square of the expanded simplified formula C1 is implemented as an absolute value formula:

[0140] Formula D1.

[0141] The variable parameters k1 and k2 of the formula B1 / C1 / D1 are non-zero integers such as -2, -1, 1, 2, 3, etc., k1 Multiples of M, k2 The sampling time axis is a multiple of M, where M is the number of sampling channels of the TIADC, where n = ..., -2, -1, 0, 1, .... The theoretical sampling time distance between x[nk] and x[n] is k×T, and the theoretical sampling time distance between x[n] and x[n+k] is k×T. ΔE(n) is the sampling time error common to each sub-channel and is applicable to the protection implemented on any path.

[0142] The principle of the present invention is mainly based on the fact that a single correlation formula (sub-formula) cannot stably extract the correlation errors of all frequency bands, and even the extraction errors in some frequency bands are abnormal. Therefore, formulas B1 / C1 / D1 are composed of two sets of correlation formulas to circumvent the natural defects of error extraction. They can be applied to any Nyquist zone and even across Nyquist zones. The above formula only shows the combination of two sets of sub-formulas. In theory, more sub-formulas can be used, but the digital resources for actual implementation will increase exponentially and introduce other defects. Therefore, two sets of sub-formulas are the optimal implementation and the least complex implementation method. The core protection of this embodiment is the correlation error extraction feature of the combination of two sets of sub-formulas, including but not limited to formulas B1 / C1 / D1. Specifically, the combination of formulas in the form of adding weighted gain coefficients to each set of sub-formulas, taking absolute values, taking squares, and screening two sub-formulas is used to extract errors.

[0143] For example, formula D1 can be realized by changing the squares of two groups of sub-formulas:

[0144] Formula E1.

[0145] For example, formula B1 can be implemented by changing the weighted gain coefficients of two groups of sub-formulas:

[0146] Formula F1.

[0147] For example, formula D1 can be modified to filter out the absolute value of the two sub-formulas first, and then the maximum (minimum) value:

[0148] Formula G1.

[0149] The core of this embodiment is to extract the error by mathematically combining two sub-formulas. Similarly, it can be transformed into two different types of sub-formula combinations. For example, one is a correlation multiplication and the other is a square to achieve other free combinations, such as:

[0150] Formula H1.

[0151] The core of this embodiment is the mathematical combination of two sub-formulas to achieve error extraction. Similarly, it can be expanded to more sub-formula combinations. In principle, digitally implementing such formulas requires more resources and more complex k parameter considerations. This is not the optimal solution and is only an extended application of patent protection. For example:

[0152] Formula J1.

[0153] The core of this embodiment is to implement error extraction by mathematically combining two sub-formulas. Therefore, the two sub-formulas can be extended to the same sub-channel, but error extraction at different time n. For example:

[0154] .

[0155] in, These are four different moments of the sub-channel.

[0156] The application of the combination formula of B1 / C1 / D1 used in the present invention is applicable to all sub-channels of TIADC. Figure 16 The example application shows that k1=1 and k2=2 for each sub-channel Sub-ADCj of the M-channel TIADC, where j=1 / 2 / …M. Formula B1 / C1 / D1 can also be used for solutions where k1 and k2 values are different for each sub-channel. For detailed application examples, see Figure 17 As shown, with Sub-ADC1 as the benchmark, the error extraction scheme of formula D1 with k1=j-1 and k2=M-j+1 is implemented, where j=2 / …M:

[0157] Sampling delay error of Sub-ADC2 channel:

[0158] .

[0159] Sampling delay error of Sub-ADC3 channel:

[0160] .

[0161] …….

[0162] Sub-ADC j Channel sampling delay error:

[0163] .

[0164] …….

[0165] Sub-ADC m Channel sampling delay error:

[0166] .

[0167] The parameters k1 and k2 of the instantiated M sub-channels can be selected to be different for each channel or the same, and can be used to extract the error information of the sampling clock. The channel subscript calculation rule is: the time axis of the M (subscript m) sub-channels is patrolled in sequence, each time The j is any integer, and the subscript can be decomposed into j=p×m+q, and the remainder q must be a number between 1 and m. The decomposed p is the integer delay beat value. For example:

[0168] j=0=-1×m+m, then .

[0169] j=-1=-1×m+(m-1), then .

[0170] j=1×m+1, then .

[0171] j=-1×m+1, then .

[0172] In summary, the above A1 / E1 / F1 / G1 / H1 / J1 formulas are subsets and extensions of the B1 / C1 / D1 formulas. The present invention proposes a combination of three types of sampling error formulas to implement a sampling error extraction scheme. This scheme is applicable to variable references and can be extended to TIADCs with any M channels. It can resolve the constraint problem of calibration error extraction on the TIADC input frequency and even enable the use of ADCs across Nyquist zones.

[0173] 2. Implementation of the process control and iteration modules in this embodiment:

[0174] Definition of TIADC calibration value for M channel: Each Sub-ADC j The analog circuit compensation code corresponding to the compensation is C j , adjustable CLK_PH j The sampling delay of the clock (where j = 1 / 2 / 3...M), that is, the compensation of Sub-ADC2 corresponds to C2,..., Sub-ADC M The compensation corresponds to C M .

[0175] Typically a single channel Sub-ADC j The calibration value iteration formula is:

[0176] .

[0177] Or the iterative formula is (applicable to full digital compensation iteration):

[0178] .

[0179] The present invention realizes sampling error extraction based on the combination of two sub-formulas, makes adaptive improvements to the iterative method, and proposes a calibration implementation scheme for multi-channel shared error extraction in detail, which improves the power consumption and area of the calibration module implementation. The implementation principle block diagram of this scheme is shown in the figure below. Figure 18 As shown in the figure, it consists of multi-channel data delay beats, 5 groups of MUX selection modules, M-channel shared sampling error extraction and single channel calibration value iteration. The core lies in selecting a general formula for error extraction. In each round, only one channel sampling error is calculated and counted, and the compensation value of the channel is adjusted. Other channels do not participate in the error extraction calculation and iterative processing.

[0180] The calibration implementation of the entire shared error extraction algorithm formula is as follows: Figure 19 As shown in the figure, the application lists M=4 TIADCs, selects formula B as the error extraction formula, selects SubADC0 as the reference, and the formula parameters of each sub-channel are fixed to k1=1 and k2=2. Then the three calibration error extraction formulas of the non-reference channel are:

[0181] .

[0182] .

[0183] .

[0184] Digital feasibility considers that all data streams are delayed by one beat (group delay does not change the formula) and is changed to:

[0185] .

[0186] .

[0187] .

[0188] 1) Perform multi-channel beat processing on the input data y1 to y4 according to the formula implementation requirements, where y1[n+1] is the data stream y1_f1 with a digital one-beat delay, y2[n+1] is the data stream y2_f1 with a digital one-beat delay, ..., y2[n+2] is the data stream y2_f2 with a digital two-beat delay.

[0189] 2) Select the corresponding input signal based on the currently pre-calibrated channel MUX. For example, when calibrating Sub-ADC2, x[n] selects y2_f1; x[n-k1] selects y1_f1; x[n+k1] selects y3_f1; x[n-k2] selects y4; and x[n+k2] selects y4_f1. Similarly, the calibration data for the remaining channels is selected using the MUX to connect to the corresponding channel.

[0190] 3) The data selected by MUX is the input data stream of x[n], x[n+k1], x[n-k1], x[n+k2], x[n-k2], and the general formula B determined by the implementation target is applied to realize its digital calculation processing, and the data of a section is accumulated and averaged to obtain ΔE2, ΔE3, and ΔE4. One-to-one correspondence with the channels selected by MUX, where j=2 / 3 / 4.

[0191] The above three steps describe the shared error extraction implementation in detail. The last step is the iteration of multi-channel calibration: the digital selector MUX selects the Sub-ADC j Get sampling time error ΔE j, for analog circuit compensation code C j Perform iterative adjustment and calibration. All channel iterative processing requires the state machine to implement the adjustment step by step. Example of iterative control process: The first round of MUX selection statistics value, adjust the Sub-ADC2 The rest of the calibration values remain unchanged; the second round of MUX selection statistics value, adjust the Sub-ADC3 The rest of the calibration values remain unchanged; ...; The M-1 round of MUX selection statistics Value, adjust Sub-ADC m of The rest of the calibration values remain unchanged; in the Mth round, MUX selects and counts value, adjust the Sub-ADC2 The rest of the calibration values remain unchanged. Value, adjust Sub-ADC m of The remaining calibration values are maintained, and calibration can achieve real-time continuous adaptive iterative tracking. This iterative method does not require the adjustment order of the sub-channels, but requires that the step factor and update speed of all iterative channels are consistent. The update rate of each channel = the total number of iterations / M.

[0192] The error extraction and detailed simulation examples of the entire calibration scheme provided above are:

[0193] The example shows a TIADC with M = 4 channels, which has picosecond sampling deviation. Using the relevant formula C1, the benchmark Sub-ADC0, k1 = 2 / k2 = 0, that is, the single-subst error extraction method, the TIADC input excitation dual tone is Fin1 / Fs = 0.68 and Fin2 / Fs = 0.8063, the input is both in the second Nyquist zone, the dual tone amplitude is the same, and the spectrum observed at 4 times the sampling rate is as follows Figure 20 As shown; the FFT performance before TIADC calibration is as follows Figure 21 As shown, the spectrum is folded back to the first Nyquist zone, and the FFT performance of the TIADC output after calibration is as follows Figure 22 As shown, the comparison shows that its spectrum is further deteriorated and the calibration is invalid; Figure 23 The left side shows that using a single minor formula does not significantly change the calibration error extraction, that is, no error can be extracted. Figure 23 The right side shows the abnormal convergence process of the calibration code value, with no convergence trend and calibration failure; Figure 24 It is shown that under the same conditions, the parameters are changed to k1=2 / k2=3 for calibration. The calibration value converges and the FFT performance shows that the sampling error spur is eliminated. That is, the use of the two minor formulas can avoid calibration failure at some uncertain frequency points.

[0194] The following example shows an M=8-channel TIADC with picosecond sampling deviation. Using formula B1, with reference to Sub-ADC0, k1=1 / k2=0, a single-element error extraction method is used. The TIADC input excitation dual tones are Fin1 / Fs=0.86 (second Nyquist zone) and Fin2 / Fs=1.0956 (third Nyquist zone). The input crosses the Nyquist zone, and the dual tones have the same amplitude. The spectrum observed at 4x the sampling rate is as follows: Figure 25 As shown; the output FFT performance of TIADC before and after calibration is as follows Figure 26 As shown, the spectrum spur cannot be eliminated after calibration, and the calibration is off; Figure 27 It shows that under the same conditions, the calibration value converges after the parameters are changed to k1=1 / k2=3, and the FFT performance shows that the sampling error spur is eliminated.

[0195] There are many similar issues involving frequency band anomalies in broadband signals, which will not be shown one by one.

[0196] This phenomenon is typically normal with single-tone calibration, but various unstable anomalies can occur during dual-tone or broadband calibration, with numerous scenarios where amplitude-frequency fluctuations can lead to sampling error extraction failures. Therefore, single-sub-item calibration has certain drawbacks, necessitating the use of a two-sub-item combination to mitigate these calibration failures. This involves resolving input signal constraints and even enabling the ADC to operate across the Nyquist interval. For many scenarios using TIADC, background tracking of ADC sampling error calibration as PVT changes is crucial. This calibration solution is particularly well-suited for scenarios with uncertain ADC input frequencies.

[0197] The digital calibration circuit for TIADC sampling time error of the present invention has the following advantages:

[0198] 1. The present invention provides a method for digitally extracting multiple sampling errors. This method provides detailed requirements for the extraction formula for each channel and provides detailed examples. Each sub-channel is relatively independent and can be applied to the TIADC of any channel. The reference channel can be flexibly and freely adjusted. The above-mentioned related error extraction methods are numerous and available. The hardware is easy to implement, the computational complexity is low, and the portability is good.

[0199] 2. The present invention provides a variety of sampling error digital extraction methods with wide universality and versatility. It can be applied to the sampling error extraction of any TIADC channel, and the k parameter value of its formula can be flexibly adjusted. The error extraction is performed in conjunction with statistical operations, which can overcome the problem that the traditional calibration algorithm is limited by the signal input frequency bandwidth and can be implemented in the entire Nyquist sampling frequency.

[0200] 3. The present invention provides three types of two-subformula combinations to implement sampling error extraction methods. The k parameter value of the two-subformula error formula can be flexibly controlled. The arithmetic combination of the two subformulas, combined with statistical operations for error extraction, can avoid scenarios where single-subformula sampling error extraction fails. This overcomes the problem that traditional calibration algorithms are limited by the signal input frequency bandwidth. Even the ADC can be used across the Nyquist interval. This method allows TIADC performance to be unrestricted by spectrum frequency points, providing a stable, reliable, and flawless solution for real-time background tracking of TIADC changes with PVT. It can almost eliminate some of the restrictions on the use of TIADC in fields such as communications and radar.

[0201] 4. The calibration iteration process of the present invention is simple. Combined with the error extraction method, it can freely choose simultaneous or time-sharing mode, without the need for a complex state machine to control the calibration sequence.

[0202] 5. The error statistics module and calibration iteration module of the present invention can be widely applied to mixed digital-analog or full digital calibration.

[0203] 6. The error statistics module and calibration iteration module of the present invention are compatible with foreground calibration and background tracking calibration, ensuring the performance consistency of TIADC under different PVTs.

[0204] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0205] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. At the same time, those skilled in the art will find that the specific implementation methods and application scopes may vary based on the concept of the present invention. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims

1. A digital calibration circuit for TIADC sampling time error, characterized in that: include: TIADC analog-to-digital converter, digital calibration module and time error compensation circuit; The TIADC analog-to-digital converter includes multiple quantization circuits; the quantization circuits include a clock, a sampling switch, and a quantization conversion module connected in sequence; wherein one quantization circuit is a reference circuit; and the quantization circuits other than the reference circuit are circuits to be calibrated; The clock is used to generate a frequency-divided clock; The sampling switch is used to be turned on when triggered by the rising edge of the corresponding frequency-divided clock, thereby sampling the input data and sending the sampled data to the corresponding quantization conversion module; The quantization conversion module is used to quantize the received sampled data to obtain a digital code value, and send the digital code value to the digital calibration module; The digital calibration module includes a multi-channel sampling error extraction and statistics module and a process control and iteration module connected in sequence; The multi-channel sampling error extraction and statistics module is used to process the digital code value output by the circuit to be calibrated to obtain mismatch information of the sampling switch of each circuit to be calibrated; The mismatch information calculation formula of the multi-channel sampling error extraction and statistics module is: ;or ; ； Wherein, x[n] is the digital code value at the current time n; x[n-k1] is the digital code value at the time n-k1; x[n+k1] is the digital code value at the time n+k1; x[n-k2] is the digital code value at the time n-k2; x[n+k2] is the digital code value at the time n+k2; E is the statistical average of the mathematical expectation; ΔE is the mismatch information of the sampling switch; k1 and k2 are non-zero integers, k1=…, -2, -1, 1, 2, 3...; k2=…, -2, -1, 1, 2, 3...; n=…, -2, -1, 0, 1,...; The process control and iteration module is used to determine the compensation code value of the corresponding circuit to be calibrated according to the mismatch information; The calculation formula of the compensation code value of the process control and iteration module is: ; in, The mismatch information of the sampled switches of the jth circuit to be calibrated is obtained in the tth iteration; is the compensation code value used in the t-th iteration, is the iteration compensation code value used in the t+1th iteration, is the adjustment step factor for each iteration, sign is the symbol value of the data; The time error compensation circuit is used to compensate the corresponding clock according to the compensation code value, so that the time delay from the divided clock generated by each clock to the corresponding sampling switch is equal.

2. The digital calibration circuit for TIADC sampling time error according to claim 1, wherein: It also includes a digital combining module; the digital combining module is connected to each of the quantization circuits; the digital combining module is used to combine all the digital code values.

3. The digital calibration circuit for TIADC sampling time error according to claim 1, wherein: The mismatch information calculation formula of the multi-channel sampling error extraction and statistics module is: ; Wherein, x[n] is the digital code value at the current time n; x[nk] is the digital code value at the time nk; k is the number of sampling cycles; x[n+k] is the digital code value at the time n+k; E is the statistical average of the mathematical expectation; ΔE is the mismatch information of the sampling switch.

4. The digital calibration circuit for TIADC sampling time error according to claim 1, wherein: The mismatch information calculation formula of the multi-channel sampling error extraction and statistics module is: ; Among them, x[n] is the digital code value at the current time n; x[nk] is the digital code value at the time nk; k is the number of sampling cycles; x[n+k] is the digital code value at the time n+k; E is the statistical average of the mathematical expectation; ΔE is the mismatch information of the sampling switch.

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