An N-bit capacitive digital-to-analog converter

Abstract

The present invention belongs to the technical field of analog-digital hybrid integrated circuits, and specifically relates to an N-bit capacitive digital-to-analog converter, which is applicable to multiple voltage domains. Based on the root-mean-square quantization noise formula within the Nyquist bandwidth, for an ADC with the same precision, the quantization noise is larger when the input voltage range is larger. Therefore, by introducing a dual voltage domain, the input voltage range is increased, and the quantization noise is increased without further improving the performance of the comparator to meet the comparison requirements. The comparator and the SAR logic part still adopt a low voltage domain to meet the high-speed design requirements, making the analog-to-digital converter more conducive to the current development needs of the industry.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-digital hybrid integrated circuits, and specifically relates to an N-bit capacitive digital-to-analog converter, which is applicable to multiple voltage domains. Background Art

[0002] With the progress of science and technology and the rapid development of fields such as medical measurement and wireless communication, the performance of analog-to-digital converters, which serve as the bridge between analog signals and digital signals, has become increasingly important. Classified by structure, analog-to-digital converters can be roughly divided into several categories such as Flash analog-to-digital converters (Flash ADC), successive approximation analog-to-digital converters (SAR ADC), pipelined analog-to-digital converters (Pipeline ADC), Sigma-Delta analog-to-digital converters (Sigma-delta ADC), etc. The traditional successive approximation analog-to-digital converter is more widely used in high-speed fields.

[0003] In the quantization process of the traditional successive approximation analog-to-digital converter, a capacitive analog-to-digital converter (CDAC) compares the reference voltage established under the control of SAR logic with the sampled input voltage. The SAR control logic controls the switching of the DAC array switches according to the comparison result, compares the newly established reference voltage again, and repeats the above steps. Finally, the reference voltage generated by the DAC array is gradually approximated to the input voltage.

[0004] With the progress of the process technology and the reduction of MOS transistor size, more and more designs adopt a low voltage domain to improve the circuit speed, reduce the circuit area and power consumption. In traditional designs, for an ADC with the same accuracy, the quantization noise is smaller in the low voltage domain. Therefore, for a comparator, it is required to distinguish a smaller voltage difference to achieve the corresponding accuracy. However, in circuit design, due to factors such as the process, the offset and noise of the comparator cannot be eliminated, and it is difficult for the comparator to meet the required accuracy. Therefore, if the requirements of high-speed and high-precision ADC can be achieved without improving the performance of the comparator, it will be more conducive to the current development needs of the industry. Summary of the Invention

[0005] Aiming at the above problems or deficiencies, the present invention provides an N-bit capacitive digital-to-analog converter. By introducing a dual voltage domain, the input voltage range is increased, and the quantization noise is increased without further improving the performance of the comparator to meet the comparison requirements. The comparator and the SAR logic part still adopt the low voltage domain to meet the high-speed design requirements.

[0006] An N-bit capacitive digital-to-analog converter (such as Figure 1As shown, it includes two parts of circuits: a high-voltage domain and a low-voltage domain. The high-voltage domain circuit part includes an M-bit Flash ADC and the high-M-bit switched capacitors of the CDAC. The low-voltage domain circuit part includes all the remaining switched capacitors except the high-M-bit switched capacitors in the CDAC, a comparator, and a SAR logic part. V REFH is the reference voltage of the high-voltage domain, V REFL is the reference voltage of the low-voltage domain, V GND is the ground signal, V IN is the input signal, and its input range is 0 to V REFH .

[0007] The CDAC mentioned above includes N quantization capacitors C1 - C N , a compensation capacitor C0, and an upper-plate grounded switch S G , with a total of N + 1 capacitors; each capacitor C i corresponds to a three-way switch S i , where i takes values from 0 to N; among them, C0 = C1.

[0008] In the high-voltage domain circuit structure, the lower plate of the first-bit quantization capacitor C N is connected to the three-way switch S N , and the three inputs of the three-way switch S N are respectively connected to V IN , V REFH , and V GND , and its control signal is provided by the M-bit Flash ADC; the lower plate of the second-bit quantization capacitor C N-1 is connected to the three-way switch S N-1 , and the three inputs of the three-way switch S N-1 are respectively connected to V IN , V REFH , and V GND , and its control signal is provided by the M-bit Flash ADC; and so on, the lower plate of the M-bit quantization capacitor C N-M+1 is connected to the three-way switch S N-M+1 , and the three inputs of the three-way switch S N-M+1 are respectively connected to V IN , V REFH , and V GND , and its control signal is provided by the M-bit Flash ADC.

[0009] In the low-voltage domain circuit structure, the lower plate of the (M + 1)-bit quantization capacitor C N-M is connected to the three-way switch S N-M , and the three inputs of the three-way switch S N-M are respectively connected to V IN , V REFL , and V GND, whose control signal is provided by the SAR logic; the lower plate of the M+2th quantization capacitor C N-M-1 is connected to the three-way switch S N-M-1 , and the three-way switch S N-M-1 has three input terminals respectively connected to V IN , V REFL and V GND , whose control signal is provided by the SAR logic; and so on, the lower plate of the Nth quantization capacitor C1 is connected to the three-way switch S1, and the three input terminals of the three-way switch S1 are respectively connected to V IN , V REFL and V GND , whose control signal is provided by the SAR logic. The lower plate of the compensation capacitor C0 is connected to the three-way switch S0, and the three input terminals of the three-way switch S0 are respectively connected to V IN , V REFL and V GND , whose control signal is provided by the SAR logic.

[0010] Except for being connected to the grounding switch S G , the upper plates of all capacitors are also connected to the positive input terminal of the comparator and transmitted to the comparator after the voltage signal is established. The negative input terminal of the comparator is connected to V GND , and the output terminal is connected to the SAR logic module.

[0011] Furthermore, the values of the remaining quantization capacitors other than C0 and C1 in the CDAC are selected according to specific designs, and binary values or non-binary forms are adopted.

[0012] For the above N-bit capacitive digital-to-analog converter, its switch control logic is as follows:

[0013] 1. In the sampling stage, the lower plates of all capacitors C N to C0 in the CDAC are connected to the input signal V IN through the three-way switch, and the upper plates are connected to V G through the grounding switch S GND , and the input signal V IN is sampled through the capacitor, and the charge is stored on the upper plate. In the sampling stage, the M-bit Flash ADC samples the input signal V IN at the same time, and completes the quantization of the high M bits of the input signal within the sampling stage, and provides the quantization results of the high M bits to the three-way switches S N to S N-M+1 of the high M-bit capacitors in the CDAC as their control signals.

[0014] 2. According to the quantization results of the high M bits of the input signal V IN in the sampling stage, if the quantization result is '1', control the input terminals of the three-way switches S N to S N-M+1 to be connected to VREFH ; If the quantization result is '0', control the three - way switch S N ~S N-M+1 's input terminal is connected to V GND . For the remaining three - way switches S N-M ~S0, the control signals are provided by the SAR logic and are all connected to V GND after sampling is completed, and the grounding switch S G is disconnected.

[0015] 3. After completing the switching of the high M - bit switches S N ~S N-M+1 , start the quantization of the low N - M bits. During the low - bit quantization process, the potential of the input terminals of the three - way switches S N ~S N-M+1 remains unchanged.

[0016] Quantize the (M + 1)-th bit. First, connect the input terminal of the three - way switch S N-M to V REFL , connect the input terminals of the three - way switches S N-M-1 ~S0 to V GND . After the voltage on the upper plate of the CDAC is established when the switches are switched, the comparator compares the voltage V P on the upper plate of the CDAC with V GND . According to the comparison result, determine whether the lower plate of the quantization capacitor C N-M of the (M + 1)-th bit is connected to V REFL or V GND . If V P >V GND , connect the input terminal of the three - way switch S N-M to V GND ; if V P <V GND , connect the input terminal of the three - way switch S N-M to V REFL . After the three - way switch S N-M is switched, complete the quantization process of the (M + 1)-th bit and obtain the corresponding quantization result.

[0017] Quantize the (M + 2)-th bit. Connect the input terminal of the three - way switch S N-M-1 to V REFL , connect the input terminals of the three - way switches S N-M-2 ~S0 to V GND , and connect the three - way switch S N-M according to the previous quantization result (the (M + 1)-th bit) to V REFL or V GND . After the voltage on the upper plate of the CDAC is established when the switches are switched, the comparator compares the voltage V P on the upper plate of the CDAC with V GNDCompare, and based on the comparison result, determine whether the lower plate of the quantization capacitor C at the (M + 2)-th bit is connected to V N-M-1 or V REFL or V GND . If V P > V GND , connect the input terminal of the three-way switch S N-M-1 to V GND ; if V P < V GND , connect the input terminal of the three-way switch S N-M-1 to V REFL . After the three-way switch S N-M-1 switches, complete the quantization process of the (M + 2)-th bit and obtain the corresponding quantization result.

[0018] And so on, for the N-th bit quantization, connect the input terminal of the three-way switch S1 to V REFL , connect the input terminal of the three-way switch S0 to V GND , and connect the three-way switches S N-M ~S2 to V REFL or V GND according to the previous quantization results. After the upper plate voltage of the switched capacitor digital-to-analog converter (CDAC) is established after the switch is switched, the comparator compares the upper plate voltage V P of the CDAC with V GND , and based on the comparison result, determine whether the lower plate of the quantization capacitor C1 at the N-th bit is connected to V REFL or V GND . If V P > V GND , connect the input terminal of the three-way switch S1 to V GND ; if V P < V GND , connect the input of the three-way switch S1 to V REFL . After the three-way switch S1 is switched, complete the quantization process of the N-th bit and obtain the corresponding quantization result.

[0019] 4. After the quantization of the low N - M bits is completed, combined with the high M-bit quantization result of the M-bit Flash ADC, obtain the N-bit quantization result of the input signal V IN , and complete the quantization process of one sampling period.

[0020] In summary, the present invention is based on the root mean square quantization noise formula within the Nyquist bandwidth: (where ), for the ADC with the same precision, the quantization noise is larger when the input voltage range is larger; thus, by introducing a dual voltage domain, the input voltage range is increased, and the quantization noise is increased under the condition of not further improving the performance of the comparator to meet the comparison requirements, and the comparator and the successive approximation register (SAR) logic part still use the low voltage domain to meet the high-speed design requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is the circuit structure diagram of the present invention;

[0022] Figure 2 It is the circuit structure diagram of the 10-bit capacitive digital-to-analog converter in Embodiment 10. Specific embodiments

[0023] The following combines the accompanying drawings and embodiments to further elaborate on the present invention.

[0024] This embodiment is a 10-bit capacitive digital-to-analog converter, and the specific circuit is as Figure 2 shown. Among them, the switching capacitors of the upper 4 bits of the CDAC are in the V REFH = 5V voltage domain, and the remaining 7 switching capacitors are in the V REFL = 1.8V voltage domain. The specific switching method of the switching capacitors of this circuit is as follows:

[0025] 1. Sampling stage:

[0026] During sampling, the lower plates of all capacitors C 10 ~C0 in the CDAC are connected to the input signal V IN through a three-way switch, and the upper plates are connected to V G through the grounding switch S GND . At this time, the total charge stored on the upper plates of all quantization capacitors C 10 ~C0 is:

[0027] Q = -V IN *C tot

[0028] At the same time, the 4-bit Flash ADC samples and quantizes V IN . Taking the quantization result '1010' as an example. According to the quantization result, the quantization results of the 1st and 3rd bits are '1'. The lower plates of the quantization capacitors C 10 , C8 need to be connected to V REFH , and the input ends of the three-way switches S 10 , S8 are controlled to be connected to V REFH ; the quantization results of the 1st and 3rd bits are '1'. The lower plates of the quantization capacitors C9, C7 need to be connected to V GND , and the input ends of the three-way switches S9, S7 are controlled to be connected to V REFH .

[0029] 2. Pre-cutting stage:

[0030] According to the quantization results of the upper 4 bits in the sampling stage, the three-way switches S 10 , S8 are connected to V REFH , and the three-way switches S9, S7 are connected to V GND, the three - way switches S6 to S0 are connected to V GND . At this time, the charge Q' on the upper plate of the CDAC is:

[0031] Q'=(V P - V REFH )*C totpre +(V P - V GND )*(C tot - C totpre )

[0032] Among them, V P is the voltage of the upper plate of the CDAC. C totpre is the sum of the capacitance values of the high - order three capacitors connected to V REFH . In this formula, C totpre = C 10 + C8. C tot is the total capacitance value sum of the CDAC, C tot = C 10 + C9+…+C0. According to the principle of charge conservation, the voltage of the upper plate of the CDAC can be obtained as:

[0033]

[0034] Since the input range of V IN is 0 to V REFH , V IN can be expressed as the large signal V INH quantized by the high 4 bits and the small signal V INL that cannot be quantized by the high 4 bits, that is, V IN = V INH + V INL . Then take V GND = 0, and simplify the above formula to get:

[0035]

[0036] 3. Quantization stage:

[0037] Quantize the 5th bit. Connect the input end of the three - way switch S6 of the 5th - bit quantization capacitor C6 to V REFL , connect the input ends of the three - way switches S 10 , S8 to V REFH , connect the input ends of the three - way switches S9, S7, S5 to S0 to V GND , and record that the voltage of the upper plate of the CDAC becomes V P1 , and the charge on the upper plate is Q1:

[0038] Q1=(V P1 - V REFH )*C totpre +(VP1 -V REFL )*C6+(V P1 -V GND )*(C tot -C totpre -C6)

[0039] According to the principle of charge conservation and taking V GND = 0, we have:

[0040]

[0041] The comparator compares V P1 with V GND , and let the comparison result be V P1 < V GND , then C6 should be connected to V REFL , and the SAR logic output control signal connects the input terminal of the three - way switch S6 to V REFL , and the quantization result of the 5th bit is obtained as '1'.

[0042] Quantize the 6th bit. Connect the input terminal of the three - way switch S5 of the 6th - bit quantization capacitor C5 to V REFL , connect the input terminals of the three - way switches S 10 , S8 to V REFH , connect the input terminal of the three - way switch S6 to V REFL , connect the input terminals of the three - way switches S9, S7, S4 - S0 to V GND , and record that the upper - plate voltage of the CDAC becomes V P2 , and the upper - plate charge is Q2:

[0043] Q2=(V P2 -V REFH )*C totpre +(V P2 -V REFL )*(C6 + C5)

[0044] +(V P2 -V GND )*(C tot -C totpre -C6 - C5)

[0045] According to the principle of charge conservation and taking V GND = 0, we have:

[0046]

[0047] The comparator compares V P2 with V GND , and let the comparison result be V P2 > V GND , then C5 should be connected to VGND The SAR logic output control signal connects the input terminal of the three - way switch S5 to V GND to obtain the quantization result of the 6th bit as '0'.

[0048] Quantize the 7th bit. Connect the input terminal of the three - way switch S4 of the 7th - bit quantization capacitor C4 to V REFL , the input terminals of the three - way switches S 10 and S8 to V REFH , the input terminal of the three - way switch S6 to V REFL , the input terminals of the three - way switches S9, S7, S5, S3 - S0 to V GND . Denote that the upper - plate voltage of the CDAC becomes V P3 , and the upper - plate charge is Q3:

[0049] Q3=(V P3 - V REFH )*C totpre +(V P3 - V REFL )*(C6 + C4)+(V P3 - V GND )*(C tot - C totpre - C6 - C4)

[0050] According to the principle of charge conservation and taking V GND = 0, we have:

[0051]

[0052] The comparator compares V P3 with V GND . Suppose the comparison result is V P3 < V GND , then C4 should be connected to V REFL . The SAR logic output control signal connects the input terminal of the three - way switch S4 to V REFL to obtain the quantization result of the 7th bit as '1'.

[0053] Quantize the 8th bit. Connect the input terminal of the three - way switch S3 of the 8th - bit quantization capacitor C3 to V REFL , the input terminals of the three - way switches S 10 and S8 to V REFH , the input terminals of the three - way switches S6, S4 to V REFL , the input terminals of the three - way switches S9, S7, S5, S2 - S0 to V GND . Denote that the upper - plate voltage of the CDAC becomes V P4 , and the upper - plate charge is Q4:

[0054] Q4=(VP4 -V REFH )*C totpre +(V P4 -V REFL )*(C6 + C4 + C3)+(V P4 -V GND )*(C tot -C totpre -C6 - C4 - C3)

[0055] According to the principle of charge conservation and taking V GND = 0, we have:

[0056]

[0057] The comparator compares V P4 with V GND and sets the comparison result as V P4 < V GND , then C3 should be connected to V REFL , and the SAR logic output control signal connects the input terminal of the three - way switch S3 to V REFL , obtaining the quantization result of the 8th bit as '1'.

[0058] Quantize the 9th bit. Connect the input terminal of the three - way switch S2 of the 9th - bit quantization capacitor C2 to V REFL , connect the input terminals of the three - way switches S 10 , S8 to V REFH , connect the input terminals of the three - way switches S6, S4, S3 to V REFL , connect the input terminals of the three - way switches S9, S7, S5, S1~S0 to V GND , and record that the voltage of the upper plate of the CDAC becomes V P5 , and the charge of the upper plate is Q5:

[0059] Q5 = (V P5 - V REFH )*C totpre +(V P5 - V REFL )*(C6 + C4 + C3 + C2)+(V P5 - V GND )*(C tot - C totpre - C6 - C4 - C3 - C2)

[0060] According to the principle of charge conservation and taking V GND = 0, we have:

[0061]

[0062] The comparator compares V P5 with V GNDCompare them, and let the comparison result be V P5 <V GND , then C2 should be connected to V REFL , and the SAR logic output control signal connects the input terminal of the three-way switch S2 to V REFL , and the quantization result of the 9th bit is obtained as '1'.

[0063] Quantize the 10th bit, and connect the input terminal of the three-way switch S1 of the 10th-bit quantization capacitor C1 to V REFL , the three-way switch S 10 , the input terminals of S8 are connected to V REFH , the input terminals of the three-way switches S6, S4, S3, and S2 are connected to V REFL , the input terminals of the three-way switches S9, S7, S5, and S0 are connected to V GND , record that the upper plate voltage of the CDAC becomes V P6 , and the upper plate charge is Q6:

[0064] Q6 = (V P6 -V REFH )*C totpre +(V P6 -V REFL )*(C6 + C4 + C3 + C2 + C1)+(V P6 -V GND )*(C tot -C totpre -C6 - C4 - C3 - C2 - C1)

[0065] According to the principle of charge conservation and taking V GND = 0, we have:

[0066]

[0067] The comparator compares V P5 with V GND , and let the comparison result be V P5 >V GND , then C1 should be connected to V GND , and the SAR logic output control signal connects the input terminal of the three-way switch S1 to V GND , and the quantization result of the 10th bit is obtained as '0'.

[0068] 4. After the quantization stage, the quantization of the 6th to 10th bits is completed. Combining with the high 4-bit quantization result of the 4-bit Flash ADC, the 10-bit quantization result of the final input signal V IN is obtained as '1010101110'.

[0069] As can be seen from the above embodiments, based on the root mean square quantization noise formula within the Nyquist bandwidth, for an ADC with the same precision, the quantization noise is greater when the input voltage range is larger. Therefore, by introducing a dual voltage domain, the input voltage range is increased, and the quantization noise is increased without further improving the performance of the comparator to meet the comparison requirements. The comparator and the SAR logic part still use the low voltage domain to meet the high-speed design requirements, making the analog-to-digital converter more conducive to the current development needs of the industry.

Claims

1. An N-bit capacitive digital-to-analog converter, characterized in that: It includes two parts of circuits, namely a high-voltage domain and a low-voltage domain; the high-voltage domain circuit part includes an M-bit Flash ADC and the high-M-bit switched capacitors of the CDAC; the low-voltage domain circuit part includes all the remaining switched capacitors except the high-M-bit switched capacitors in the CDAC, a comparator, and a SAR logic part; V REFH is the reference voltage of the high-voltage domain, V REFL is the reference voltage of the low-voltage domain, V GND is the ground signal, V IN is the input signal, and its input range is 0 to V REFH ; The CDAC includes N quantization capacitors C1 - C N , a compensation capacitor C0, and an upper plate grounding switch S G , with a total of N + 1 capacitors; each capacitor C i corresponds to a three - way switch S i , where i takes values from 0 to N; among them, C0 = C1; In the high-voltage domain circuit structure, the first-bit quantization capacitor C N has its lower plate connected to a three-way switch S N . The three inputs of the three-way switch S N are respectively connected to V IN , V REFH , and V GND , and its control signal is provided by an M-bit Flash ADC. The second-bit quantization capacitor C N-1 has its lower plate connected to a three-way switch S N-1 . The three inputs of the three-way switch S N-1 are respectively connected to V IN , V REFH , and V GND , and its control signal is provided by an M-bit Flash ADC. And so on, the Mth-bit quantization capacitor C N-M+1 has its lower plate connected to a three-way switch S N-M+1 . The three inputs of the three-way switch S N-M+1 are respectively connected to V IN , V REFH , and V GND , and its control signal is provided by an M-bit Flash ADC. In the low-voltage domain circuit structure, the lower plate of the (M + 1)-th quantization capacitor C N-M is connected to the three-way switch S N-M . The three inputs of the three-way switch S N-M are respectively connected to V IN , V REFL and V GND . Its control signal is provided by the SAR logic. The lower plate of the (M + 2)-th quantization capacitor C N-M-1 is connected to the three-way switch S N-M-1 . The three inputs of the three-way switch S N-M-1 are respectively connected to V IN , V REFL and V GND . Its control signal is provided by the SAR logic. And so on, the lower plate of the N-th quantization capacitor C1 is connected to the three-way switch S1. The three inputs of the three-way switch S1 are respectively connected to V IN , V REFL and V GND . Its control signal is provided by the SAR logic. The lower plate of the compensation capacitor C0 is connected to the three-way switch S0. The three inputs of the three-way switch S0 are respectively connected to V IN , V REFL and V GND . Its control signal is provided by the SAR logic. The upper plates of all capacitors, except for being connected to the grounding switch S G are also connected to the positive input terminal of the comparator and are transmitted to the comparator after the voltage signal is established; the negative input terminal of the comparator is connected to V GND , and the output terminal is connected to the SAR logic module.

2. The N-bit capacitive digital-to-analog converter according to claim 1, wherein: For the remaining quantization capacitors other than the capacitors C0 and C1 in the CDAC, their values are selected according to specific designs, and binary values or non-binary forms are adopted.

3. The N-bit capacitive digital-to-analog converter according to claim 1, wherein The switch control logic is as follows: 1), In the sampling stage, the lower plates of all capacitors C N ~C0 in the CDAC are connected to the input signal V IN through a three-way switch, and the upper plates are connected to V G through the grounding switch S GND . The input signal V IN is sampled through the capacitor, and the charge is stored on the upper plate. In the sampling stage, the M-bit Flash ADC simultaneously samples the input signal V IN . The quantization of the high M bits of the input signal is completed within the sampling stage, and the quantization results of the high M bits are provided to the three-way switches S N ~S N-M+1 in the CDAC for the high M-bit capacitors as its control signals; 2), according to the high M-bit quantization result of the input signal V IN : If the quantization result is 1, control the input terminals of the three-way switches S N ~S N-M+1 to be connected to V REFH ; if the quantization result is 0, control the input terminals of the three-way switches S N ~S N-M+1 to be connected to V GND ; the control signals of the remaining three-way switches S N-M ~S0 are provided by the SAR logic and are all connected to V GND after sampling is completed, and the grounding switch S G is disconnected; 3), Complete the switching of the high M-bit switches S N ~S N-M+1 After the switching, start the quantization of the low N-M bits. During the low-bit quantization process, the input terminal potentials of the three-way switches S N ~S N-M+1 remain unchanged; Quantize the (M + 1)-th bit. First, connect the input terminal of the three-way switch S N-M to V REFL , and connect the input terminals of the three-way switches S N-M-1 to S0 to V GND . After the upper plate voltage of the switched capacitor digital-to-analog converter (CDAC) is established, the comparator compares the upper plate voltage V P of the CDAC with V GND , and determines whether the lower plate of the quantization capacitor C N-M of the (M + 1)-th bit is connected to V REFL or V GND according to the comparison result. If V P > V GND , connect the input terminal of the three-way switch S N-M to V GND . If V P < V GND , connect the input terminal of the three-way switch S N-M to V REFL . After the three-way switch S N-M is switched, the quantization process of the (M + 1)-th bit is completed, and the corresponding quantization result is obtained; Quantize the (M + 2)-th bit, and connect the input terminal of the three-way switch S N-M-1 to V REFL ; connect the input terminals of the three-way switches S N-M-2 to S0 to V GND ; connect the three-way switch S N-M to V REFL or V GND according to the previous quantization result; after the establishment of the upper plate voltage of the switched capacitor digital-to-analog converter (CDAC) is completed, the comparator compares the upper plate voltage V P of the CDAC with V GND , and determines whether the lower plate of the (M + 2)-th bit quantization capacitor C N-M-1 is connected to V REFL or V GND according to the comparison result; if V P > V GND , connect the input terminal of the three-way switch S N-M-1 to V GND ; if V P < V GND , connect the input terminal of the three-way switch S N-M-1 to V REFL ; after the three-way switch S N-M-1 is switched, complete the quantization process of the (M + 2)-th bit and obtain the corresponding quantization result; And so on, quantize the Nth bit, connect the input terminal of the three - way switch S1 to V REFL , connect the input terminal of the three - way switch S0 to V GND , the three - way switches S N-M ~S2 are connected to V REFL or V GND according to the previous quantization result; after the establishment of the upper - plate voltage of the switched - capacitor digital - to - analog converter (CDAC) is completed, the comparator compares the upper - plate voltage V P of the CDAC with V GND , and judges whether the lower - plate of the quantization capacitor C1 of the Nth bit is connected to V REFL or V GND according to the comparison result; if V P >V GND , connect the input terminal of the three - way switch S1 to V GND ; if V P <V GND , the input of the three - way switch S1 is V REFL ; after the three - way switch S1 is switched, the quantization process of the Nth bit is completed, and the corresponding quantization result is obtained; 4), After the low N-M bit quantization is completed, combine the high M bit quantization result of the M bit Flash ADC to obtain the N bit quantization result of the input signal V IN to complete the quantization process of one sampling period.

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