A pixel circuit and a method for operating the pixel circuit

Abstract

The present disclosure relates to a LOFIC circuit for metal-insulator-metal MIM capacitor hysteresis correction in a pixel and an associated correction method. The pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive image charge from the photodiode. A transfer transistor is coupled between the photodiode and the floating diffusion. The transfer transistor is configured to transfer image charge from the photodiode to the floating diffusion. A reset transistor is coupled between a reset voltage and the floating diffusion. A lateral overflow integrating capacitor LOFIC network is coupled between the reset transistor and a bias voltage source. The LOFIC network includes a main LOFIC coupled between the reset transistor and the bias voltage source and a plurality of slave capacitor-switch pairs, each slave capacitor-switch pair including a slave LOFIC and a switch transistor coupled to the slave LOFIC. Each of the plurality of slave capacitor-switch pairs is coupled between the reset transistor and the bias voltage source.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to high dynamic range (HDR) complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, security cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range) through both device architecture design and image acquisition processing. The technology used to manufacture image sensors continues to develop rapidly. For example, the demand for higher resolution and lower power consumption encourages further miniaturization and integration of these devices.

[0003] A typical complementary metal oxide semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and photogenerate image charge upon absorbing the image light. The image charge photogenerated by the pixel can be measured as an analog output image signal on a column bit line that varies as a function of the incident image light. In other words, the amount of photogenerated image charge is proportional to the intensity of the image light, and the image light is read out from the column bit line as an analog signal and converted into a digital value to produce a digital image (i.e., image data) representing the external scene.

[0004] Standard image sensors have a limited dynamic range of approximately 60dB to 70dB. However, the real-world dynamic range of brightness is much greater. For example, natural scenes often span a range of 90dB or more. In order to capture details in both bright highlights and dark shadows, high dynamic range (HDR) technology is used in image sensors to increase the captured dynamic range. Summary of the invention

[0005] In one aspect, the present disclosure relates to a pixel circuit comprising: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion; a reset transistor coupled between a reset voltage and the floating diffusion; and a lateral overflow integrating capacitor (LOFIC) network coupled between the reset transistor and a bias voltage source, wherein the LOFIC network comprises: a main LOFIC coupled between the reset transistor and the bias voltage source; and a plurality of slave capacitor-switch pairs, wherein each of the plurality of slave capacitor-switch pairs comprises: a slave LOFIC; and a switching transistor coupled to the slave LOFIC, wherein each of the plurality of slave capacitor-switch pairs is coupled between the reset transistor and the bias voltage source.

[0006] In another aspect, the present invention relates to a method of operating a pixel circuit, comprising: during a first frame period - photogenerating image charge in a photodiode in response to incident light; transferring the image charge from the photodiode to a floating diffusion; transferring the overflow image charge from the photodiode to a lateral overflow integrating capacitor (LOFIC) network of the pixel circuit, wherein the LOFIC network comprises a main LOFIC and a plurality of slave capacitor-switch pairs, wherein each of the plurality of slave capacitor-switch pairs comprises a slave LOFIC and a switching transistor coupled in series to the slave LOFIC; turning on the switching transistor of a first one of the plurality of slave capacitor-switch pairs; and simultaneously turning off the switching transistors of the remaining slave capacitor-switch pairs of the plurality of slave capacitor-switch pairs. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] Figure 1 An example of an imaging system including a pixel array according to the teachings of the present disclosure is illustrated.

[0009] Figure 2 Illustrated is a schematic diagram of one example of a pixel circuit including a lateral overflow integration capacitor (LOFIC) network and a photodiode in accordance with the teachings of the present disclosure.

[0010] Figure 3A and 3BA timing diagram illustrating different frame periods of example signal values ​​in an example pixel circuit including a LOFIC network and a photodiode during idle, precharge, integration, and readout periods in accordance with the teachings of the present disclosure.

[0011] Figure 4 Illustrated is a schematic diagram of one example of a pixel circuit including a lateral overflow integration capacitor (LOFIC) network and a photodiode in accordance with the teachings of the present disclosure.

[0012] Figure 5A , 5B and 5C illustrate timing diagrams of different frame periods of example signal values ​​in an example pixel circuit including a LOFIC network and a photodiode during idle, precharge, integration, and readout periods in accordance with the teachings of the present disclosure.

[0013] Figure 6 is a flow chart illustrating a method of operating one example of a pixel circuit including a lateral overflow integration capacitor (LOFIC) network and a photodiode in accordance with the teachings of the present disclosure.

[0014] Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present disclosure. In addition, common but well-known elements that are useful or necessary in commercially feasible embodiments are generally not described in order to promote a less obstructed view of these different embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Examples are described herein for an imaging system having a pixel array including a pixel circuit, each pixel circuit having a LOFIC network that provides reduced image lag. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the examples. However, one skilled in the art will recognize that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0016] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present disclosure. Thus, appearances of the phrase "in one example" or "in one embodiment" throughout this specification are not necessarily all referring to the same example. Furthermore, in one or more examples, the particular features, structures, or characteristics may be combined in any suitable manner.

[0017] For ease of description, spatial relative terms (e.g., "below," "below," "above," "below," "above," "upper," "top," "bottom," "left," "right," "center," "middle," etc.) may be used herein to describe the relationship between an element or feature and another element or feature as illustrated in the figure. It should be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figure is rotated or flipped, the element described as being "below" or "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can encompass both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein are interpreted accordingly. In addition, it should also be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements, or one or more intermediate elements may also be present.

[0018] Throughout this specification, several technical terms are used. These terms will take their ordinary meaning in the art unless specifically defined herein or the context of their use clearly implies otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0019] As will be discussed, various examples of imaging systems are disclosed that include a pixel array having a pixel circuit, each pixel circuit having a LOFIC network configured to provide reduced image lag. It should be appreciated that a LOFIC may be included in a pixel circuit to increase the full well capacity of the pixel circuit, and thereby increase the high dynamic range capability of a corresponding image sensor. The LOFIC capacitance is positively correlated to the full well capacity. Therefore, as the capacitance of the LOFIC employed in a pixel circuit increases, the full well capacity of the pixel circuit also increases. For this reason, a higher LOFIC capacitance is generally desired. However, due to the large RC load as the capacitance of the LOFIC increases, the time required for the row driver of the imaging system to charge and / or reset the LOFIC also increases, resulting in a slower frame rate. In addition, as the capacitance of the LOFIC in the pixel circuit increases, image lag increases, which affects image quality.

[0020] It should be appreciated that image hysteresis caused by LOFIC can be associated with high dielectric constant or high-k materials included in the insulating material of metal-insulator-metal (MIM) LOFIC due to the hysteresis characteristics and slow relaxation behavior of high-k materials that require long discharge times (e.g., hundreds of milliseconds). High-k material relaxation behavior can cause image quality degradation, such as image hysteresis due to a number of mechanisms including trap-to-trap tunneling, structural relaxation, coupling to phonon energy, etc.

[0021] As will be shown in various examples below, an example pixel circuit includes a photodiode configured to photogenerate image charge in response to incident light. A floating diffusion is coupled to receive the image charge from the photodiode. In one example, a reset transistor is coupled between a bias voltage source and the floating diffusion. In another example, a reset transistor is coupled between a reset voltage source and the floating diffusion. The reset transistor is configured to be switched in response to a reset control signal.

[0022] In various instances, the pixel circuit further includes a LOFIC network that provides additional storage capacity configured to store overflow image charge for high dynamic range (HDR) image acquisition. In various instances, the LOFIC network includes a main LOFIC and two or more slave capacitor-switch pairs, each slave capacitor-switch pair including a slave LOFIC and a switching transistor coupled to the slave LOFIC. In various instances, the main LOFIC and each of the slave capacitor-switch pairs are coupled in parallel with each other. In various instances, each of the LOFICs is a metal-insulator-metal (MIM) storage capacitor including a high-k insulating region disposed between a first metal electrode and a second metal electrode. In various instances, a first metal electrode of each of the main LOFIC and the slave LOFICs is coupled to a bias voltage source, and a second metal electrode of each of the slave LOFICs is coupled to a switching transistor of the same slave capacitor-switch pair, the switching transistor being locally coupled to a reset transistor through one or more circuit elements of the pixel circuit including a floating diffusion portion of the pixel circuit. In various examples, the second metal electrode of the master LOFIC is similarly coupled to the reset transistor. In various examples, the LOFIC network includes a master switch transistor, and the second metal electrode of the master LOFIC is coupled to the master switch transistor, which is locally coupled to the reset transistor through one or more circuit elements of the pixel circuit including a floating diffusion portion of the pixel circuit. In various examples, the master LOFIC and the slave LOFIC have the same dielectric composition, the same dielectric thickness, and / or the same biasing scheme (e.g., have similar operating conditions). In various examples, the master LOFIC has a larger capacitive area than each of the slave LOFICs.

[0023] Image lag is caused by the slow discharge of residual charge in the LOFIC, which may cause the pixel circuit to be unable to keep up with the desired image sensor frame rate. If the residual charge from the previous frame is not sufficiently discharged, it will appear in the next frame, resulting in undesirable image lag and image artifacts (e.g., ghost images or lagging images). A LOFIC network according to the teachings of the present disclosure includes a slave LOFIC for sensing the residual charge accumulated in the previous frame by alternately coupling the residual charge to the rest of the pixel circuit on a frame-by-frame basis during an integration period. In one example, in each frame cycle of the image sensor, during the integration period, only a single switch of the slave capacitor-switch pair of the LOFIC network is turned on, so that one slave LOFIC is exposed simultaneously with the main LOFIC and simulates the hysteresis characteristics of the main LOFIC during that frame (e.g., the amount of residual charge accumulated and discharged in the previous one or more frames for hysteresis compensation), and at least one other slave LOFIC is operated in a discharge mode. As the image sensor continues to move to the next frame, the previously turned-on switching transistor is turned off, and at the same time a different switching transistor is turned on during the integration period. In other words, in one example, multiple switching transistors are alternately turned on, with only one of the switching transistors turned on during the integration period in a given frame, so that the slave LOFICs coupled to the simultaneously turned-off switching transistors can discharge the residual charge before the frame in which their corresponding switching transistors will be turned on. Therefore, the slave LOFICs storing charge from their active frame period have a large number of idle periods to fully relax and fully discharge before the integration period in their next active frame. The number of slave capacitor-switch pairs may depend on the desired frame rate and how long it takes for the LOFIC to fully discharge (e.g., greater than 10ms, greater than 100ms). For example, if a slave LOFIC requires 30ms to fully discharge, and a frame rate of 30 frames per second (fps) is desired (each frame lasting approximately 33ms), then the LOFIC network should have at least two slave capacitor-switch pairs. The number of slave capacitor-switch pairs may also depend on the desired level of image lag reduction, the number of frames to be considered in determining lag compensation, and / or the pixel size.

[0024] In various examples, the LOFIC network includes a main switching transistor to which the main LOFIC is coupled, thereby selectively coupling the main LOFIC to the pixel circuit. The main switching transistor can be configured to remain on during all frame periods, allowing charge to overflow from the coupled photodiode and discharge from the main LOFIC during signal readout.

[0025] In various instances, the LOFIC network does not include a switching transistor for the main LOFIC. That is, the main LOFIC is always coupled between the reset transistor and the floating diffusion. Therefore, the main LOFIC is active during each frame and does not have enough time to fully relax and fully discharge before the integration period in the next frame. Instead of discharging the residual image charge on the main LOFIC, the image lag accumulated in the main LOFIC is compensated based on the image lag accumulated in the slave LOFICs that were inactive during that frame. The pixel circuit reads out a first signal in response to the image charge from the main LOFIC and the slave LOFICs that were active during the integration period of that frame. The first signal includes a lag-free signal specific to that frame and the image lag from the main LOFIC (the slave LOFICs that were active during that frame are assumed to have no image lag). Then, during the same frame, the pixel circuit reads out a second signal in response to the image charge from all LOFICs (i.e., the main LOFIC and all slave LOFICs, whether they were active or inactive during the integration period of that frame). The second signal includes a no-lag signal specific to that frame, image lag from the master LOFIC, and various levels of image lag from the slave LOFICs that were inactive during the integration period of that frame but were active during one or more previous frames. In other words, the second signal is the first signal combined with the image lag from the inactive slave LOFIC. Thus, the pixel circuit can compensate for the image lag measured from the inactive slave LOFIC (hereinafter referred to as the "slave LOFIC lag signal") by subtracting the first signal from the second signal.

[0026] In various examples, the image lag accumulated in the capacitor is assumed to be proportional to the capacitance of the capacitor. Therefore, the image lag ratio between the master LOBIC and the slave LOBIC is assumed to be equivalent to the capacitance ratio between the master LOBIC and the slave LOBIC. If there are more than two slave LOBICs in the LOBIC network, the slave LOBIC lag signal represents the image lag from multiple slave LOBICs captured during the previous frame. The master LOBIC image lag can be compensated by scaling the slave LOBIC lag signal (e.g., by calculating the quotient by dividing the slave LOBIC lag signal by the number of inactive slave LOBICs) and then multiplying the result by the capacitance ratio (i.e., calculating the product thereof). The capacitance of a capacitor is proportional to the capacitor area and inversely proportional to the dielectric thickness. Therefore, if the master LOBIC and each of the slave LOBICs have the same dielectric composition and dielectric thickness, the capacitance ratio can be replaced by the area ratio. Using smaller slave LOBICs allows the use of smaller chips. The LOFIC network and hysteresis correction method according to the teachings of the present disclosure breaks some of the limitations on the maximum 3D or trench capacitor size (associated with hysteresis issues).The hysteresis-free signal can then be determined by subtracting the compensated primary LOFIC image hysteresis from the first signal.

[0027] For illustration purposes, Figure 1 An example of an imaging system 100 having a pixel array with pixel circuits each including a LOFIC network that provides reduced image lag according to the teachings of the present disclosure is shown. Specifically, Figure 1 1 illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and function logic 108. In one example, pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to reproduce an image of the person, place, object, etc.

[0028] In various examples, each pixel circuit 104 may include one or more photodiodes configured to photogenerate image charge in response to incident light. The image charge generated in the one or more photodiodes is transferred to a floating diffusion included in each pixel circuit 104, which may be converted into an image signal, which is then read out from each pixel circuit 104 by a readout circuit 106 through a column bit line 112. As will be discussed, in various examples, the pixel circuit 104 is also configured to provide an HDR image signal, in which case the image charge generated by the one or more photodiodes under bright lighting conditions may also be transferred to the LOFIC network and / or additional floating diffusions in each pixel circuit 104 to store the image charge. For example, each pixel circuit 104 may include a LOFIC network configured to store excess image charge overflowing from the coupled one or more photodiodes during an integration period. In various examples, the readout circuit 106 may be configured to read out the image signal through a column bit line 112. In various examples, readout circuitry 106 may include current sources, routing circuitry, and comparators that may be included in an analog-to-digital converter or other device.

[0029] In an example, the digital image data values ​​produced by the analog-to-digital converter in the readout circuitry 106 may then be received by the function logic 108. The function logic 108 may simply store the digital image data, or even manipulate the digital image data by applying post image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or other). In various examples, the function logic 108 may include circuitry or logic for performing image lag compensation (e.g., performing signal subtraction to determine a lag-free signal). The function logic 108 may be implemented in an image signal processor (ISP).

[0030] In one example, control circuit 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuit 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect such as a flash.

[0031] In one example, the imaging system 100 may be included in a digital, cellular telephone, laptop computer, endoscope, security camera, or imaging device for an automobile, etc. In addition, the imaging system 100 may be coupled to other pieces of hardware, such as a processor (general purpose or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting / strobe, electrical inputs (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other pieces of hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or process image data supplied by the imaging system 100.

[0032] Figure 2 A schematic diagram illustrating one example of a pixel circuit 204 including a LOFIC network 250 and a photodiode 214 according to the teachings of the present disclosure. It should be appreciated that Figure 2 The pixel circuit 204 may be included in Figure 1 1. An example of one of the pixel circuits 104 in the pixel array 102 shown in , and similarly named and numbered elements described above are similarly coupled and function below.

[0033] As shown in the depicted example, pixel circuit 204 includes a photodiode 214 configured to photogenerate image charge in response to incident light. In the depicted example, pixel circuit 204 also includes a first floating diffusion FD1 218 coupled to receive the image charge from photodiode 214 through transfer transistor 216. In the example, transfer transistor 216 is coupled to be controlled in response to a transfer control signal TX 246 to transfer the image charge from photodiode 214 to first floating diffusion FD1 218, such as during a readout cycle associated with pixel circuit 204. The source follower transistor 220 has a gate coupled to the first floating diffusion portion FD1 218, and the row selection transistor 222 is coupled to the source follower transistor 220, so that the source follower transistor 220 and the row selection transistor 222 are coupled between the power line PIXVDD and the bit line 212 to output an image signal from the pixel circuit 204 in response to the row selection control signal RS248 and the amount of charge at the gate of the source follower transistor 220.

[0034] exist Figure 2 , a double floating diffusion transistor 224 is coupled between a first floating diffusion FD1 218 and a second floating diffusion FD2 226. The second floating diffusion FD2 226 is coupled to a capacitor (e.g., a junction capacitor) configured to receive excess image charge overflow from the photodiode 214 through the transfer transistor 216 and the double floating diffusion transistor 224. The second floating diffusion FD2 226 is further coupled to the source of the LOFIC transistor 228. The third floating diffusion FD3 230 is coupled between the LOFIC transistor 228 and the reset transistor 232. The drain of the reset transistor 232 is coupled to the reset voltage source PIXVDD, and the source of the reset transistor 232 is coupled to the third floating diffusion FD3 230. Double floating diffusion transistor 224 is coupled to be controlled in response to double floating diffusion control signal DFD 244 , LOBIC transistor 228 is coupled to be controlled in response to LOBIC transistor control signal LOF 242 , and reset transistor 232 is coupled to be controlled in response to reset control signal RST 240 .

[0035] As shown in the depicted example, pixel circuit 204 also includes a LOFIC network 250 coupled between bias voltage source VCAP 238 and third floating diffusion FD3 230. Thus, it should be appreciated that LOFIC network 250 is selectively coupled to first floating diffusion FD1 218 through LOFIC transistor 228 and dual floating diffusion transistor 224. LOFIC network 250 is configured to receive excess image charge overflow from photodiode 214 (e.g., under bright light conditions, such as IR light or LED light).

[0036] In an example, the LOFIC network 250 includes a main LOFIC 252 and a plurality of slave capacitor-switch pairs coupled in parallel. In the illustrated embodiment, there are two slave capacitor-switch pairs. Each slave capacitor-switch pair includes a respective LOFIC 254-n and a switching transistor 256-n connected in series. The first switching transistor and the second switching transistor are coupled to be controlled in response to switch control signals SW-1 234-1 and SW-2 234-2, respectively. As will be discussed in various examples, a slave LOFIC 254-1 or 254-2 in the LOFIC network 250 that is inactive during the integration period of a frame is given sufficient time to relax and sufficiently discharge the residual charge so that during operation, by alternately coupling and decoupling the slave LOFICs 254-1 and 254-2 from the rest of the pixel circuitry on a frame-by-frame basis via the switching transistors 256-1 and 256-2, the residual charge will not have an effect on the next captured frame. For example, in each frame period of the image sensor, only one switch transistor (e.g., 256-1) of the slave capacitor-switch pair of the LOFIC network 250 is turned on during the integration period, and at the same time the other switch transistor (e.g., 256-2) is turned off. As the image sensor continues to move to the next frame, the other switch transistor (e.g., 256-2) is turned on during the integration period, and at the same time the switch transistor (e.g., 256-1) that was turned on during the previous frame is turned off. The slave LOFIC 254-n coupled to the switch transistor 256-n that is turned off during the integration period can discharge the residual charge before the frame in which its corresponding switch transistor will be turned on. Therefore, the slave LOFIC 254-n storing the charge from its active frame period has a large number of idle periods to fully relax and fully discharge before the integration period in its next active frame, thereby reducing any undesirable image lag (e.g., visible artifacts on the captured frame).

[0037] In various examples, the LOFIC network 250 may also include a main switch transistor 258 to which the main LOFIC 252 is coupled. In the depicted example, the main switch transistor 258 is coupled to be controlled in response to the main switch control signal SW-M 236 for selectively coupling the main LOFIC 252 to the third floating diffusion FD3 230 to enable an overflow path between the photodiode 214 and the main LOFIC 252. In various examples, the main switch transistor 258 may be configured to remain on during all frame periods.

[0038] In various examples, the main switching transistor 258 is not included, and therefore the main LOBIC 252 is active during each frame and does not have sufficient time to fully relax and fully discharge before the next frame. Instead of discharging the residual image charge on the main LOBIC 252, the image lag accumulated in the main LOBIC 252 is compensated based on the image lag accumulated in the slave LOBICs 254-n that were inactive during the integration period of that frame. During the idle, pre-charge (e.g., zero bias or reverse bias), and readout cycles of any frame, each of the slave LOBICs 254-n may undergo the same operations as the main LOBIC 252 to closely monitor the hysteresis behavior of the main LOBIC 252. An exemplary method of compensating for the image lag accumulated in the main LOBIC 252 is illustrated below Figure 6 middle.

[0039] In an example, each of the master LOFIC 252 and the slave LOFIC 254-n is implemented with a metal-insulator-metal (MIM) capacitor including a high dielectric or high-k insulating material disposed between a first metal electrode and a second metal electrode. In various examples, the insulating material disposed between the first metal electrode and the second metal electrode of the master LOFIC 252 and the slave LOFIC 254-n may be formed of a single layer of high-k material or a multi-layer high-k material stack. The exact composition and overall thickness of the high-k material may depend on the desired LOFIC capacitance. In various examples, the high-k material may include aluminum oxide (AhO 3 )、ZrO 2), hafnium oxide (HfO), or a combination thereof. In various examples, the master LOFIC 252 and the slave LOFICs 254-n have substantially the same size, dielectric composition, dielectric thickness, and / or biasing scheme (e.g., have similar operating conditions). In various examples, the master LOFIC 252 has a different (e.g., larger) capacitance area than each of the slave LOFICs 254-n. Using a smaller capacitance area for each of the slave LOFICs 254-n allows the slave LOFICs 254-n to occupy less space, which allows the use of a smaller chip.

[0040] In operation, bias voltage source VCAP 238 is configured to provide a bias voltage to LOFIC network 250 during precharge and readout cycles. In one example, bias voltage source VCAP 238 may have a value between 0V and 3.5V. It should be appreciated that in various examples, the voltage level of bias voltage source VCAP 238 may be determined taking into account the stability range of the high-k material. In an example, during an idle period, reset control signal RST 240 may have a value sufficient to turn on reset transistor 232 (e.g., between 2.5V and 4V), double floating diffusion control signal DFD 244 may have a high voltage value ranging between 2.5V and 4V, LOFIC transistor control signal LOF 242 may have a value of 0V to 4V, and transfer control signal TX 246 may have a value of 0V to 3V.

[0041] Figure 3A and 3B The timing diagrams of the first frame period and the second frame period respectively illustrate example signal values ​​in an example pixel circuit including a LOFIC network and a photodiode. According to the teachings of the present disclosure, each frame (i.e., Figure 3A and 3B Each of) operates in idle, precharge, integration and readout cycles. It should be understood that Figure 3A and 3B The signal depicted in the figure can be Figure 2 2. Examples of signals for controlling the operation of an example pixel circuit, such as pixel circuit 204, are depicted in FIG. 1 and similarly named and numbered elements described above are similarly coupled and function below.

[0042] Now referring to the depicted example, Figure 3A and 3B The diagram is configured to control the above Figure 2 334-1, the second switch control signal SW-2 334-2, and the bias voltage source VCAP 338 of the corresponding circuit elements discussed in detail in FIG.

[0043] At time t 1 At , the idle period of the frame period begins. Figure 3A and 3B , the reset control signal RST 340 pulses the reset transistor 232, the first switch control signal SW-1 334-1 pulses the first switch transistor 256-1, and the second switch control signal SW-2 334-2 pulses the second switch transistor 256-2 such that each of the slave LOBIC 254-n and the master LOBIC 252 receives the same bias operation (e.g., having the same bias voltage across each of the slave LOBIC 254-n and the master LOBIC 252). The bias voltage source VCAP 338 can be configured to have a low value (e.g., 0 volts) during idle periods. In various examples, the LOBIC network 250 shortens idle periods because residual charge in the slave LOBIC 254-n can be discharged during one or more complete frame periods, rather than just during idle periods.

[0044] At time t 2 At , the idle period ends and the precharge period begins. The reset control signal RST 340 pulses the reset transistor 232, and the bias voltage source 338 is pulsed. For each frame, one of the switch control signals SW-1 334-1 or SW-2 334-2 turns on the corresponding switch transistor 256-1 or 256-2 (e.g., at Figure 3A In the pre-charge cycle, the first switch control signal SW-1 334-1 is turned on) until the read cycle ends, while the other switch control signal SW-2 334-2 or SW-1 334-1 is pulsed during the pre-charge cycle (e.g., Figure 3A 2, the second switch control signal SW-2 334-2 is pulsed). Each of the slave LOBIC 254-n and the master LOBIC 252 is precharged at the same time. In various examples, each of the slave LOBIC 254-n and the master LOBIC 252 may be reverse biased during the precharge cycle to remove at least a portion of the residual charge accumulated in the previous frame.

[0045] At time t 3 At , the precharge period ends and the integration period begins. The switch control signal SW-n 334-n (eg, Figure 3A The first switch control signal SW-1 334-1 in Figure 3B The second switch control signal SW-2 334-2 in 334-2 remains on until the read cycle as described above is completed. Other control signals (e.g., Figure 3AThe second switch control signal SW-2 334-2 in Figure 3B Thus, at the same time, the master LOFIC 252 and the corresponding active slave LOFIC (e.g., Figure 3A Subordinate LOFIC 254-1, Figure 3B During the integration period, the photodiode 214 photogenerates image charge in response to incident light. The pixel circuit 204 is configured so that excess photogenerated charge can overflow from the photodiode 214 into the LOFIC network 250, through the dual floating diffusion transistor 224 and the LOFIC transistor 228 into the master LOFIC 252 and / or the active slave LOFIC (e.g., Figure 3A Subordinate LOFIC 254-1, Figure 3B 254-2) to store under strong or bright light conditions (e.g., LED light or IR light).

[0046] In one example, during the integration period, photogenerated excess image charge is configured to overflow from the photodiode 214 to the second floating diffusion FD2 226 through the dual floating diffusion transistor 224, and to overflow to the LOC network 250 through the dual floating diffusion transistor 224 and the LOC transistor 228 (e.g., overflow to and be stored in the master LOC 252 and / or active slave LOCs 254-n).

[0047] At time t 4 At , the integration period ends and the readout period begins. The bias voltage source VCAP 338 is turned on and remains on until the readout period ends. Next, a correlated double sampling (CDS) readout of the photodiode 214 occurs, during which a high conversion gain (HCG) readout of the reset value (R) from the photodiode 214 and the first floating diffusion FD1 218 occurs. Then, an HCG readout of the signal value (S) occurs.

[0048] Next, LOFIC readout of photodiode 214 occurs, during which a first signal readout of the signal value (S) occurs (eg, Figure 3A Cfd+Cfd1(S) Figure 3B254-n) during the integration period of that frame. Figure 3A The first switch control signal SW-1334-1 and Figure 3B The second switch control signal SW-2 334-2) remains on or active. Next, the switch transistor that was turned off during the integration period is turned on by the corresponding switch control signal (e.g., Figure 3A The second switch control signal SW-2 334-2 and Figure 3B The first switch control signal SW-1 334-1) is turned on. Then, a second signal readout of the signal value (S) occurs (e.g., Figure 3A and Figure 3B The second signal is output by the pixel circuit 204 in response to image charge from both the master LOFIC 252 and the first and second slave LOFICs 254 - 1 and 254 - 2 included in the LOFIC network 250 .

[0049] Next, reset control signal RST 340 pulses reset transistor 232 and a second signal readout of the reset value (R) occurs (eg, Figure 3A and 3B Then, the switch control signal (for example, Figure 3A The second switch control signal SW-2 334-2 and Figure 3B The first switch control signal SW-1 334-1) turns off the corresponding switch transistor 256-n. Then, the first signal readout of the reset value (R) occurs (for example, Figure 3A Cfd+Cfd1(R) Figure 3BIn various examples, the CDS HCG readout may be determined by finding the difference between the HCG signal value (S) and the HCG reset value (R), and the CDS LOFIC readout of the first signal or the second signal may be determined by finding the difference between the LOFIC signal value (S) and the corresponding LOFIC reset value (R). In various examples, an additional CDS readout of the photodiode 214 for medium conversion gain (MCG) readout (e.g., the reset value (R) and signal value (S) read out from the photodiode 214, the first floating diffusion FD1 218, and the second floating diffusion FD 226) may occur prior to the CDS LOFIC readout.

[0050] Next, the switch control signal (eg, Figure 3A The first switch control signal SW-1334-1 and Figure 3B The second switch control signal SW-2 334-2) will turn off the corresponding switch transistor 256-n, and the bias voltage source VCAP 338 is turned off. The timing diagram continues to move to time t 1 to proceed to the next frame.

[0051] exist Figure 2 , 3A 3B, the LOFIC network 250 includes two slave capacitor-switch pairs. Thus, the two switching transistors of the LOFIC network 250 can be alternately turned on on a frame-by-frame basis during the integration period (e.g., the first switch control signal SW-1 334-1 is turned on during the integration period of the odd-coded frames, and the second switch control signal SW-2 334-2 is turned on during the integration period of the even-numbered frames). As will be described below, in other examples, the LOFIC network 250 can have more than two slave capacitor-switch pairs.

[0052] Figure 4 A schematic diagram illustrating one example of a pixel circuit 404 including a LOFIC network 450 and a photodiode 414 according to the teachings of the present disclosure. It should be appreciated that Figure 4 The pixel circuit 404 may be included in Figure 1 1. An example of one of the pixel circuits 104 in the pixel array 102 shown in FIG. 1 and similarly named and numbered elements described above are similarly coupled and function below.

[0053] As shown in the depicted example, pixel circuit 404 includes a photodiode 414 configured to photogenerate image charge in response to incident light. In the depicted example, pixel circuit 404 also includes a first floating diffusion FD1 418 coupled to receive the image charge from photodiode 414 through transfer transistor 416. In the example, transfer transistor 416 is coupled to be controlled in response to a transfer control signal TX 446 to transfer the image charge from photodiode 414 to first floating diffusion FD1 418, for example, during a readout cycle associated with pixel circuit 404. The source follower transistor 420 has a gate coupled to the first floating diffusion portion FD1 418, and the row selection transistor 422 is coupled to the source follower transistor 420, so that the source follower transistor 420 and the row selection transistor 422 are coupled between the power line PIXVDD and the bit line 412 to output an image signal from the pixel circuit 404 in response to the row selection control signal RS 448 and the amount of charge at the gate of the source follower transistor 420.

[0054] exist Figure 4 , a double floating diffusion transistor 424 is coupled between a first floating diffusion FD1 418 and a second floating diffusion FD2 426. The second floating diffusion FD2 426 is coupled to a capacitor configured to receive excess image charge overflow from the photodiode 414 through the transfer transistor 416 and the double floating diffusion transistor 424. The second floating diffusion FD2 426 is further coupled to the source of the LOFIC transistor 428. The third floating diffusion FD3 430 is coupled between the LOFIC transistor 428 and the reset transistor 432. The drain of the reset transistor 432 is coupled to the reset voltage source PIXVDD, and the source of the reset transistor 432 is coupled to the third floating diffusion FD3 430. Double floating diffusion transistor 424 is coupled to be controlled in response to double floating diffusion control signal DFD 444 , LOBIC transistor 428 is coupled to be controlled in response to LOBIC transistor control signal LOF 442 , and reset transistor 432 is coupled to be controlled in response to reset control signal RST 440 .

[0055] As shown in the depicted example, the pixel circuit 404 also includes a LOFIC network 450 coupled between the bias voltage source VCAP 438 and the third floating diffusion FD3 430. Thus, it should be appreciated that the LOFIC network 250 is selectively coupled to the first floating diffusion FD1 418 through the LOFIC transistor 428 and the dual floating diffusion transistor 424. The LOFIC network 450 is configured to receive excess image charge overflow from the photodiode 414 (e.g., under bright light conditions, such as IR light or LED light).

[0056] In an example, the LOFIC network 450 includes a master LOFIC 452 and a plurality of slave capacitor-switch pairs coupled in parallel. Each slave capacitor-switch pair includes a respective slave LOFIC 454-1, 454-2, 454-3, 454-4, ..., 454-n and a switching transistor 456-1, 456-2, 456-3, 456-4, ..., 456-n. The switching transistors are coupled to be controlled in response to switch control signals SW-1 434-1, ..., SW-n 434-n. As will be discussed in various examples, the slave LOFICs 454-1, ..., 454-n in the LOFIC network 450 that are inactive during the integration period of the frame are given enough time to relax and fully discharge the residual charge so that during operation, by sequentially coupling and decoupling the slave LOFICs 454-1, ..., 454-n from the rest of the pixel circuitry on a frame-by-frame basis via switch transistors 456-1, ..., 456-n, the residual charge will not have an impact on the next captured frame. For example, during the integration period in each frame period of the image sensor, only one switch transistor (e.g., 456-1) of the slave capacitor-switch pair of the LOFIC network 450 is turned on. At the same time, the remaining switch transistors (e.g., 456-2, ..., 456-n) are turned off. As the image sensor continues to move to the next frame, the next switch transistor (e.g., 456-2) is turned on during the integration period, and at the same time the other switch transistors (including the switch transistors that were turned on during the previous frame (e.g., 456-1, 456-3, ..., 456-n)) are turned off. In various examples, for the (n+1)th frame period, the pixel circuit 404 loops back to turn on the first switch transistor 456-1. The slave LOFICs 454-1, ..., 454-n coupled to the switch transistors 456-1, ..., 456-n that were turned off during the integration period can discharge the residual charge before the frame in which their corresponding switch transistors will be turned on. Therefore, the slave LOFICs 454-1, ..., 454-n storing charge from their active frame period have a large number of idle periods to fully relax and fully discharge before the integration period in their next active frame, thereby reducing any undesirable image lag (e.g., visible artifacts on the captured frame).

[0057] In various examples, the number of slave capacitor-switch pairs may depend on the desired frame rate and the time required for the slave LOFIC to fully discharge (e.g., greater than 10 ms, greater than 100 ms). For example, if the slave LOFIC requires 30 ms to fully discharge, and a frame rate of 30 frames per second (fps) is desired (each frame lasting approximately 33 ms), then the LOFIC network should have at least two slave capacitor-switch pairs. The number of slave capacitor-switch pairs may also depend on the target level of hysteresis compensation. For example, two slave capacitor-switch pairs may compensate for the hysteresis charge accumulated in one previous frame. For example, three slave capacitor-switch pairs may compensate for the hysteresis charge accumulated in two previous frames (e.g., the charge accumulated in frame N-1 and frame N-2). Having N slave capacitor-switch pairs enables hysteresis correction or compensation for up to N-1 frames. However, having more slave capacitor-switch pairs may increase the reduction of image hysteresis, but should be balanced with the larger size of the semiconductor substrate required to accommodate all elements of the pixel circuit 404. Note that the residual charge accumulated in response to a bright frame will be released or discharged primarily in the next two frames, so having two slave capacitor-switch pairs may be sufficient to compensate for image lag.

[0058] In various examples, the LOFIC network 450 may also include a main switch transistor 458 to which the main LOFIC 452 is coupled, thereby selectively coupling the main LOFIC 452 to the third floating diffusion FD3 426 and controlling an overflow path between the photodiode 414 and the main LOFIC 452. In the depicted example, the main switch transistor 458 is coupled to be controlled in response to the main switch control signal SW-M 436. In various examples, the main switch transistor 458 may be configured to remain on during all frame periods.

[0059] In various examples, the main switching transistor is not included, and therefore the main LOFIC 452 is active during each frame and does not have sufficient time to fully relax and fully discharge before the next frame. Rather than discharge the residual image charge on the main LOFIC 452, the image lag accumulated in the main LOFIC 452 is compensated based on the image lag accumulated in the slave LOFICs 454-n that were inactive during the integration period of that frame. An exemplary method of compensating for the image lag accumulated in the main LOFIC 452 is illustrated below. Figure 6 middle.

[0060] In an example, each of the master LOFIC 452 and the slave LOFIC 454-n is implemented with a metal-insulator-metal (MIM) capacitor including a high dielectric or high-k insulating material disposed between a first metal electrode and a second metal electrode. In various examples, the insulating material disposed between the first metal electrode and the second metal electrode of the master LOFIC 452 and the slave LOFIC 454-n may be formed of a single layer of high-k material or a multi-layer high-k material stack. The exact composition and overall thickness of the high-k material may depend on the desired LOFIC capacitance. In various examples, the high-k material may include aluminum oxide (AhO 3 )、ZrO 2 ), hafnium oxide (HfO), or one of a combination thereof. The master LOFIC 452 and the slave LOFICs 454-n may have substantially the same size, dielectric composition, dielectric thickness, and / or biasing scheme (e.g., with similar operating conditions). In various examples, the master LOFIC 452 has a different (e.g., larger) capacitor area than each of the slave LOFICs 454-n. Using a smaller capacitor area for the slave LOFICs 454-n allows for the use of a smaller die.

[0061] In operation, bias voltage source VCAP 438 is configured to provide a bias voltage to LOFIC network 450 during precharge and readout cycles. In one example, bias voltage source VCAP 438 may have a value between 0V and 3.5V. It should be appreciated that in various examples, the voltage level of bias voltage source VCAP 438 may be determined taking into account the stability range of the high-k material. In an example, during an idle cycle, reset control signal RST 440 may have a value sufficient to turn on reset transistor 432 (e.g., between 4.5V and 4V), double floating diffusion control signal DFD 444 may have a high voltage value ranging between 2.5V and 4V, LOFIC transistor control signal LOF 442 may have a value of 0V to 4V, and transmit control signal TX 446 may have a value of 0V to 3V.

[0062] Figure 5A , 5B 5C and 5C illustrate timing diagrams of the first frame period, the second frame period, and the nth frame period of example signal values ​​in an example pixel circuit including a LOFIC network and a photodiode, respectively. According to the teachings of the present disclosure, each frame (i.e., Figure 5A , 5B and 5C) operate in idle, precharge, integration and readout cycles. It should be understood that Figure 5A , 5B and the signal depicted in 5C can be Figure 44. Examples of signals for controlling the operation of an example pixel circuit, such as pixel circuit 404, are depicted in , and similarly named and numbered elements described above are similarly coupled and function below.

[0063] Now referring to the depicted example, Figure 5A , 5B And 5C diagram instructions are configured above Figure 4 The reset control signal RST 540, the first switch control signal SW-1 534-1, the second switch control signal SW-2 534-2, the third switch control signal SW-3 534-3, the fourth switch control signal SW-4 534-4, the nth switch control signal SW-n 534-n and the bias voltage source VCAP 538 of the corresponding circuit elements discussed in detail in FIG.

[0064] At time t 1 At , the idle period of the frame period begins. Figure 5A , 5B 5C, reset control signal RST 540 pulses reset transistor 432, and all switch control signals SW-1 534-1, ..., SW-n 534-n pulse their corresponding switch transistors 456-1, ..., 456-n. Bias voltage source VCAP 538 is configured to have a low value (e.g., 0 volts) during idle periods. In various examples, LOFIC network 450 shortens idle periods because residual charge in slave LOFIC 454-n can be discharged during one or more complete frame periods, not just during idle periods.

[0065] At time t 2 At , the idle period ends and the precharge period begins to reset the photodiode 414, the first floating diffusion FD1 418, the second floating diffusion FD2 426, and the third floating diffusion FD3 430, and the LOFIC network 450. The reset control signal RST 540 pulses the reset transistor 432, and the bias voltage source 538 is pulsed. For each frame, one of the switch control signals SW-1 534-1, ..., SW-n 534-n turns on the corresponding switch transistor 456-1, ..., 456-n (e.g., at Figure 5C , the nth switch control signal SW-n 534-n is turned on) until the read cycle ends, while the other switch control signals SW-1 534-1, ..., SW-n 534-n are pulsed during the precharge cycle (e.g., Figure 5C, each of the first switch control signal SW-1 534-1 to the second switch control signal SW-n 534-n is pulsed) so that all slave LOFICs 454-n and the master LOFIC 452 receive the same bias operation.

[0066] At time t 3 At , the precharge cycle ends and the integration cycle begins. The switch control signal SW-n 534-n corresponding to the active slave LOBIC 454-n of the frame remains on until the readout cycle ends as described above. The other control signals are turned off to ensure that the other slave LOBICs 454-n are inactive. During the integration period, the photodiode 414 photogenerates image charge in response to incident light. The pixel circuit 404 is configured so that excess photogenerated charge can overflow from the photodiode 414 to the LOBIC network 450 through the dual floating diffusion transistor 424 and the LOBIC transistor 428 for storage under strong or bright light conditions (e.g., LED light or IR light).

[0067] In one example, during the integration period, photogenerated excess image charge is configured to overflow from the photodiode 414 to the second floating diffusion FD2 426 through the dual floating diffusion transistor 424 and to the LOFIC network 450 through the dual floating diffusion transistor 424 and the LOFIC transistor 428 .

[0068] At time t 4 At , the integration period ends and the readout period begins. The bias voltage source VCAP 538 is turned on and remains on until the readout period ends. Next, a correlated double sampling (CDS) readout of the photodiode 414 occurs, during which a high conversion gain (HCG) readout of the reset value (R) from the photodiode 414 occurs. Then, an HCG readout of the signal value (S) occurs.

[0069] Next, LOFIC readout of photodiode 414 occurs, during which a first signal readout of a signal value (S) occurs. The first signal is output by pixel circuit 404 in response to image charge from master LOFIC 452 and slave LOFIC 454-n, which is output during an integration period by corresponding switching transistors 456-n and switch control signals (e.g., Figure 5C Next, the off switch transistor 456-n is switched on by the corresponding switch control signal (e.g., Figure 5CThe first switch control signal SW-1 534-1 to the (n-1)th switch control signal SW-(n-1) 534-(n-1)) are turned on. Then, a second signal readout of the signal value (S) occurs. The second signal is output by the pixel circuit 404 in response to the image charge from the master LOFIC 452 and all the slave LOFICs 454-1, ..., 454-n included in the LOFIC network 450.

[0070] Next, the reset control signal RST 540 pulses the reset transistor 432 and a second signal readout of the reset value (R) occurs. Then, the switch control signal (e.g., Figure 5C The first switch control signal SW-1 534-1 to the (n-1)th switch control signal SW-(n-1) 534-(n-1)) turns off the corresponding switch transistor 456-n. Then, a first signal readout of the reset value (R) occurs. In various examples, the CDS HCG readout can be determined by finding the difference between the HCG signal value (S) and the HCG reset value (R), and the CDS LOFIC readout of the first signal or the second signal can be determined by finding the difference between the LOC signal value (S) and the corresponding LOC reset value (R).

[0071] Next, the switch control signal (eg, Figure 5C The nth switch control signal SW-n 534-n) turns off the corresponding switch transistor 456-n, and the bias voltage source VCAP 538 is turned off. The timing diagram continues to move to time t 1 to proceed to the next frame.

[0072] exist Figure 4 , 5A , 5B and 5C, the LOFIC network 450 includes n slave capacitor-switch pairs. Thus, the n switching transistors of the LOFIC network 450 may be alternately turned on (or turned on one at a time) during the integration period on a frame-by-frame basis (e.g., the first switch control signal SW-1 534-1 is turned on during the integration period of the first, (n+1), (2n+1), etc. frames, and the second switch control signal SW-2 534-2 is turned on during the integration period of the second, (n+2), (2n+2), etc. frames).

[0073] Figure 6 6 is a flow chart illustrating one example of a process 600 for operating a pixel circuit including a lateral overflow integration capacitor (LOFIC) network and a photodiode according to the teachings of the present disclosure. It should be appreciated that Figure 6 The processing described in Figure 2 and 4 The operation of example pixel circuits (eg, pixel circuits 204 and 404) described in . In various examples, process 600 is used to compensate for image lag accumulated in a primary LOFIC.

[0074] At processing block 610, a first signal is read out (e.g., by a master LOFIC 452) and an image charge from a slave LOFIC (e.g., first slave LOFIC 454-1) of a first of a plurality of slave capacitor-switch pairs. Figure 1 106). Because the first slave LOFIC is assumed to have discharged all residual image charge and output no image lag, the first signal represents the lag-free signal for that frame plus the image lag from the master LOFIC. In various examples, a correlated double sampling (CDS) LOFIC readout of the first signal may be determined by finding the difference between the LOFIC signal value (S) corresponding to the first signal and the LOFIC reset value (R), as described above with reference to Figure 3A , 3B , 5A, 5B and 5C.

[0075] At processing block 620, a second signal is read out in response to the master LOBIC and the image charge from all slave LOBICs of the plurality of slave capacitor-switch pairs (e.g., slave capacitors 454-1, ..., 454-n). The second signal represents the lag-free signal for that frame plus the image lag from the master LOBIC (i.e., the first signal) plus the image lag from the slave LOBIC (as previously described, the first slave LOBIC is assumed to have discharged all residual image charge and outputs no image lag). In various instances, the CDS LOFIC readout of the second signal may be determined by finding the difference between the LOBIC signal value (S) corresponding to the second signal and the LOBIC reset value (R), as described above with reference to FIG. Figure 3A , 3B , 5A, 5B and 5C.

[0076] At processing block 630, a difference between the first signal and the second signal is determined (e.g., the first signal is subtracted from the second signal) to obtain a slave LOFIC hysteresis signal. The slave LOFIC hysteresis signal represents the image hysteresis from all slave LOFICs (as previously described, the first slave LOFIC is assumed to have zero image hysteresis).

[0077] At processing block 640, the slave LOBIC hysteresis signal is scaled based on the number of remaining slave LOBICs (the number of slave LOBICs with image hysteresis, i.e., n-1) to obtain an average slave LOBIC hysteresis signal. At any given frame, each slave LOBIC has discharged the residual image charge in a different time period (e.g., in a pixel circuit with five slave capacitor-switch pairs, at the beginning of the 5th frame, the first slave LOBIC has three full frame periods to discharge, while the third slave LOBIC has only one full frame period to discharge). Therefore, each slave LOBIC may contain a different degree of image hysteresis. In one example, the average slave LOBIC hysteresis signal is obtained by finding the quotient of the slave LOBIC hysteresis signal and the number of remaining slave LOBICs (i.e., n-1) (e.g., dividing).

[0078] At processing block 650, the product of the average LOBIC hysteresis signal and the capacitor ratio is determined (e.g., multiplied) to obtain a primary LOBIC hysteresis signal. The primary LOBIC hysteresis signal represents the image hysteresis from the primary LOBIC. The capacitor ratio is the capacitance ratio between the primary LOBIC and one of the slave LOBICs. In various instances, the image hysteresis accumulated in the capacitor is assumed to be proportional to the capacitance of the capacitor. Therefore, the image hysteresis ratio between the primary LOBIC and the slave LOBIC is assumed to be equivalent to the capacitance ratio between the primary LOBIC and the slave LOBIC. In addition, the capacitance of a capacitor is proportional to the dielectric constant, proportional to the capacitor area, and inversely proportional to the dielectric thickness. Therefore, if the primary LOBIC and the slave LOBIC have the same dielectric composition and dielectric thickness, the capacitance ratio can be replaced by the capacitance area ratio. As a result, in various instances, the primary LOBIC hysteresis signal is obtained by multiplying the average LOBIC hysteresis signal by the capacitance area ratio.

[0079] At processing block 660, a difference (eg, subtraction) is determined between the primary LOFIC hysteresis signal and the first signal to obtain the hysteresis-free signal for the frame. As described above, the first signal represents the hysteresis-free signal for that frame plus the image hysteresis from the primary LOFIC.

[0080] The various embodiments of the LOFIC networks described herein may be used with any imaging system (eg, an automated sensor) that includes a MIM capacitor.The disclosed LOFIC networks help resolve hysteresis issues associated with imaging systems.

[0081] The above description of the illustrated examples of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific examples of the present disclosure are described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the present disclosure.

[0082] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the following claim bundle should not be interpreted as limiting the present disclosure to the specific examples disclosed in the specification. Instead, the scope of the present disclosure will be determined entirely by the following claims, which will be interpreted in accordance with established principles of claim interpretation.

Claims

1. A pixel circuit, include: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the floating diffusion, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion; a reset transistor coupled between a reset voltage and the floating diffusion; as well as a lateral overflow integrating capacitor (LOFIC) network coupled between the reset transistor and a bias voltage source, wherein the LOFIC network comprises: a primary LOFIC coupled between the reset transistor and the bias voltage source; and a plurality of slave capacitor-switch pairs, wherein each of the plurality of slave capacitor-switch pairs comprises: Dependent LOFIC; and A switching transistor is coupled to the slave LOFIC, wherein each of the plurality of slave capacitor-switch pairs is coupled between the reset transistor and the bias voltage source.

2. The pixel circuit according to claim 1, wherein the pixel circuit is configured to: outputting a first signal in response to image charge from the master LOFIC and the slave LOFIC of a first of the plurality of slave capacitor-switch pairs; and outputting a second signal in response to image charge from the master LOFIC and all of the slave LOFICs of the plurality of slave capacitor-switch pairs, wherein a slave LOFIC hysteresis signal is determined in response to a difference between the second signal and the first signal, wherein an average slave L OFIC hysteresis signal is determined in response to a quotient of the slave L OFIC hysteresis signal and the number of remaining slave L OFICs; wherein a master LOBIC hysteresis signal is determined in response to a product of the average slave LOBIC hysteresis signal and a capacitor ratio, wherein the capacitor ratio is a capacitance ratio between the master LOBIC and the slave LOBIC of one of the plurality of slave capacitor-switch pairs, and Wherein a no hysteresis signal is determined in response to a difference between the first signal and the primary LOFIC hysteresis signal.

3. A pixel circuit according to claim 1, wherein during a first frame period, the switching transistor of the first one of the plurality of slave capacitor-switch pairs is configured to be turned on, and simultaneously the switching transistors of the remaining slave capacitor-switch pairs of the plurality of slave capacitor-switch pairs are configured to be turned off and discharge the residual image charge.

4. A pixel circuit according to claim 3, wherein during a second frame period, the switching transistor of the second one of the plurality of slave capacitor-switch pairs is configured to be turned on, and at the same time, the switching transistors of the remaining slave capacitor-switch pairs of the plurality of slave capacitor-switch pairs are configured to be turned off and discharge the residual image charge. 5 . The pixel circuit of claim 1 , wherein the master LOFIC and each slave LOFIC of the plurality of slave capacitor-switch pairs have the same dielectric composition. 6 . The pixel circuit of claim 1 , wherein the master LOFIC and each slave LOFIC of the plurality of slave capacitor-switch pairs have a same dielectric thickness. 7 . The pixel circuit of claim 1 , wherein the master LOFIC has a larger capacitive area than each slave LOFIC of the plurality of slave capacitor-switch pairs.

8. The pixel circuit of claim 1, wherein the master LOFIC and each slave LOFIC of the plurality of slave capacitor-switch pairs have the same biasing scheme during an idle period of a frame.

9. The pixel circuit of claim 8, wherein the master LOFIC and each slave LOFIC of the plurality of slave capacitor-switch pairs are reverse biased during the idle period.

10. The pixel circuit of claim 1, wherein the plurality of slave capacitor-switch pairs comprises two slave capacitor-switch pairs.

11. The pixel circuit of claim 1, wherein the plurality of slave capacitor-switch pairs comprises three slave capacitor-switch pairs.

12. The pixel circuit of claim 1, wherein the primary LOFIC and each of the plurality of slave capacitor-switch pairs are coupled in parallel with each other between the reset transistor and the bias voltage source.

13. The pixel circuit of claim 1 , wherein the floating diffusion is a first floating diffusion, and wherein the pixel circuit further comprises: include: a second floating diffusion coupled between the first floating diffusion and the reset transistor; a double floating diffusion (DFD) transistor coupled between the first floating diffusion and the second floating diffusion; a third floating diffusion coupled between the second floating diffusion and the reset transistor; and A LOFIC transistor is coupled between the second floating diffusion and the third floating diffusion, wherein the LOFIC network is coupled between the third floating diffusion and the bias voltage source.

14. The pixel circuit according to claim 13, further comprising: include: a source follower transistor having a gate coupled to the first floating diffusion; and A row select transistor is coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between a power line and a bit line.

15. The pixel circuit of claim 1, wherein the LOFIC network further comprises a primary switching transistor coupled to the primary LOFIC.

16. A method of operating a pixel circuit, wherein include: During the first frame period— photogenerating image charge in a photodiode in response to incident light; transferring the image charge from the photodiode to a floating diffusion; a lateral overflow integrating capacitor (LOFIC) network that transfers overflow image charge from the photodiode to the pixel circuit, wherein the LOFIC network comprises a master LOFIC and a plurality of slave capacitor-switch pairs, wherein each of the plurality of slave capacitor-switch pairs comprises a slave LOFIC and a switch transistor coupled in series to the slave LOFIC; turning on the switching transistor of a first one of the plurality of slave capacitor-switch pairs; and The switch transistors of the remaining slave capacitor-switch pairs among the plurality of slave capacitor-switch pairs are turned off simultaneously.

17. The method according to claim 16, further comprising: include: During the first frame period— reading out a first signal, wherein the first signal represents image charge from the master LOFIC and the slave LOFIC of a first of the plurality of slave capacitor-switch pairs; reading out a second signal, wherein the second signal represents image charge from the master LOFIC and the slave LOFICs of the plurality of slave capacitor-switch pairs; subtracting the first signal from the second signal to obtain a slave LOFIC hysteresis signal; scaling the slave LOBIC hysteresis signal based on the number of remaining slave LOBICs to obtain an average slave LOBIC hysteresis signal; multiplying the average slave LOFIC hysteresis signal by a capacitor ratio to obtain a master LOFIC hysteresis signal, wherein the capacitor ratio is a capacitance ratio between the master LOFIC and the slave LOFIC of one of the plurality of slave capacitor-switch pairs; and The primary LOFIC hysteresis signal is subtracted from the first signal to obtain a hysteresis-free signal.

18. The method according to claim 17, further comprising: include: During the second frame period— turning on the switching transistor of a second one of the plurality of slave capacitor-switch pairs; and The switch transistors of the remaining slave capacitor-switch pairs among the plurality of slave capacitor-switch pairs are turned off simultaneously.

19. The method of claim 17, wherein the capacitor ratio is a capacitance area ratio between the master LOFIC and the slave LOFIC of one of the plurality of slave capacitor-switch pairs.

20. The method of claim 16, wherein the master LOFIC and each slave LOFIC of the plurality of slave capacitor-switch pairs have the same dielectric composition, the same dielectric thickness and / or the same biasing scheme, and wherein the master LOFIC has a larger capacitive area than each slave LOFIC of the plurality of slave capacitor-switch pairs.

Images