A multiplexing chip circuit

Abstract

The present invention discloses a multiplexing chip circuit, including a third resistor, a fourth resistor, a fifth resistor, an eleventh resistor, a first operational amplifier, a second triode, a first connector, and a second connector. The non-inverting input terminal of the first operational amplifier is connected to one end of the eleventh resistor and the first connector. The inverting input terminal of the first operational amplifier is connected to one end of the fifth resistor. The output terminal of the first operational amplifier is connected to the other end of the fifth resistor and the emitter of the second triode. The collector of the second triode is connected to one end of the fourth resistor and the second connector. The base of the second triode is connected to one end of the third resistor. The other end of the third resistor, the other end of the fourth resistor, and the other end of the eleventh resistor are connected to the ground terminal.

Description

Technical Field

[0001] The present invention relates to the technical field of chip reuse, and particularly to a reusable chip circuit. Background Art

[0002] Each pin in a chip needs to occupy a certain amount of chip space. Therefore, an increase in the number of pins will lead to an increase in the chip size and production cost. Chip reuse can improve the applicability and flexibility of the chip. However, existing chip reuse technologies mostly add peripheral devices and switch circuits to achieve the purpose of chip reuse. It is impossible to reuse the pins of the chip while setting the common switching threshold of two working modules sharing the pins, so that the two working modules can flexibly switch the working threshold according to their needs during operation to obtain the feedback of the signals they need, and make the signal input ports of the two working modules enter the silent state during the switching period to prevent the two working modules from having an incorrect response during and after the working threshold switching and before the switching signal ends. Summary of the Invention

[0003] To solve the above technical problems, the object of the present invention is to provide a reusable chip circuit, including a third resistor R3, a fourth resistor R4, a fifth resistor R5, an eleventh resistor R11, a first operational amplifier U1, a second triode Q2, a first connector P1, and a second connector P2. The non-inverting input terminal of the first operational amplifier U1 is connected to one end of the eleventh resistor R11 and the first connector P1. The inverting input terminal of the first operational amplifier U1 is connected to one end of the fifth resistor R5. The output terminal of the first operational amplifier U1 is connected to the other end of the fifth resistor R5 and the emitter of the second triode Q2. The collector of the second triode Q2 is connected to one end of the fourth resistor R4 and the second connector P2. The base of the second triode Q2 is connected to one end of the third resistor R3. The other end of the third resistor R3, the other end of the fourth resistor R4, and the other end of the eleventh resistor R11 are connected to the ground terminal.

[0004] Further, it further includes a first resistor R1, a second resistor R2, a twelfth resistor R12, a fourth operational amplifier U4, a fifth operational amplifier U5, a first MOS transistor Q1, and a fourth MOS transistor Q4. One end of the second resistor R2 is connected to a power supply, and the other end of the second resistor R2 is connected to one end of the first resistor R1 and the non-inverting input terminal of the fourth operational amplifier U4. The inverting input terminal of the fourth operational amplifier U4 is connected to one end of the twelfth resistor R12. The output terminal of the fourth operational amplifier U4 is connected to the other end of the twelfth resistor R12 and the source electrode of the first MOS transistor Q1. The drain electrode of the first MOS transistor Q1 is connected to the inverting input terminal of the fifth operational amplifier U5. The output terminal of the fifth operational amplifier U5 is connected to the base electrode of the second triode Q2. The non-inverting input terminal of the fifth operational amplifier U5 is connected to the drain electrode of the fourth MOS transistor Q4. The source electrode of the fourth MOS transistor Q4 is connected to the emitter electrode of the second triode Q2. The gate electrode of the fourth MOS transistor Q4 is connected to the gate electrode of the first MOS transistor Q1. The other end of the first resistor R1 is connected to a ground terminal.

[0005] Further, it further includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a second operational amplifier U2, an eighth MOS transistor Q8, a first diode D1, and a first capacitor C1. One end of the eighth resistor R8 is connected to a power supply, and the other end of the eighth resistor R8 is connected to one end of the seventh resistor R7 and the inverting input terminal of the second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is connected to a first connector P1. The output terminal of the second operational amplifier U2 is connected to one end of the ninth resistor R9, one end of the tenth resistor R10, and the anode of the first diode D1. The other end of the ninth resistor R9 is connected to one end of the first capacitor C1 and the gate electrode of the eighth MOS transistor Q8. The cathode of the first diode D1 is connected to the output terminal of the fifth operational amplifier U5. The other end of the seventh resistor R7, the other end of the tenth resistor R10, and the other end of the first capacitor C1 are connected to a ground terminal.

[0006] Further, it further includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a third operational amplifier U3, a third MOS transistor Q3, a fifth MOS transistor Q5, a sixth triode Q6, a seventh triode Q7, and a second capacitor C2. One end of the thirteenth resistor R13, one end of the sixteenth resistor R16 are connected to a power supply. The other end of the thirteenth resistor R13, one end of the fourteenth resistor R14, one end of the seventeenth resistor R17, and the collector of the sixth triode Q6 are connected. The other end of the fourteenth resistor R14, one end of the second capacitor C2, and the source of the eighth MOS transistor Q8 are connected. The other end of the sixteenth resistor R16, one end of the fifteenth resistor R15, the collector of the seventh triode Q7, and the non-inverting input terminal of the third operational amplifier U3 are connected. The other end of the fifteenth resistor R15, the base of the sixth triode Q6, and the drain of the eighth MOS transistor Q8 are connected. The inverting input terminal of the third operational amplifier U3 is connected to the inverting input terminal of the second operational amplifier U2. The output terminal of the third operational amplifier U3 is connected to the gate of the first MOS transistor Q1, the gate of the third MOS transistor Q3, the gate of the fourth MOS transistor Q4, and the gate of the fifth MOS transistor Q5. The drain of the fifth MOS transistor Q5 is connected to the output terminal of the fourth operational amplifier U4. The source of the fifth MOS transistor Q5 is connected to the drain of the fourth MOS transistor Q4. The source of the third MOS transistor Q3 is connected to the drain of the first MOS transistor Q1. The drain of the third MOS transistor Q3 is connected to the emitter of the second triode Q2. The other end of the seventeenth resistor R17 is connected to the base of the seventh triode Q7. The emitters of the sixth triode Q6 and the seventh triode Q7 are connected to a ground terminal.

[0007] Further, it further includes an eighteenth resistor R18. One end of the eighteenth resistor R18 is connected to the gate of the eighth MOS transistor Q8, and the other end of the eighteenth resistor R18 is connected to a ground terminal.

[0008] Further, it further includes a sixth resistor R6. One end of the sixth resistor R6 is connected to the gate of the third MOS transistor Q3, and the other end of the sixth resistor R6 is connected to a ground terminal.

[0009] Further, the ninth resistor R9 can be a variable resistor.

[0010] The beneficial effects of the present invention compared with the prior art are as follows:

[0011] The present invention can multiplex the pins of the chip while setting the common switching threshold of two working modules sharing the pins, so that the two working modules can flexibly switch the working threshold according to their needs during operation to obtain the feedback of the signals they need, and make the signal input ports of the two working modules enter the silent state during the switching period to prevent the two working modules from having an incorrect response during and after the working threshold switching and before the switching signal ends. Description of the Drawings

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required in the prior art and the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 The circuit structure diagram provided by the present invention. Specific embodiments

[0014] In order to make the purpose and advantages of the present invention more clear, the following will specifically describe the present invention in combination with embodiments. It should be understood that the following text only describes one or several specific implementation manners of the present invention, and does not strictly limit the scope of protection of the specific claims of the present invention.

[0015] The present invention discloses a multiplexing chip circuit, including a third resistor R3, a fourth resistor R4, a fifth resistor R5, an eleventh resistor R11, a first operational amplifier U1, a second triode Q2, a first connector P1, and a second connector P2. The non-inverting input terminal of the first operational amplifier U1 is connected to one end of the eleventh resistor R11 and the first connector P1. The inverting input terminal of the first operational amplifier U1 is connected to one end of the fifth resistor R5. The output terminal of the first operational amplifier U1 is connected to the other end of the fifth resistor R5 and the emitter of the second triode Q2. The collector of the second triode Q2 is connected to one end of the fourth resistor R4 and the second connector P2. The base of the second triode Q2 is connected to one end of the third resistor R3. The other end of the third resistor R3, the other end of the fourth resistor R4, and the other end of the eleventh resistor R11 are connected to the ground terminal.

[0016] Specifically, it further includes a first resistor R1, a second resistor R2, a twelfth resistor R12, a fourth operational amplifier U4, a fifth operational amplifier U5, a first MOS transistor Q1, and a fourth MOS transistor Q4. One end of the second resistor R2 is connected to the power supply. The other end of the second resistor R2 is connected to one end of the first resistor R1 and the non-inverting input terminal of the fourth operational amplifier U4. The inverting input terminal of the fourth operational amplifier U4 is connected to one end of the twelfth resistor R12. The output terminal of the fourth operational amplifier U4 is connected to the other end of the twelfth resistor R12 and the source of the first MOS transistor Q1. The drain of the first MOS transistor Q1 is connected to the inverting input terminal of the fifth operational amplifier U5. The output terminal of the fifth operational amplifier U5 is connected to the base of the second triode Q2. The non-inverting input terminal of the fifth operational amplifier U5 is connected to the drain of the fourth MOS transistor Q4. The source of the fourth MOS transistor Q4 is connected to the emitter of the second triode Q2. The gate of the fourth MOS transistor Q4 is connected to the gate of the first MOS transistor Q1. The other end of the first resistor R1 is connected to the ground terminal.

[0017] Specifically, it further includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a second operational amplifier U2, an eighth MOS transistor Q8, a first diode D1, and a first capacitor C1. One end of the eighth resistor R8 is connected to the power supply, and the other end of the eighth resistor R8 is connected to one end of the seventh resistor R7 and the inverting input terminal of the second operational amplifier U2. The non-inverting input terminal of the second operational amplifier U2 is connected to the first connector P1. The output terminal of the second operational amplifier U2 is connected to one end of the ninth resistor R9, one end of the tenth resistor R10, and the anode of the first diode D1. The other end of the ninth resistor R9 is connected to one end of the first capacitor C1 and the gate of the eighth MOS transistor Q8. The cathode of the first diode D1 is connected to the output terminal of the fifth operational amplifier U5. The other end of the seventh resistor R7, the other end of the tenth resistor R10, and the other end of the first capacitor C1 are connected to the ground terminal.

[0018] Specifically, it further includes a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, a third operational amplifier U3, a third MOS transistor Q3, a fifth MOS transistor Q5, a sixth triode Q6, a seventh triode Q7, and a second capacitor C2. One end of the thirteenth resistor R13 and one end of the sixteenth resistor R16 are connected to the power supply. The other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14, one end of the seventeenth resistor R17, and the collector of the sixth triode Q6. The other end of the fourteenth resistor R14 is connected to one end of the second capacitor C2 and the source of the eighth MOS transistor Q8. The other end of the sixteenth resistor R16 is connected to one end of the fifteenth resistor R15, the collector of the seventh triode Q7, and the non-inverting input terminal of the third operational amplifier U3. The other end of the fifteenth resistor R15 is connected to the base of the sixth triode Q6 and the drain of the eighth MOS transistor Q8. The inverting input terminal of the third operational amplifier U3 is connected to the inverting input terminal of the second operational amplifier U2. The output terminal of the third operational amplifier U3 is connected to the gate of the first MOS transistor Q1, the gate of the third MOS transistor Q3, the gate of the fourth MOS transistor Q4, and the gate of the fifth MOS transistor Q5. The drain of the fifth MOS transistor Q5 is connected to the output terminal of the fourth operational amplifier U4. The source of the fifth MOS transistor Q5 is connected to the drain of the fourth MOS transistor Q4. The source of the third MOS transistor Q3 is connected to the drain of the first MOS transistor Q1. The drain of the third MOS transistor Q3 is connected to the emitter of the second triode Q2. The other end of the seventeenth resistor R17 is connected to the base of the seventh triode Q7. The emitter of the sixth triode Q6 and the emitter of the seventh triode Q7 are connected to the ground terminal.

[0019] Specifically, it further includes an eighteenth resistor R18. One end of the eighteenth resistor R18 is connected to the gate of the eighth MOS transistor Q8, and the other end of the eighteenth resistor R18 is connected to the ground terminal.

[0020] Specifically, it further includes a sixth resistor R6. One end of the sixth resistor R6 is connected to the gate of the third MOS transistor Q3, and the other end of the sixth resistor R6 is connected to the ground terminal.

[0021] Specifically, the ninth resistor R9 can be a variable resistor.

[0022] The control signal is fed back to the signal input terminal of the chip. The signal at the signal input terminal of the chip is fed back to the first connector P1. The signal of the first connector P1 passes through the eleventh resistor R11 to the ground terminal loop. The signal at the end of the eleventh resistor R11 is fed back to the non-inverting terminal of the first operational amplifier U1. The output terminal of the first operational amplifier U1 is connected in negative feedback to the inverting terminal of the first operational amplifier U1 through the fifth resistor R5 to prevent interference from the lower-level circuit. At the same time, the signal at the output terminal of the first operational amplifier U1 passes through the emitter of the second triode Q2, the base of the second triode Q2, and the third resistor R3 to the ground terminal loop. The emitter and the base of the second triode Q2 are forward-biased, and the second triode Q2 conducts. The signal at the output terminal of the first operational amplifier U1 passes through the emitter of the second triode Q2, the collector of the second triode Q2, and the ground terminal loop of the fourth resistor R4. The signal at the end of the fourth resistor R4 is fed back to the signal output terminal of the chip through the second connector P2. The signal input terminals of the two working mode modules are connected to the second connector P2. The power supply signal passes through the second resistor R2 and the first resistor R1 to the ground terminal loop. The signal amplitude at the end of the first resistor R1 is the upper limit value of the working threshold of the first working module. The signal at the end of the first resistor R1 is fed back to the non-inverting terminal of the fourth operational amplifier U4. The output terminal of the fourth operational amplifier U4 is connected in negative feedback to the inverting terminal of the fourth operational amplifier U4 through the twelfth resistor R12 to prevent interference from the lower-level circuit. At the same time, the signal at the output terminal of the fourth operational amplifier U4 is fed back to the inverting terminal of the fifth operational amplifier U5 through the source and the drain of the first MOS transistor Q1. The signal at the output terminal of the first operational amplifier U1 is fed back to the non-inverting terminal of the fifth operational amplifier U5 through the source and the drain of the fourth MOS transistor Q4. When the signal amplitude at the signal input terminal of the chip is between the upper limit value of the working threshold of the first working module, the fifth operational amplifier U5 is cut off. At this time, the amplitude of the working signal that can be fed back at the second connector P2 terminal is the working signal required for the operation of the first working module. When the signal amplitude at the signal input terminal of the chip is higher than the upper limit value of the working threshold of the first working module, the fifth operational amplifier U5 outputs, and the second triode Q2 is cut off. The two working modules lose the feedback of the second connector P2. The power supply signal passes through the eighth resistor R8 and the seventh resistor R7 to the ground terminal loop. The signal amplitude at the end of the seventh resistor R7 is both the lower limit amplitude of the common switching threshold of the two working modules and the upper limit amplitude of the working threshold of the second working module. The signal at the end of the seventh resistor R7 is fed back to the inverting terminal of the second operational amplifier U2. The signal at the end of the eleventh resistor R11 is fed back to the non-inverting terminal of the second operational amplifier U2. When it is necessary to switch the working thresholds of the two working modules, the amplitude of the signal fed back by the control signal will be higher than the lower limit amplitude of the common switching threshold of the two working modules. The second operational amplifier U2 outputs. The signal at the output terminal of the second operational amplifier U2 passes through the tenth resistor R10 to the ground terminal loop. At the same time, the signal at the output terminal of the second operational amplifier U2 causes the potential of the first capacitor C1 to rise through the ninth resistor R9. The signal at the end of the first capacitor C1 is fed back to the gate of the eighth MOS transistor Q8.The eighteenth resistor R18 is used to discharge the parasitic capacitance of the gate of the eighth MOS transistor Q8. When the potential at one end of the first capacitor C1 rises by a certain amplitude, the voltage difference between the gate and the source of the eighth MOS transistor Q8 is higher than the conduction threshold, and the eighth MOS transistor Q8 conducts. By adjusting the resistance value of the ninth resistor R9, the rising speed of the potential of the first capacitor C1 can be changed. Adjusting the resistance value of the ninth resistor R9 as needed can prevent the control signal from causing the eighth MOS transistor Q8 to conduct when the second operational amplifier U2 outputs in an environment with strong signal interference. At the same time, the signal at the output end of the second operational amplifier U2 passes through the first diode D1 and the third resistor R3 to the ground loop, and the second triode Q2 is cut off. When the signal fed back by the control signal is lower than the lower limit amplitude of the common switching threshold of the two working modules, the eighth MOS transistor Q8 is cut off, so that the signal input ports of the two working modules enter the silent state during the switching period to prevent the two working modules from having incorrect responses during and after the switching of the working thresholds of the two working modules and before the switching signal ends. The power supply signal passes through the sixteenth resistor R16, the fifteenth resistor R15, the base of the sixth triode Q6, and the emitter of the sixth triode Q6 to the ground loop. The base and the emitter of the sixth triode Q6 are forward-biased and the sixth triode Q6 conducts. The power supply signal passes through the thirteenth resistor R13, the collector of the sixth triode Q6, and the emitter of the sixth triode Q6 to the ground loop. The signal at the collector end of the sixth triode Q6 causes the potential of the second capacitor C2 to rise after passing through the fourteenth resistor R14. At the same time, the signal at the collector end of the sixth triode Q6 passes through the seventeenth resistor R17, the base of the seventh triode Q7, and the emitter of the seventh triode Q7 to the ground loop. The base and the emitter of the seventh triode Q7 are forward-biased and the seventh triode Q7 conducts. The signal at the fifteenth resistor R15 passes through the collector and the emitter of the seventh triode Q7 to the ground loop. At the same time, the signal at the fifteenth resistor R15 is fed back to the non-inverting input end of the third operational amplifier U3. When the eighth MOS transistor Q8 conducts, the signal at the base end of the sixth triode Q6 is fed back to the second capacitor C2 end through the drain and the source of the eighth MOS transistor Q8. The rising potential of the second capacitor C2 end amplifies the signal at the collector end of the seventh triode Q7. When the eighth MOS transistor Q8 is cut off, the potential of the second capacitor C2 drops, and the signal at the seventh resistor R7 is fed back to the inverting input end of the third operational amplifier U3. The third operational amplifier U3 outputs, and the signal at the output end of the third operational amplifier U3 is fed back to the gates of the first MOS transistor Q1, the third MOS transistor Q3, the fourth MOS transistor Q4, and the fifth MOS transistor Q5. The sixth resistor R6 is used to discharge the parasitic capacitance of the gates of the first MOS transistor Q1, the third MOS transistor Q3, the fourth MOS transistor Q4, and the fifth MOS transistor Q5. The voltage difference between the gate and the source of the first MOS transistor Q1 is higher than the conduction threshold, and the first MOS transistor Q1 is cut off. The voltage difference between the gate and the source of the third MOS transistor Q3 is higher than the conduction threshold.The third MOS transistor Q3 conducts, and the signal at the output terminal of the first operational amplifier U1 is fed back to the inverting terminal of the fifth operational amplifier U5 through the drain and source of the third MOS transistor Q3. The voltage difference between the gate and source of the fourth MOS transistor Q4 is higher than the conduction threshold, so the fourth MOS transistor Q4 is cut off. The voltage difference between the gate and source of the fifth MOS transistor Q5 is higher than the conduction threshold, so the fifth MOS transistor Q5 conducts. The signal at the output terminal of the fourth operational amplifier U4 is fed back to the non-inverting terminal of the fifth operational amplifier U5 through the drain and source of the fifth MOS transistor Q5. At this time, the amplitude of the working signal that can be fed back at the second connector P2 is the working signal required for the operation of the second working module. When the signal fed back by the control signal is higher than the lower limit amplitude of the common switching threshold of the two working modules again, the eighth MOS transistor Q8 conducts, the potential of the second capacitor C2 rises, the signal at the collector terminal of the sixth triode Q6 is amplified, and the third operational amplifier U3 is cut off. In this way, based on the common switching threshold of the two working modules sharing pins, the two working modules can flexibly switch the working threshold according to their needs during operation so as to obtain the feedback of the signals they need respectively.

[0023] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present invention. Any reference signs in the claims should not be regarded as limiting the claimed claim.

Claims

1. A multiplexing chip circuit, characterized in that: The invention comprises a third resistor, a fourth resistor, a fifth resistor, an eleventh resistor, a first operational amplifier, a second triode, a first connector, and a second connector, wherein the in-phase end of the first operational amplifier is connected to one end of the eleventh resistor and the first connector, the inverting end of the first operational amplifier is connected to one end of the fifth resistor, the output end of the first operational amplifier is connected to the other end of the fifth resistor and the emitter of the second triode, the collector of the second triode is connected to one end of the fourth resistor and the second connector, the base of the second triode is connected to one end of the third resistor, the other end of the third resistor, the other end of the fourth resistor, the other end of the eleventh resistor and the grounding end, and further comprises a first resistor, a second resistor, a twelfth resistor, a fourth operational amplifier, a fifth operational amplifier, a first MOS tube, a fourth M OS tube, one end of the second resistor is connected to the power supply, the other end of the second resistor is connected to one end of the first resistor and the in-phase end of the fourth operational amplifier, the inverting end of the fourth operational amplifier is connected to one end of the twelfth resistor, the output end of the fourth operational amplifier is connected to the other end of the twelfth resistor and the source of the first MOS tube, the drain of the first MOS tube is connected to the inverting end of the fifth operational amplifier, the output end of the fifth operational amplifier is connected to the base of the second triode, the in-phase end of the fifth operational amplifier is connected to the drain of the fourth MOS tube, the source of the fourth MOS tube is connected to the emitter of the second triode, the gate of the fourth MOS tube is connected to the gate of the first MOS tube, the other end of the first resistor is connected to the ground end, and also includes a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, the second operational amplifier a device, an eighth MOS tube, a first diode, and a first capacitor, one end of the eighth resistor is connected to the power supply, the other end of the eighth resistor is connected to one end of the seventh resistor and the inverting end of the second operational amplifier, the non-inverting end of the second operational amplifier is connected to the first connector, the output end of the second operational amplifier is connected to one end of the ninth resistor, one end of the tenth resistor, and the anode of the first diode, the other end of the ninth resistor is connected to one end of the first capacitor and the grid of the eighth MOS tube, the cathode of the first diode is connected to the output end of the fifth operational amplifier, the other end of the seventh resistor, the other end of the tenth resistor, the other end of the first capacitor are connected to the ground, and also includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, a third operational amplifier, a third MOS tube, a fifth MO S tube, the sixth triode, the seventh triode, the second capacitor, one end of the thirteenth resistor and one end of the sixteenth resistor are connected to the power supply, the other end of the thirteenth resistor is connected to one end of the fourteenth resistor, one end of the seventeenth resistor, and the collector of the sixth triode, the other end of the fourteenth resistor is connected to one end of the second capacitor and the source of the eighth MOS tube, the other end of the sixteenth resistor is connected to one end of the fifteenth resistor, the collector of the seventh triode, and the in-phase end of the third operational amplifier, the other end of the fifteenth resistor is connected to the base of the sixth triode and the drain of the eighth MOS tube, the inverting end of the third operational amplifier is connected to the inverting end of the second operational amplifier, and the output end of the third operational amplifier is connected to the gate of the first MOS tube, the gate of the third MOS tube, the gate of the fourth MOS tube, and the gate of the fifth MOS tube,The drain of the fifth MOS tube is connected to the output end of the fourth operational amplifier, the source of the fifth MOS tube is connected to the drain of the fourth MOS tube, the source of the third MOS tube is connected to the drain of the first MOS tube, the drain of the third MOS tube is connected to the emitter of the second transistor, the other end of the seventeenth resistor is connected to the base of the seventh transistor, and the emitter of the sixth transistor, the emitter of the seventh transistor and the ground terminal are connected.

2. The multiplexing chip circuit according to claim 1, characterized in that: It also includes an eighteenth resistor, one end of the eighteenth resistor is connected to the gate of the eighth MOS tube, and the other end of the eighteenth resistor is connected to the ground end.

3. The multiplexing chip circuit according to claim 1, characterized in that: It also includes a sixth resistor, one end of which is connected to the gate of the third MOS tube, and the other end of which is connected to the ground.

4. The multiplexing chip circuit according to claim 1, characterized in that: The ninth resistor may be an adjustable resistor.

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