Electric storage battery pack, semiconductor device, and method for manufacturing semiconductor device

Abstract

The electricity storage pack (100) includes: an electricity storage unit (3), electricity storage sheets (80AB) connected to the electricity storage unit (3), a protection circuit board (60) for protecting the electricity storage unit (3) against overcharging or over-discharging, a chip scale package type semiconductor element (2A) mounted face-down on the protection circuit board (60), and an electricity storage sheet bonding metal plate (70AB) having a portion with a thickness of 0.2 mm or less and connected to the semiconductor element (2A) with a first main surface. In a plan view of the protection circuit board (60), the electricity storage sheet bonding metal plate (70AB) is bonded to the electricity storage sheet (80AB) with a second main surface facing away from the first main surface, so that there is an overlapping portion where the electricity storage sheet (80AB), the electricity storage sheet bonding metal plate (70AB), the semiconductor element (2A), and the protection circuit board (60) overlap. In the plan view of the protection circuit board (60), there is a portion where a region that can form a conduction path between the electricity storage sheet (80AB) and the protection circuit board (60) overlaps with the overlapping portion.

Description

Technical Field

[0001] The present invention relates to a power storage pack, a semiconductor device used in the power storage pack, and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, a power storage pack using a semiconductor device has been known (for example, Patent Document 1).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: International Publication No. 2022 / 009396 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] Generally, in a power storage pack, a power storage unit and a protection circuit board on which a semiconductor element is mounted and which has a function of protecting the power storage unit against overcharging or over-discharging are included.

[0008] The protection circuit board included in the power storage pack is desired to be miniaturized.

[0009] Therefore, an object of the present disclosure is to provide a power storage pack, a semiconductor device, and a method for manufacturing the semiconductor device that can achieve miniaturization of the protection circuit board.

[0010] Means for Solving the Problems

[0011] A power storage pack according to an embodiment of the present disclosure includes: a power storage unit; a power storage sheet connected to the power storage unit and serving as a conduction path for charging the power storage unit or discharging from the power storage unit; a protection circuit board that protects the power storage unit against overcharging or over-discharging; a chip scale package type semiconductor element mounted face down on the protection circuit board; and a power storage sheet bonding metal plate connected to the semiconductor element through a first main surface and having a portion with a thickness of 0.2 mm or less; the power storage sheet bonding metal plate is bonded to the power storage sheet through a second main surface opposite to the first main surface so that in a plan view of the protection circuit board, there is an overlapping portion where the power storage sheet, the power storage sheet bonding metal plate, the semiconductor element, and the protection circuit board overlap; in the plan view of the protection circuit board, there is a portion where a region that can serve as the conduction path between the power storage sheet and the protection circuit board overlaps with the overlapping portion.

[0012] A semiconductor device according to an embodiment of the present disclosure includes: a chip size package type semiconductor element having a plurality of external connection terminals; and a first metal plate having a portion with a thickness of 0.2 mm or less. The first metal plate is connected to one main surface of the semiconductor element. On the other main surface of the semiconductor element facing away from the one main surface, there are provided substrate connection terminals among the plurality of external connection terminals that are connected to a mounting substrate on which the semiconductor element is mounted. On a second main surface of the first metal plate facing away from the first main surface, there is provided a bonding preparation area for bonding to a second metal plate, and the first main surface is the main surface connected to the semiconductor element. In a plan view of the first metal plate, the bonding preparation area does not overlap with a connection area where the first metal plate and the semiconductor element are connected. The potential of the first metal plate is the same as that of at least one of the plurality of external connection terminals. The first metal plate can be bent at the portion with a thickness of 0.2 mm or less to have a portion where the second main surfaces face each other.

[0013] An electric storage pack according to an embodiment of the present disclosure includes the semiconductor device, the second metal plate, the mounting substrate, and an electric storage unit. The second metal plate is an electric storage sheet that is connected to the electric storage unit and serves as a conduction path for charging the electric storage unit or discharging from the electric storage unit. The first metal plate is a metal plate for bonding to the electric storage sheet. The mounting substrate is a protection circuit substrate that protects the electric storage unit against overcharging or over-discharging. From the electric storage unit, the conduction path is formed in the order of the electric storage sheet, the metal plate for bonding to the electric storage sheet, and the semiconductor element or in the reverse order.

[0014] An electric storage pack according to an embodiment of the present disclosure includes the semiconductor device, the second metal plate, the mounting substrate, and an electric storage unit. The second metal plate is bonded to the first metal plate in the bonding preparation area. The second metal plate is connected to the electric storage unit and is an electric storage sheet that serves as a conduction path for charging the electric storage unit or discharging from the electric storage unit. The first metal plate is a metal plate for bonding to the electric storage sheet. The mounting substrate is a protection circuit substrate that protects the electric storage unit against overcharging or over-discharging. From the electric storage unit, a current path through which current flows is formed in the order of the electric storage sheet, the metal plate for bonding to the electric storage sheet, and the semiconductor element or in the reverse order. The semiconductor element is a switching element. The switching element controls the charging of the electric storage unit or the discharging from the electric storage unit in the protection circuit substrate.

[0015] The power storage pack according to an embodiment of the present disclosure includes: the first semiconductor device and the second semiconductor device; a fourth metal plate as the second metal plate, which is joined to the joining preparation region in the first semiconductor device; a fifth metal plate as the second metal plate, which is joined to the joining preparation region in the second semiconductor device; the mounting substrate on which a first semiconductor element as the semiconductor element in the first semiconductor device and a second semiconductor element as the semiconductor element in the second semiconductor device are mounted; and a power storage unit; the fourth metal plate is a first power storage sheet connected to the positive terminal of the power storage unit; the fifth metal plate is a second power storage sheet connected to the negative terminal of the power storage unit; the mounting substrate is a protection circuit substrate for protecting the power storage unit against overcharging or over-discharging; the first metal plate in the first semiconductor device is a first power storage sheet joining metal plate joined to the first power storage sheet; the first metal plate in the second semiconductor device is a second power storage sheet joining metal plate joined to the second power storage sheet; the first semiconductor element is a first switching element; the second semiconductor element is a second switching element; a current path through which current flows is formed from the power storage unit in the order of the first power storage sheet, the first power storage sheet joining metal plate, and the first semiconductor element or in the reverse order thereof; a current path through which current flows is formed from the power storage unit in the order of the second power storage sheet, the second power storage sheet joining metal plate, and the second semiconductor element or in the reverse order thereof; the first switching element and the second switching element control charging of the power storage unit or discharging from the power storage unit in the protection circuit substrate; the substrate connection terminals in the first switching element are plural; the substrate connection terminals in the second switching element are plural; the power storage pack further includes: a first wiring, which is provided on the protection circuit substrate and has the same potential as the first power storage sheet, and is connected to one of the substrate connection terminals of the first switching element, i.e., a first substrate connection terminal; a second wiring, which is the second wiring provided on the protection circuit substrate, and is connected to one other than the first substrate connection terminal of the substrate connection terminals of the first switching element; a power storage pack positive terminal, which is connected to the second wiring; a third wiring, which is provided on the protection circuit substrate and has the same potential as the second power storage sheet, and is connected to one of the substrate connection terminals of the second switching element, i.e., a second substrate connection terminal; a fourth wiring, which is the fourth wiring provided on the protection circuit substrate, and is connected to one other than the second substrate connection terminal of the substrate connection terminals of the second switching element; and a power storage pack negative terminal, which is connected to the fourth wiring.

[0016] The power storage battery pack according to an embodiment of the present disclosure includes: the first semiconductor device; a fourth metal plate serving as the second metal plate, which is joined to the joining preparation region of the first semiconductor device; the mounting substrate on which a first semiconductor element serving as the semiconductor element in the first semiconductor device is mounted; a second semiconductor element of a chip scale package type, which is mounted face down on the mounting substrate; a power storage unit; a second power storage sheet connected to the positive terminal of the power storage unit; and a metal plate for joining the second power storage sheet, which is connected to the second semiconductor element with a third main surface and joined to the second power storage sheet with a fourth main surface facing away from the third main surface, and has a thickness of 0.A portion of 2 mm or less; the fourth metal plate is a first storage electrode plate connected to the negative terminal of the storage battery unit; the mounting substrate is a protection circuit substrate that protects the storage battery unit against overcharging or over-discharging; the first metal plate in the first semiconductor device is a first storage electrode plate bonding metal plate bonded to the first storage electrode plate; the first semiconductor element is a first switching element; the second semiconductor element is a second switching element; a current path through which current flows is formed from the storage battery unit in the order of the first storage electrode plate, the first storage electrode plate bonding metal plate, and the first semiconductor element or in the reverse order thereof; a current path through which current flows is formed from the storage battery unit in the order of the second storage electrode plate, the second storage electrode plate bonding metal plate, and the protection circuit substrate or in the reverse order thereof; in a plan view of the protection circuit substrate, there is an overlapping portion, which is a portion where the second storage electrode plate, the second storage electrode plate bonding metal plate, the second semiconductor element, and the protection circuit substrate overlap; in the plan view of the protection circuit substrate, there is a portion where a region capable of allowing current to flow between the second storage electrode plate and the protection circuit substrate overlaps with the overlapping portion; the second storage electrode plate bonding metal plate is bent to have portions where the fourth main surfaces face each other; in the plan view of the second storage electrode plate bonding metal plate in the state before bending, the region where the second storage electrode plate bonding metal plate is bonded to the second storage electrode plate does not overlap with the region where the second storage electrode plate bonding metal plate is connected to the second semiconductor element; the first switching element and the second switching element control charging of the storage battery unit or discharging from the storage battery unit in the protection circuit substrate; the substrate connection terminals in the first switching element are plural; the storage battery pack further includes: a first wiring provided on the protection circuit substrate and having the same potential as the first storage electrode plate, which is connected to one of the substrate connection terminals of the first switching element, i.e., the first substrate connection terminal; a second wiring provided on the protection circuit substrate, which is connected to one of the substrate connection terminals of the first switching element other than the first substrate connection terminal; a third wiring provided on the protection circuit substrate, which is connected to the second wiring via the second switching element; a storage battery pack negative terminal connected to the third wiring; a fourth wiring provided on the protection circuit substrate and having the same potential as the second storage electrode plate; and a storage battery pack positive terminal connected to the fourth wiring.

[0017] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes: a first step of connecting a semiconductor element to a first main surface of a first metal plate; a second step of mounting the semiconductor element on a mounting substrate after the first step; a third step of joining a second metal plate to a second main surface of the first metal plate opposite to the first main surface after the second step; a fourth step of bending the first metal plate after the third step so that (1) the second main surfaces face each other, and (2) in a plan view of the semiconductor element, an area where the first metal plate and the semiconductor element are connected and an area where the first metal plate and the second metal plate are joined have an overlapping portion separated by the first metal plate; and a fifth step of bending the second metal plate after the third step so that the second metal plate has a portion where the surfaces joined to the first metal plate face each other.

[0018] Effects of the Invention

[0019] According to a power storage pack, a semiconductor device, and a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, a power storage pack, a semiconductor device, and a method for manufacturing the semiconductor device are provided, which enable miniaturization of a protection circuit substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a plan view showing the structure of the power storage pack according to the first embodiment.

[0021] Figure 2A This is a cross-sectional view showing the structure of the power storage pack according to the first embodiment.

[0022] Figure 2B This is a cross-sectional view showing the structure of the power storage pack according to the first embodiment.

[0023] Figure 3 This is a circuit diagram showing a first semiconductor element according to the first embodiment.

[0024] Figure 4 This is a cross-sectional view showing an example of the structure of the first semiconductor element according to the first embodiment.

[0025] Figure 5 This is a plan view showing an example of the structure of the first semiconductor element in the first embodiment.

[0026] Figure 6 This is an example of a plan view showing the first metal plate according to the first embodiment.

[0027] Figure 7 This is another example of the plan view of the first metal plate in the first embodiment.

[0028] Figure 8It is a plan view of the first semiconductor device of Embodiment 1.

[0029] Figure 9 It is a plan view of the first semiconductor device of Embodiment 1.

[0030] Figure 10 It is a plan view of the first semiconductor device of Embodiment 1.

[0031] Figure 11 It is a diagram for explaining the vicinity of each corner of the first semiconductor element of Embodiment 1.

[0032] Figure 12 It is a circuit diagram of the power storage pack of Embodiment 1.

[0033] Figure 13 It is a cross-sectional view of the protection circuit board and the first semiconductor element of Embodiment 1.

[0034] Figure 14 It is a cross-sectional view of the protection circuit board and the first semiconductor element of Embodiment 1.

[0035] Figure 15 It is a plan view showing the structure of the power storage pack of Embodiment 2.

[0036] Figure 16A It is a cross-sectional view showing the structure of the power storage pack of Embodiment 2.

[0037] Figure 16B It is a cross-sectional view showing the structure of the power storage pack of Embodiment 2.

[0038] Figure 17 It is a plan view showing the structure of the power storage pack of Embodiment 3.

[0039] Figure 18A It is a cross-sectional view showing the structure of the power storage pack of Embodiment 3.

[0040] Figure 18B It is a cross-sectional view showing the structure of the power storage pack of Embodiment 3.

[0041] Figure 19 It is a plan view showing the structure of the power storage pack of Embodiment 4.

[0042] Figure 20A It is a cross-sectional view showing the structure of the power storage pack of Embodiment 4.

[0043] Figure 20B It is a cross-sectional view showing the structure of the power storage pack of Embodiment 4.

[0044] Figure 21 It is a plan view showing the structure of the power storage pack of Embodiment 5.

[0045] Figure 22A It is a cross-sectional view showing the structure of the electricity storage pack of Embodiment 5.

[0046] Figure 22B It is a cross-sectional view showing the structure of the electricity storage pack of Embodiment 5.

[0047] Figure 23 It is a circuit diagram of the first semiconductor element of Embodiment 5.

[0048] Figure 24 It is a circuit diagram of the electricity storage pack of Embodiment 5.

[0049] Figure 25A It is a circuit diagram of other structures of the electricity storage pack of Embodiment 5.

[0050] Figure 25B It is a circuit diagram of other structures of the electricity storage pack of Embodiment 5.

[0051] Figure 26 It is a circuit diagram of the first semiconductor element of Modification 1.

[0052] Figure 27 It is a circuit diagram of the electricity storage pack of Modification 1.

[0053] Figure 28 It is a circuit diagram of the electricity storage pack of Modification 2.

[0054] Figure 29 It is a circuit diagram of the electricity storage pack of Modification 3.

[0055] Figure 30 It is a plan view showing the structure of the electricity storage pack of Embodiment 6.

[0056] Figure 31A It is a cross-sectional view showing the structure of the electricity storage pack of Embodiment 6.

[0057] Figure 31B It is a cross-sectional view showing the structure of the electricity storage pack of Embodiment 6.

[0058] Figure 32 It is a circuit diagram of the electricity storage pack of Embodiment 6.

[0059] Figure 33A It is a cross-sectional view of the first semiconductor device during the manufacturing process of the zeroth process of the manufacturing method of the semiconductor device.

[0060] Figure 33B It is a cross-sectional view of the first semiconductor device during the manufacturing process of the first process of the manufacturing method of the semiconductor device.

[0061] Figure 33C It is a cross-sectional view of the first semiconductor device during the manufacturing process of the second process of the manufacturing method of the semiconductor device.

[0062] Figure 33D This is a cross-sectional view of the first semiconductor device during the third step of the semiconductor device manufacturing method.

[0063] Figure 33E This is a cross-sectional view of the first semiconductor device during the fourth step of the semiconductor device manufacturing method.

[0064] Figure 33F This is a cross-sectional view of the first semiconductor device during the fifth step of the semiconductor device manufacturing method.

[0065] Figure 34 This is a cross-sectional view showing another structure of the power storage pack according to the sixth embodiment.

[0066] Figure 35A This is a cross-sectional view showing another structure of the power storage pack according to the third embodiment.

[0067] Figure 35B This is a cross-sectional view showing another structure of the power storage pack according to the third embodiment. DETAILED DESCRIPTION

[0068] (How One Embodiment of the Present Disclosure Was Obtained)

[0069] The inventors have developed a semiconductor device for use in a power storage pack. Through this development, the inventors have conducted repeated and intensive experiments and research to minimize the size of the protective circuit board included in the power storage pack. As a result, the inventors have developed the power storage pack, the semiconductor device, and the method for manufacturing the semiconductor device, described below, according to one embodiment of the present disclosure.

[0070] A storage pack according to one embodiment of the present disclosure comprises: a storage cell; a storage cell connected to the storage cell to form a conductive path for charging or discharging the storage cell; a protective circuit substrate to protect the storage cell against overcharging or overdischarging; a chip-size package-type semiconductor element mounted face down on the protective circuit substrate; and a metal plate for bonding the storage cell, connected to the semiconductor element through a first main surface and having a portion with a thickness of less than 0.2 mm; the metal plate for bonding the storage cell is bonded to the storage cell through a second main surface opposite to the first main surface, so that in a plan view of the protective circuit substrate, there is an overlapping portion in which the storage cell, the metal plate for bonding the storage cell, the semiconductor element and the protective circuit substrate overlap; in a plan view of the protective circuit substrate, there is a portion in which an area capable of forming the conductive path between the storage cell and the protective circuit substrate overlaps with the overlapping portion.

[0071] In conventional power storage packs, power storage sheets connected to power storage cells are connected to a protection circuit board on which semiconductor elements are mounted.

[0072] In contrast, in the power storage pack according to an embodiment of the present disclosure described above, the power storage sheet connected to the power storage cell is joined to a power storage sheet joining metal plate to which the semiconductor element mounted on the protection circuit board is connected.

[0073] Therefore, in the power storage pack according to an embodiment of the present disclosure described above, there is no need for an area in the protection circuit board for connecting the power storage sheet, which is required in conventional power storage packs.

[0074] Thus, in the power storage pack according to an embodiment of the present disclosure described above, miniaturization of the protection circuit board can be achieved.

[0075] In addition, in this specification, the term "join" means a state of physically contacting and connecting regardless of whether it is direct or indirect, and means a state where disassembly is not easy. Further, in this specification, the term "connect" means a connected state that includes non-physical (e.g., electrical) connection in addition to the meaning of the term "join".

[0076] Furthermore, it may be that the power storage sheet joining metal plate is bent at a portion having a thickness of 0.2 mm or less to have a portion where the second main surfaces face each other with the power storage sheet therebetween; in a plan view of the power storage sheet joining metal plate in a state before bending, an area where the power storage sheet joining metal plate is joined to the power storage sheet and an area where the power storage sheet joining metal plate is connected to the semiconductor element do not overlap.

[0077] In the power storage pack having the above structure, in a plan view of the power storage sheet joining metal plate in a state before bending, an area where the power storage sheet joining metal plate is joined to the power storage sheet and an area where the power storage sheet joining metal plate is connected to the semiconductor element are separated. Therefore, it is possible to suppress an adverse effect of heat generated when joining the power storage sheet joining metal plate to the power storage sheet on the semiconductor element, and an adverse effect of a physical impact generated when joining the power storage sheet joining metal plate to the power storage sheet on the semiconductor element.

[0078] Furthermore, by bending the power storage sheet joining metal plate, miniaturization of the power storage pack itself can be achieved.

[0079] In addition, it may be that the semiconductor element is a switching element, and the switching element controls charging from or discharging to the power storage cell in the protection circuit board.

[0080] Thereby, it is possible to use the semiconductor element to achieve a protection function for protecting the power storage cell against overcharge or over-discharge.

[0081] A semiconductor device according to an embodiment of the present disclosure includes: a chip scale package type semiconductor element having a plurality of external connection terminals; and a first metal plate having a portion with a thickness of 0.2 mm or less; the first metal plate is connected to one main surface of the semiconductor element; on the other main surface of the semiconductor element facing away from the one main surface, there are provided substrate connection terminals among the plurality of external connection terminals that are connected to a mounting substrate on which the semiconductor element is mounted; on a second main surface of the first metal plate facing away from the first main surface, there is provided a joining preparation area for joining with a second metal plate, and the first main surface is the main surface of the first metal plate that is connected to the semiconductor element; in a plan view of the first metal plate, the joining preparation area does not overlap with a connection area where the first metal plate and the semiconductor element are connected; the potential of the first metal plate is the same as the potential of at least one of the plurality of external connection terminals; the first metal plate can be bent at the portion with a thickness of 0.2 mm or less to have a portion where the second main surfaces face each other.

[0082] As described above, in a conventional power storage battery pack, a power storage sheet connected to a power storage unit is connected to a protection circuit board on which a semiconductor element is mounted.

[0083] In contrast, according to the semiconductor device of an embodiment of the present disclosure, the semiconductor element is mounted on a protection circuit board as a mounting substrate, and a power storage sheet as a second metal plate is joined to the joining preparation area of the first metal plate, thereby enabling a power storage battery pack to be realized.

[0084] In this power storage battery pack, a power storage sheet connected to a power storage unit is joined to a power storage sheet joining metal plate to which a semiconductor element mounted on a protection circuit board is connected.

[0085] Therefore, according to the semiconductor device of an embodiment of the present disclosure, there is no need for an area in the protection circuit board for connecting the power storage sheet, which is required in a conventional power storage battery pack.

[0086] Thus, according to the semiconductor device of an embodiment of the present disclosure, miniaturization of the protection circuit board can be achieved.

[0087] Furthermore, according to the semiconductor device of an embodiment of the present disclosure, in a plan view of the first metal plate, since the joining preparation area is separated from the connection area, it is possible to suppress adverse effects of heat generated when joining the first metal plate and the power storage sheet as the second metal plate on the semiconductor element, and adverse effects of physical impact generated when joining the first metal plate and the power storage sheet on the semiconductor element.

[0088] Furthermore, by joining the power storage sheet, which is the second metal plate, to the first metal plate, heat dissipation can be achieved using the power storage sheet, thereby improving the heat dissipation performance.

[0089] In addition, it may be that one or more metal components that are mounted on the mounting substrate together with the semiconductor element when the semiconductor element is mounted on the mounting substrate are further provided on the first main surface; in a plan view of the first metal plate, the regions where the first main surface is connected to the one or more metal components do not overlap with the bonding preparation regions.

[0090] In addition, it may be that the first metal plate can be bent at a portion having a thickness of 0.2 mm or less at the bending axis so as to have a portion where the second main surfaces face each other; in a plan view of the first metal plate, the bonding preparation region and the connection region are located on one side and the other side across the bending axis.

[0091] In addition, it may be that the first metal plate can be bent at a portion having a thickness of 0.2 mm or less at the bending axis so as to have a portion where the second main surfaces face each other; in a plan view of the semiconductor element, the semiconductor element is a rectangle having a first side; the semiconductor element is connected to the first metal plate with the first side orthogonal to the bending axis; the length of the first metal plate in the direction orthogonal to the bending axis in the plan view of the first metal plate is 2 times or more the length of the first side in the plan view of the semiconductor element.

[0092] In addition, it may be that the first metal plate can be bent at a portion having a thickness of 0.2 mm or less at the bending axis so as to have a portion where the second main surfaces face each other; in a plan view of the first metal plate, the first metal plate is a substantially rectangle having a first substantially linear side and a second substantially linear side extending in a direction orthogonal to the bending axis; in a plan view of the first metal plate, the first substantially linear side and the second substantially linear side each have a concave portion recessed inwardly of the first metal plate.

[0093] Thus, the bending of the first metal plate at the concave portion becomes relatively easy.

[0094] In addition, it may be that the one or more metal components are made of the same material as the first metal plate, and the one or more metal components and the first metal plate are integrated.

[0095] In addition, it is possible that a third metal plate is further provided between the semiconductor element and the first metal plate; the third metal plate is connected to the semiconductor element in the one main surface and is connected to the first metal plate in the first main surface; the first metal plate is connected to the one main surface via the third metal plate.

[0096] In addition, it is possible that on the main surface of the third metal plate where the third metal plate is connected to the semiconductor element, one or more metal components that are mounted on the mounting substrate together with the semiconductor element when the semiconductor element is mounted on the mounting substrate are provided, and in a plan view of the first metal plate, the regions of the main surface that are connected to the one or more metal components do not overlap with the bonding preparation regions.

[0097] In addition, it is possible that the first metal plate is bent to have a portion where the second main surfaces face each other, and in a plan view of the semiconductor element, there is a portion where the semiconductor element and the bonding preparation region overlap with each other with the first metal plate therebetween.

[0098] Thus, the first metal plate is bent, enabling miniaturization of the semiconductor device.

[0099] In addition, it is possible that the semiconductor element is mounted on the mounting substrate face down via the substrate connection terminal, and the first metal plate is bonded to the second metal plate in the bonding preparation region.

[0100] In addition, it is possible that the semiconductor element is mounted on the mounting substrate face down via the substrate connection terminal; the first metal plate is bonded to the second metal plate in the bonding preparation region; the second metal plate is bent to have a portion where the surfaces bonded to the first metal plate face each other with the first metal plate therebetween; in a plan view of the mounting substrate, there is an overlapping portion where the second metal plate, the first metal plate, the semiconductor element, and the mounting substrate overlap; and in a plan view of the mounting substrate, there is a portion where a region where current can flow between the second metal plate and the mounting substrate overlaps with the overlapping portion.

[0101] The power storage battery pack according to an embodiment of the present disclosure includes the semiconductor device, the second metal plate, the mounting substrate, and the power storage unit; the second metal plate is a power storage sheet that is connected to the power storage unit and serves as a conduction path for charging the power storage unit or discharging from the power storage unit; the first metal plate is a metal plate for bonding the power storage sheet that is bonded to the power storage sheet; the mounting substrate is a protection circuit substrate that protects the power storage unit against overcharging or over-discharging; from the power storage unit, the conduction path is formed in the order of the power storage sheet, the metal plate for bonding the power storage sheet, and the semiconductor element or the reverse order thereof.

[0102] As described above, in the conventional power storage battery pack, the power storage sheet connected to the power storage unit is connected to the protection circuit substrate on which the semiconductor element is mounted.

[0103] In contrast, in the power storage battery pack according to an embodiment of the present disclosure, the power storage sheet connected to the power storage unit is bonded to the metal plate for bonding the power storage sheet to which the semiconductor element mounted on the protection circuit substrate is connected.

[0104] Therefore, in the power storage battery pack according to an embodiment of the present disclosure, the area in the protection circuit substrate for connecting the power storage sheet, which is required in the conventional power storage battery pack, is not required.

[0105] Thus, in the power storage battery pack according to an embodiment of the present disclosure, miniaturization of the protection circuit substrate can be achieved.

[0106] In addition, it may be that the one or more metal components are connected to the protection circuit substrate.

[0107] In addition, in a plan view of the semiconductor element, the semiconductor element may be rectangular and have two sides in a direction parallel to the length direction of the protection circuit substrate; the one or more metal components include two metal components arranged opposite to each other along the two sides over at least the entire length of the two sides.

[0108] Thereby, a part of the stress acting on the semiconductor element is dispersed to the two metal components. Therefore, the semiconductor element is difficult to peel off from the protection circuit substrate. In addition, the pressure resistance against the pressure from the second main surface side of the first metal plate can be improved for one main surface of the semiconductor element.

[0109] In addition, in a plan view of the semiconductor element, the semiconductor element may be rectangular and have two sides in a direction orthogonal to the length direction of the protection circuit substrate, and the one or more metal components include two metal components arranged opposite to each other along the two sides over at least the entire length of the two sides.

[0110] Accordingly, a part of the stress applied to the semiconductor element is dispersed to the two metal components. Therefore, it is difficult for the semiconductor element to peel off from the protective circuit board. In addition, it is possible to improve the pressure resistance against the pressure from the second main surface side of the first metal plate for one main surface of the semiconductor element.

[0111] In addition, in the plan view of the semiconductor element, the semiconductor element may be rectangular, and the one or more metal components may include four metal components arranged near respective four corners of the semiconductor element.

[0112] Accordingly, a part of the stress applied to the semiconductor element is dispersed to the four metal components. Therefore, it is difficult for the semiconductor element to peel off from the protective circuit board. In addition, it is possible to improve the pressure resistance against the pressure from the second main surface side of the first metal plate for one main surface of the semiconductor element.

[0113] In addition, the semiconductor element may be a switching element, and the switching element controls charging to or discharging from the power storage unit in the protective circuit board.

[0114] Accordingly, it is possible to use the semiconductor element to implement a protection function for protecting the power storage unit against overcharging or over-discharging.

[0115] In addition, in the plan view of the switching element, the switching element may have, on the other main surface side, a plurality of regions including a first region and a second region adjacent to each other that divide the switching element; the switching element further includes: a first vertical MOS transistor formed in the first region; and a second vertical MOS transistor formed in the second region; the substrate connection terminals are plural; the first vertical MOS transistor has, on the other main surface, a first source terminal as the substrate connection terminal and a first gate terminal as the substrate connection terminal to control the conduction state of the first vertical MOS transistor; the second vertical MOS transistor has, on the other main surface, a second source terminal as the substrate connection terminal and a second gate terminal as the substrate connection terminal to control the conduction state of the second vertical MOS transistor; the switching element further has, on one main surface, a drain electrode common to the first vertical MOS transistor and the second vertical MOS transistor; the drain electrode is connected to the metal plate for bonding the power storage sheet via an insulating bonding member; at least one of the one or more metal components is connected to only the first source terminal among the substrate connection terminals via a wiring formed in the protective circuit board.

[0116] Accordingly, it is possible to use a semiconductor element to implement a protection function of the power storage unit for charging or discharging the power storage unit due to the current flowing from the power storage sheet to the protection circuit board, and a protection function of the power storage unit for charging or discharging the power storage unit due to the current flowing from the protection circuit board to the power storage sheet.

[0117] In addition, it may be that the above-mentioned substrate connection terminals are multiple; the above-mentioned switching element is a vertical MOS transistor, which has a source terminal as the above-mentioned substrate connection terminal and a gate terminal as the above-mentioned substrate connection terminal on the other main surface, and has a drain electrode as the above-mentioned external connection terminal on the one main surface; the drain electrode is connected to the metal plate for bonding the power storage sheet via a conductive bonding member.

[0118] Accordingly, it is possible to use a semiconductor element to implement a protection function of the power storage unit for charging or discharging the power storage unit due to the current flowing from the power storage sheet to the protection circuit board, and a protection function of the power storage unit for charging or discharging the power storage unit due to the current flowing from the protection circuit board to the power storage sheet.

[0119] A power storage pack according to an embodiment of the present disclosure includes the above-mentioned semiconductor device, the above-mentioned second metal plate, the above-mentioned mounting substrate, and the power storage unit; the above-mentioned second metal plate is bonded to the above-mentioned first metal plate in the above-mentioned bonding preparation area; the above-mentioned second metal plate is connected to the above-mentioned power storage unit and is a power storage sheet that forms a conduction path for charging or discharging the above-mentioned power storage unit; the above-mentioned first metal plate is a metal plate for bonding the power storage sheet that is bonded to the above-mentioned power storage sheet; the above-mentioned mounting substrate is a protection circuit board that protects the above-mentioned power storage unit against overcharging or over-discharging; a current path for current flow is formed from the above-mentioned power storage unit in the order of the above-mentioned power storage sheet, the above-mentioned metal plate for bonding the power storage sheet, and the above-mentioned semiconductor element or in the reverse order thereof; the above-mentioned semiconductor element is a switching element; the above-mentioned switching element controls the charging or discharging of the above-mentioned power storage unit in the above-mentioned protection circuit board.

[0120] As described above, in a conventional power storage pack, the power storage sheet connected to the power storage unit is connected to a protection circuit board on which a semiconductor element is mounted.

[0121] In contrast, according to the power storage pack of an embodiment of the present disclosure, the power storage sheet connected to the power storage unit is bonded to a metal plate for bonding the power storage sheet to which the semiconductor element mounted on the protection circuit board is connected.

[0122] Therefore, according to the electricity storage pack of an embodiment of the present disclosure described above, there is no need for an area in the protection circuit board that is required in a conventional electricity storage pack for connecting electricity storage sheets.

[0123] Thus, according to the electricity storage pack of an embodiment of the present disclosure described above, miniaturization of the protection circuit board can be achieved.

[0124] Furthermore, according to the electricity storage pack of an embodiment of the present disclosure described above, the protection function of the electricity storage unit can be realized by using semiconductor elements.

[0125] The electricity storage battery pack according to an embodiment of the present disclosure includes: the first semiconductor device and the second semiconductor device; a fourth metal plate as the second metal plate, which is joined to the joining preparation region in the first semiconductor device; a fifth metal plate as the second metal plate, which is joined to the joining preparation region in the second semiconductor device; the mounting substrate on which a first semiconductor element as the semiconductor element in the first semiconductor device and a second semiconductor element as the semiconductor element in the second semiconductor device are mounted; and an electricity storage unit; the fourth metal plate is a first electricity storage piece connected to the positive terminal of the electricity storage unit; the fifth metal plate is a second electricity storage piece connected to the negative terminal of the electricity storage unit; the mounting substrate is a protection circuit substrate for protecting the electricity storage unit against overcharging or over-discharging; the first metal plate in the first semiconductor device is a first electricity storage piece joining metal plate joined to the first electricity storage piece; the first metal plate in the second semiconductor device is a second electricity storage piece joining metal plate joined to the second electricity storage piece; the first semiconductor element is a first switching element; the second semiconductor element is a second switching element; a current path through which current flows is formed from the electricity storage unit in the order of the first electricity storage piece, the first electricity storage piece joining metal plate, and the first semiconductor element or in the reverse order thereof; a current path through which current flows is formed from the electricity storage unit in the order of the second electricity storage piece, the second electricity storage piece joining metal plate, and the second semiconductor element or in the reverse order thereof; the first switching element and the second switching element control charging to the electricity storage unit or discharging from the electricity storage unit in the protection circuit substrate; the substrate connection terminals in the first switching element are multiple; the substrate connection terminals in the second switching element are multiple; the electricity storage battery pack further includes: a first wiring which is provided on the protection circuit substrate and has the same potential as the first electricity storage piece, and is connected to one of the substrate connection terminals in the first switching element, namely a first substrate connection terminal; a second wiring which is the second wiring provided on the protection circuit substrate and is connected to one other than the first substrate connection terminal among the substrate connection terminals in the first switching element; a positive terminal of the electricity storage battery pack, which is connected to the second wiring; a third wiring which is provided on the protection circuit substrate and has the same potential as the second electricity storage piece, and is connected to one of the substrate connection terminals in the second switching element, namely a second substrate connection terminal; a fourth wiring which is the fourth wiring provided on the protection circuit substrate and is connected to one other than the second substrate connection terminal among the substrate connection terminals in the second switching element; and a negative terminal of the electricity storage battery pack, which is connected to the fourth wiring.

[0126] In a conventional power storage battery pack, a first power storage sheet connected to the positive terminal of the power storage unit and a second power storage sheet connected to the negative terminal of the power storage unit are respectively connected to a protection circuit board on which a first semiconductor element and a second semiconductor element are mounted.

[0127] In contrast, in the power storage battery pack according to an embodiment of the present disclosure, the first power storage sheet connected to the positive terminal of the power storage unit is joined to a first power storage sheet joining metal plate to which the first semiconductor element mounted on the protection circuit board is connected, and the second power storage sheet connected to the negative terminal of the power storage unit is joined to a second power storage sheet joining metal plate to which the second semiconductor element mounted on the protection circuit board is connected.

[0128] Therefore, in the power storage battery pack according to an embodiment of the present disclosure, there is no need for the areas in the protection circuit board for connecting the first power storage sheet and for connecting the second power storage sheet, which are required in a conventional power storage battery pack.

[0129] Thus, in the power storage battery pack according to an embodiment of the present disclosure, miniaturization of the protection circuit board can be achieved.

[0130] Furthermore, in the power storage battery pack according to an embodiment of the present disclosure, by using the first semiconductor element and the second semiconductor element, a dual protection function for each of the power storage units can be achieved for the current path on the high side of the power storage unit and the current path on the low side of the power storage unit.

[0131] The electricity storage battery pack according to an embodiment of the present disclosure includes: the first semiconductor device; a fourth metal plate as the second metal plate, which is joined to the joining preparation region of the first semiconductor device; the mounting substrate on which a first semiconductor element as the semiconductor element in the first semiconductor device is mounted; a second semiconductor element of a chip scale package type, which is mounted on the mounting substrate with its face facing downward; an electricity storage unit; a second electricity storage sheet connected to the positive terminal of the electricity storage unit; and a metal plate for joining the second electricity storage sheet, which is connected to the second semiconductor element with its third main surface and joined to the second electricity storage sheet with its fourth main surface facing away from the third main surface, and has a thickness of 0.A portion of 2 mm or less; the fourth metal plate is a first power storage sheet connected to the negative terminal of the power storage unit; the mounting substrate is a protection circuit substrate that protects the power storage unit against overcharging or over-discharging; the first metal plate in the first semiconductor device is a first power storage sheet bonding metal plate bonded to the first power storage sheet; the first semiconductor element is a first switching element; the second semiconductor element is a second switching element; from the power storage unit, a current path for current flow is formed in the order of the first power storage sheet, the first power storage sheet bonding metal plate, and the first semiconductor element or in the reverse order thereof, and from the power storage unit, a current path for current flow is formed in the order of the second power storage sheet, the second power storage sheet bonding metal plate, and the protection circuit substrate or in the reverse order thereof; in a plan view of the protection circuit substrate, there is an overlapping portion, which is a portion where the second power storage sheet, the second power storage sheet bonding metal plate, the second semiconductor element, and the protection circuit substrate overlap; in a plan view of the protection circuit substrate, there is a portion where a region capable of allowing current to flow between the second power storage sheet and the protection circuit substrate overlaps with the overlapping portion; the second power storage sheet bonding metal plate is bent to have portions where the fourth main surfaces face each other; in a plan view of the second power storage sheet bonding metal plate in a state before bending, a region where the second power storage sheet bonding metal plate is bonded to the second power storage sheet does not overlap with a region where the second power storage sheet bonding metal plate is connected to the second semiconductor element; the first switching element and the second switching element control charging of the power storage unit or discharging from the power storage unit in the protection circuit substrate; the substrate connection terminals in the first switching element are multiple; the power storage pack further includes: a first wiring, which is a first wiring provided on the protection circuit substrate and having the same potential as the first power storage sheet, and is connected to one of the substrate connection terminals of the first switching element, namely the first substrate connection terminal; a second wiring, which is a second wiring provided on the protection circuit substrate and is connected to one of the substrate connection terminals of the first switching element other than the first substrate connection terminal; a third wiring, which is a third wiring provided on the protection circuit substrate and is connected to the second wiring via the second switching element; a power storage pack negative terminal, which is connected to the third wiring; a fourth wiring, which is provided on the protection circuit substrate and has the same potential as the second power storage sheet; and a power storage pack positive terminal, which is connected to the fourth wiring.

[0132] In a conventional power storage pack, a first power storage sheet connected to the positive terminal of the power storage unit and a second power storage sheet connected to the negative terminal of the power storage unit are respectively connected to a protection circuit substrate on which a first semiconductor element and a second semiconductor element are mounted.

[0133] In contrast, in the storage pack according to one embodiment of the present disclosure, the first storage cell connected to the positive terminal of the storage unit is joined to a first storage cell joining metal plate connected to a first semiconductor element mounted on a protection circuit substrate, and the second storage cell connected to the negative terminal of the storage unit is joined to a second storage cell joining metal plate connected to a second semiconductor element mounted on the protection circuit substrate.

[0134] Therefore, according to the power storage pack of one embodiment of the present disclosure, the areas for connecting the first power storage cell and the areas for connecting the second power storage cell in the protection circuit board, which are required in conventional power storage packs, are unnecessary.

[0135] Therefore, according to the power storage pack according to one embodiment of the present disclosure, the protection circuit board can be miniaturized.

[0136] Furthermore, according to the power storage pack of one embodiment of the present disclosure, the first semiconductor element and the second semiconductor element can realize a dual protection function of the power storage cell using only the low-side current path of the power storage cell.

[0137] A method for manufacturing a semiconductor device according to an embodiment of the present disclosure includes: a first step of connecting a semiconductor element to a first main surface of a first metal plate; a second step of mounting the semiconductor element on a mounting substrate after the first step; a third step of joining a second metal plate to a second main surface of the first metal plate opposite to the first main surface after the second step; a fourth step of bending the first metal plate after the third step so that (1) the second main surfaces face each other, and (2) in a plan view of the semiconductor element, an area where the first metal plate and the semiconductor element are connected and an area where the first metal plate and the second metal plate are joined have an overlapping portion separated by the first metal plate; and a fifth step of bending the second metal plate after the third step so that the second metal plate has a portion where the surfaces joined to the first metal plate face each other.

[0138] As described above, in a conventional power storage pack, the power storage chip connected to the power storage cell is connected to a protection circuit substrate on which a semiconductor element is mounted.

[0139] In contrast, according to the semiconductor device manufacturing method of one embodiment of the present disclosure, the semiconductor element is mounted on a protective circuit substrate as a mounting substrate, and a storage cell sheet as a second metal plate is connected to the second main surface to realize a storage pack.

[0140] In this power storage pack, the power storage tab connected to the power storage unit is joined to a power storage tab joining metal plate connected to a semiconductor element mounted on a protection circuit board.

[0141] Therefore, according to the manufacturing method of the semiconductor device according to an embodiment of the present disclosure, there is no need for an area in the protection circuit board for connecting the power storage sheets, which is required in a conventional power storage pack.

[0142] Thus, according to the manufacturing method of the semiconductor device according to an embodiment of the present disclosure, miniaturization of the protection circuit board can be achieved.

[0143] In addition, it may further include a sixth step of connecting a third metal plate having one or more metal components to the semiconductor element before the first step, and in the first step, the semiconductor element is connected to the first main surface via the third metal plate.

[0144] Hereinafter, specific examples of a power storage pack, a semiconductor device, and a manufacturing method of the semiconductor device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. The embodiments shown here are all specific examples of the present disclosure. Therefore, the numerical values, shapes, constituent elements, arrangements and connection forms of the constituent elements, and steps (processes) and the order of steps shown in the following embodiments are shown as examples and are not intended to limit the present disclosure. In addition, each drawing is a schematic diagram and is not necessarily strictly drawn. In each drawing, the same reference numerals are added to substantially the same structures, and repeated explanations are omitted or simplified.

[0145] (Embodiment 1)

[0146] <Structure>

[0147] Hereinafter, the structure of the power storage pack according to Embodiment 1 will be described.

[0148] Figure 1 is a plan view showing the structure of the power storage pack 100 according to Embodiment 1. Figure 2A is showing Figure 1 a cross-sectional view of the cut at I-I. Figure 2B is showing Figure 1 a cross-sectional view of the cut at II-II. Figure 1 In, for a part of the part that cannot be directly recognized in practice, it is shown by a dotted line as if it can be recognized.

[0149] As Figure 1 , Figure 2A , Figure 2B shown, the power storage pack 100 includes a power storage unit 3, a first power storage sheet 80A, a second power storage sheet 80B, a first semiconductor device 1A, a second semiconductor device 1B, and a protection circuit board 60. In addition, in this specification, the first power storage sheet 80A is also referred to as the second metal plate 80A, the second power storage sheet 80B is also referred to as the second metal plate 80B, and the protection circuit board 60 is also referred to as the mounting board 60.

[0150] The power storage unit 3 includes a positive terminal 36 (not shown in Figure 1 , 2A , and 2B, refer to Figure 12 described later), and a negative terminal 37 (not shown in Figure 1 , 2A , and 2B, refer to Figure 12 described later). Electric energy is stored between the positive terminal 36 and the negative terminal 37. The power storage unit 3 can be charged and discharged via the positive terminal 36 and the negative terminal 37. The power storage unit 3 can be, for example, a secondary battery represented by a lithium-ion battery or the like, or can also be a capacitor represented by a lithium-ion capacitor or the like. Hereinafter, it is assumed that the power storage unit 3 is a secondary battery represented by a lithium-ion battery or the like for explanation.

[0151] The first power storage sheet 80A is a metal plate connected to the positive terminal 36 of the power storage unit 3. As a non-limiting example, the first power storage sheet 80A is made of a metal material containing aluminum.

[0152] The second power storage sheet 80B is a metal plate connected to the negative terminal 37 of the power storage unit 3. As a non-limiting example, the second power storage sheet 80B is made of a metal material obtained by nickel-plating a metal material containing copper.

[0153] The first power storage sheet 80A and the second power storage sheet 80B form a part of the conduction path for charging the power storage unit 3 or discharging from the power storage unit 3.

[0154] The first semiconductor device 1A includes a first semiconductor element 2A, a first power storage sheet bonding metal plate 70A, a third metal plate 75A, and one or more metal components 85A. In addition, in this specification, the first power storage sheet bonding metal plate 70A is also referred to as the first metal plate 70A.

[0155] The first semiconductor element 2A is a chip-scale package type semiconductor device having a plurality of external connection terminals (here, corresponding to the first gate terminal 119, the first source terminal 111, the second gate terminal 129, the second source terminal 121, and the drain electrode 30 (not shown in Figure 1 , Figure 2A , for example, refer to Figure 3 , Figure 4 etc.)). Here, the first semiconductor element 2A is mounted on the protection circuit board 60 in a face-down manner via a plurality of substrate connection terminals (here, corresponding to the first gate terminal 119, the first source terminal 111, the second gate terminal 129, and the second source terminal 121) among the plurality of external connection terminals. In addition, in this specification, the drain electrode 30 is also referred to as the metal layer 30.

[0156] The first semiconductor element 2A is a semiconductor device in which one or more vertical MOS (Metal Oxide Semiconductor) transistors are formed. Hereinafter, as an example, it is assumed that the first semiconductor element 2A is a semiconductor device in which two vertical MOS transistors are formed, but the first semiconductor element 2A only needs to be a semiconductor device in which one or more vertical MOS transistors are formed, and it does not need to be limited to a semiconductor device in which two vertical MOS transistors are necessarily formed.

[0157] Figure 3 is the circuit diagram of the first semiconductor element 2A.

[0158] As Figure 3 shown, the first semiconductor element 2A includes a first vertical MOS transistor 10 and a second vertical MOS transistor 20. In addition, the first semiconductor element 2A includes a first gate terminal 119 as a plurality of external connection terminals, one or more first source terminals 111, a second gate terminal 129, one or more second source terminals 121, and a drain electrode 30.

[0159] Figure 4 is a cross-sectional view showing an example of the structure of the first semiconductor element 2A. Figure 5 is a plan view showing an example of the structure of the first semiconductor element 2A. Figure 4 Indicates Figure 5 the cross-sectional view taken along line III-III of

[0160] As Figure 4 and Figure 5 shown, the first semiconductor element 2A has a semiconductor layer 40, a metal layer 30, a first vertical MOS transistor 10 formed in a first region A1 within the semiconductor layer 40, and a second vertical MOS transistor 20 formed in a second region A2 within the semiconductor layer 40. Here, as Figure 4 shown, the first region A1 and the second region A2 are adjacent to each other in the plan view of the semiconductor layer 40.

[0161] The semiconductor layer 40 is formed by laminating a semiconductor substrate 32 and a low-concentration impurity layer 33.

[0162] The semiconductor substrate 32 is disposed on the lower surface side of the semiconductor layer 40 and is made of silicon containing impurities of the first conductivity type.

[0163] The low-concentration impurity layer 33 is disposed on the upper surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and contains impurities of the first conductivity type having a concentration lower than the impurity concentration of the first conductivity type of the semiconductor substrate 32. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32 by epitaxial growth, for example.

[0164] The oxide film 34 is laminated on the upper surface of the semiconductor layer 40 and formed in contact with the low-concentration impurity layer 33.

[0165] The protective layer 35 is formed in contact with a part 13 (described later) of the first source electrode 11 (described later), a part 23 (described later) of the second source electrode 21 (described later), and the upper surface of the oxide film 34, covering at least a part of the upper surfaces of the semiconductor layer 40 and the oxide film 34.

[0166] The metal layer 30 is formed in surface contact with the entire lower surface of the semiconductor substrate 32. Additionally, in the metal layer 30, elements other than metals that are mixed as impurities in the manufacturing process of the metal material may be contained in trace amounts. Here, the metal layer 30 functions as a common drain electrode for the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0167] In addition, as Figure 4 and Figure 5 shown, the first vertical MOS transistor 10 has, on the upper surface of the semiconductor layer 40, one or more (here, six) first source terminals 111 (here, first source terminals 111a, 111b, 111c, 111d, 111e, and 111f) that are joined to the mounting substrate 60 via a conductive material 81 (e.g., solder, refer to Figure 2A ) when face-down mounted, and a first gate terminal 119. In addition, the second vertical MOS transistor 20 has, on the upper surface of the semiconductor layer 40, one or more (here, six) second source terminals 121 (here, second source terminals 121a, 121b, 121c, 121d, 121e, and 121f) that are joined to the mounting substrate 60 via the conductive material 81 when face-down mounted, and a second gate terminal 129.

[0168] As Figure 4 and Figure 5 shown, in a plan view, the semiconductor layer 40 is rectangular.

[0169] In Figure 5 , the center line 90 is a line that bisects the rectangular semiconductor layer 40 in the first direction in a plan view of the semiconductor layer 40.

[0170] The boundary 90C is the boundary between the first region A1 and the second region A2. The boundary 90C bisects the semiconductor layer 40 in terms of area in a plan view of the semiconductor layer 40, but does not necessarily have to be a straight line. In a plan view of the semiconductor layer 40, there may be cases where the center line 90 coincides with the boundary 90C and cases where they do not coincide.

[0171] In addition, the number of the first gate terminals 119 and the number of the second gate terminals 129 do not necessarily have to be limited toFigure 5 One of those illustrated in

[0172] In addition, the number of one or more first source electrodes 111 and the number of one or more second source electrodes 121 do not necessarily have to be limited to Figure 5 the six illustrated in

[0173] As Figure 4 and Figure 5 shown, in the first region A1 of the low-concentration impurity layer 33, a first body region 18 containing impurities of a second conductivity type different from the first conductivity type is formed. In the first body region 18, a first source region 14, a first gate conductor 15, and a first gate insulating film 16 containing impurities of the first conductivity type are formed. The first source electrode 11 includes a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13. The first gate conductor 15 is electrically connected to the first gate terminal 119.

[0174] The portion 12 of the first source electrode 11 is a layer that is joined to the conductive material 81 during reflow in a face-down mounting, and as a non-limiting example, it may be composed of a metal material containing any one or more of nickel, titanium, tungsten, and palladium. A plating such as gold may be applied to the upper surface of the portion 12.

[0175] The portion 13 of the first source electrode 11 is a layer that connects the portion 12 to the semiconductor layer 40, and as a non-limiting example, it may be composed of a metal material containing any one or more of aluminum, copper, gold, and silver.

[0176] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 containing impurities of the second conductivity type is formed. In the second body region 28, a second source region 24, a second gate conductor 25, and a second gate insulating film 26 containing impurities of the first conductivity type are formed. The second source electrode 21 includes a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23. The second gate conductor 25 is electrically connected to the second gate terminal 129.

[0177] The portion 22 of the second source electrode 21 is a layer that is joined to the conductive material 81 during reflow in a face-down mounting, and as a non-limiting example, it may be composed of a metal material containing any one or more of nickel, titanium, tungsten, and palladium. A plating such as gold may be applied to the upper surface of the portion 22.

[0178] The portion 23 of the second source electrode 21 is a layer that connects the portion 22 to the semiconductor layer 40, and as a non-limiting example, it may be composed of a metal material containing any one or more of aluminum, copper, gold, and silver.

[0179] With the above-described structures of the first vertical MOS transistor 10 and the second vertical MOS transistor 20, the low-concentration impurity layer 33 and the semiconductor substrate 32 function as a common drain region in which the first drain region of the first vertical MOS transistor 10 and the second drain region of the second vertical MOS transistor 20 are made common.

[0180] As Figure 4 shown, the first body region 18 is covered with an oxide film 34 having an opening, and a portion 13 of the first source electrode 11 that is connected to the first source region 14 through the opening of the oxide film 34 is provided. The oxide film 34 and the portion 13 of the first source electrode 11 are covered with a protective layer 35 having an opening, and a portion 12 that is connected to the portion 13 of the first source electrode 11 through the opening of the protective layer 35 is provided.

[0181] The second body region 28 is covered with an oxide film 34 having an opening, and a portion 23 of the second source electrode 21 that is connected to the second source region 24 through the opening of the oxide film 34 is provided. The oxide film 34 and the portion 23 of the second source electrode 21 are covered with a protective layer 35 having an opening, and a portion 22 that is connected to the portion 23 of the second source electrode 21 through the opening of the protective layer 35 is provided.

[0182] Therefore, one or more first source terminals 111 and one or more second source terminals 121 respectively refer to regions where the first source electrode 11 and the second source electrode 21 are partially exposed on the upper surface of the first semiconductor element 2A, which are so-called terminal portions. Similarly, the first gate terminal 119 and the second gate terminal 129 respectively refer to regions where a first gate electrode (not shown) and a second gate electrode (not shown) are partially exposed on the upper surface of the first semiconductor element 2A, which are so-called terminal portions.

[0183] In this way, the first vertical MOS transistor 10 has a first source terminal 111 and a first gate terminal 119 for controlling the conduction state of the first vertical MOS transistor 10 on the other main surface of the first semiconductor element 2A. In addition, the second vertical MOS transistor 20 has a second source terminal 121 and a second gate terminal 129 for controlling the conduction state of the second vertical MOS transistor 20 on the other main surface of the first semiconductor element 2A. And, the first semiconductor element 2A has a drain electrode 30 common to the first vertical MOS transistor 10 and the second vertical MOS transistor 20 on one main surface of the first semiconductor element 2A.

[0184] Returning again to Figure 1 , Figure 2A , continue the description of the first semiconductor device 1A.

[0185] The first metal plate 70A has a portion with a thickness of 0.2 mm or less and is connected to one main surface of the first semiconductor element 2A in the first main surface. Here, the so-called one main surface is the main surface on which the drain electrode 30, i.e., the metal layer 30, is formed among the two main surfaces of the first semiconductor element 2A.

[0186] More specifically, the first metal plate 70A is connected to the first semiconductor element 2A with a third metal plate 75A, which will be described later, interposed therebetween between the first metal plate 70A and the first semiconductor element 2A.

[0187] Here, the first metal plate 70A and the third metal plate 75A are connected via a conductive material 71 (e.g., solder), and the third metal plate 75A and one main surface of the first semiconductor element 2A are connected via an insulating material 72 (e.g., insulating adhesive). Therefore, the third metal plate 75A and the drain electrode 30 are insulated.

[0188] As a non-limiting example, the first metal plate 70A is made of a metal material containing aluminum, copper, and silver.

[0189] In addition, the first metal plate 70A only needs to have a thickness of 0.2 mm or less in at least a part thereof. For example, only the part of the bending axis 74, which will be described later, can have a thickness of 0.2 mm or less.

[0190] On the second main surface of the first metal plate 70A, a joining preparation area 73A for joining the second metal plate 80A, i.e., the first storage piece 80A, is provided. In a plan view of the first metal plate 70A, the joining preparation area 73A does not overlap with the connection area where the first metal plate 70A and the first semiconductor element 2A are connected.

[0191] The so-called joining preparation area 73A is an area where the first metal plate 70A and the second metal plate 80A are joined later, and is a certain range provided on the first metal plate 70A at a stage before the two are joined.

[0192] Although it is also related to the joining method of the first metal plate 70A and the second metal plate 80A, for the joining preparation area 73A, some processing that makes the joining of the two easier later can be performed in advance. For example, in the first metal plate 70A, only in the joining preparation area 73A, processing with a thickness and surface roughness different from other ranges can be performed. In addition, other raw materials different from the raw materials constituting the first metal plate 70A can also be formed on the surface.

[0193] In addition, no processing may be performed on the bonding preparation area 73A either. In this case, when the first metal plate 70A is observed in plan view, the bonding preparation area 73A can be understood as the entire area on the opposite side of the area where the first metal plate 70A is connected to the first semiconductor element 2A with respect to the bending axis 74 in the first metal plate 70A.

[0194] In Embodiment 1, the first metal plate 70A is bonded to the second metal plate 80A, i.e., the first storage electrode plate 80A, in the bonding preparation area 73A.

[0195] Here, it is assumed that the first metal plate 70A and the second metal plate 80A are bonded by welding for explanation. However, the first metal plate 70A and the second metal plate 80A only need to be bonded in a conductive manner, and it is not necessarily limited to a structure bonded by welding. The first metal plate 70A and the second metal plate 80A can be bonded by solder, for example.

[0196] The first metal plate 70A is electrically connected to the second source terminal 121. More specifically, as shown in Figure 2A , the first metal plate 70A is electrically connected to the second source terminal 121 via a third metal plate 75A described later, a metal component 85A described later, and a first wiring 61 provided on the mounting substrate 60. The first wiring 61 is connected to the metal component 85A via a conductive material 81 and is connected to one of the plurality of external connection terminals of the first semiconductor element 2A, i.e., the second source terminal 121, via the conductive material 81. Therefore, the first metal plate 70A and the second source terminal 121 have the same potential.

[0197] In addition, the first metal plate 70A can be bent in a portion having a thickness of 0.2 mm or less in such a manner that portions of the second main surfaces face each other.

[0198] Bending means that the first metal plate 70A is convex, concave, or bent along the bending axis 74 (see Figure 18A etc. described later). Typically, the cross section of the bent first metal plate 70A is U-shaped or J-shaped.

[0199] In this Embodiment 1, a shape and a material of the first metal plate 70A that are not bent but can be bent are described. The reason for having a portion with a thickness of 0.2 mm or less of the first metal plate 70A is also for this reason.

[0200] Figure 6 is an example of a plan view of the first metal plate 70A observed from the second main surface side.

[0201] In addition, the bending axis 74 is an imaginary axis provided on the first metal plate 70A to be bent later, and the first metal plate 70A is bent along the bending axis 74.

[0202] Regarding the first metal plate 70A before being bent, when the first metal plate 70A is observed in a plan view, in many cases, the position of the bending axis 74 of the first metal plate 70A has specific structural features. However, there can also be cases where the first metal plate 70A does not have any structural features. In such a case, it can be understood that in the plan view of the first semiconductor element 2A, the position of the bending axis 74 inside the first metal plate 70A is an arbitrary position where the first metal plate 70A can be bent in such a way that there is a portion where the first semiconductor element 2A and the bonding preparation region 73A overlap with each other across the first metal plate 70A.

[0203] For example, it can be that the first metal plate 70A, as Figure 6 shown, can be bent at the bending axis 74 in such a way that there is a portion where the second main surfaces face each other. In the plan view of the first metal plate 70A, the bonding preparation region 73A and the connection region where the first metal plate 70A is connected to the first semiconductor element 2A are located on one side and the other side across the bending axis 74.

[0204] Thereby, the adverse effect of the heat generated when bonding the first metal plate 70A and the second metal plate 80A on the first semiconductor element 2A can be reduced.

[0205] In addition, thereby, the adverse effect of the physical shock generated when bonding the first metal plate 70A and the second metal plate 80A on the first semiconductor element 2A can be suppressed.

[0206] In addition, as Figure 6 shown, for example, it can be that the first semiconductor element 2A is connected to the first metal plate 70A with the first side 2A1 of the first semiconductor element 2A being orthogonal to the bending axis 74, and the length of the first metal plate 70A in the direction orthogonal to the bending axis 74 in the plan view of the first metal plate 70A is more than twice the length of the first side 2A1.

[0207] Thereby, in the plan view of the first metal plate 70A, the first metal plate 70A can have the bonding preparation region 73A with an area equal to or larger than that of the connection region with the first semiconductor element 2A except for the connection region with the first semiconductor element 2A.

[0208] In addition, as Figure 6As shown, for example, in the plan view of the first metal plate 70A, the first metal plate 70A is a substantially rectangular shape having a substantially linear first substantially linear side 76A and a second substantially linear side 76B extending in a direction orthogonal to the bending axis 74. The first substantially linear side 76A and the second substantially linear side 76B each have a recessed concave portion 77A and a concave portion 77B on the inner side of the first metal plate 70A in the plan view of the first metal plate 70A. Here, the concave portion 77A and the concave portion 77B may be located at the intersection of the bending axis 74 and the first substantially linear side 76A and the second substantially linear side 76B.

[0209] Thereby, the first metal plate 70A can be easily bent at the bending axis 74.

[0210] In addition, when the first metal plate 70A is locally thinned, the concave portion 77A and the concave portion 77B are preferably disposed at positions corresponding to the locally thinned portions.

[0211] Figure 7 It is another example of the plan view of the first metal plate 70A observed from the second main surface side.

[0212] As Figure 7 shown, for example, the first metal plate 70A can be bent at a plurality of bending axes 74 (here, corresponding to the bending axis 74A, the bending axis 74B, and the bending axis 74C) in such a manner that portions of the second main surfaces face each other.

[0213] Returning again to Figure 1 , Figure 2A , and continuing to describe the first semiconductor device 1A.

[0214] As Figure 2A shown, between the first semiconductor element 2A and the first metal plate 70A, the third metal plate 75A is connected to the first semiconductor element 2A on one main surface of the first semiconductor element 2A, and is connected to the first metal plate 70A on the first main surface of the first metal plate 70A.

[0215] As a non-limiting example, the third metal plate 75A is made of a metal material containing copper, nickel, or stainless steel.

[0216] The first semiconductor device 1A includes the third metal plate 75A, thereby enabling improvement of the pressure resistance of the first semiconductor element 2A, and this pressure resistance is the pressure resistance against the pressure applied to one main surface of the first semiconductor element 2A from the second main surface side of the first metal plate 70A.

[0217] In addition, the thickness and width of the third metal plate 75A are adjusted to appropriate thickness and width corresponding to the magnitude of the current supplied to the first semiconductor element 2A, so as to improve heat dissipation and suppress the high temperature of the first semiconductor element 2A. For example, in order to improve the heat dissipation of the heat generated when the first semiconductor element 2A is energized, the width of the third metal plate 75A may be greater than the width of the first semiconductor element 2A.

[0218] One or more metal components 85A are connected to the main surface of the third metal plate 75A where the third metal plate 75A is connected to the first semiconductor element 2A, as Figure 2A shown. Here, regarding the position where the main surface of the third metal plate 75A is connected to one or more metal components 85A, in the plan view of the first metal plate 70A, the regions where the main surface of the third metal plate 75A is connected to one or more metal components 85A are each located at a position that does not overlap with the bonding preparation region 73A.

[0219] One or more metal components 85A are mounted on the mounting substrate 60 together with the first semiconductor element 2A when the first semiconductor element 2A is mounted on the mounting substrate 60. That is, the height of one or more metal components 85A from the main surface of the third metal plate 75A is equal to the distance from the main surface of the third metal plate 75A to the other main surface of the first semiconductor element 2A.

[0220] The first semiconductor device 1A includes one or more metal components 85A, so that the pressure resistance of the first semiconductor element 2A can be further improved, and this pressure resistance is the pressure resistance against the pressure applied to one main surface of the first semiconductor element 2A from the second main surface side of the first metal plate 70A.

[0221] As described above, at least one of the one or more metal components 85A is connected to the first wiring 61 provided on the mounting substrate 60 via the conductive material 81, and the first wiring 61 is connected to one of the plurality of external connection terminals of the first semiconductor element 2A, namely the second source terminal 121, via the conductive material 81. As a result, the first metal plate 70A and the second source terminal 121 have the same potential, and in addition, the first storage piece 80A and the first wiring 61 have the same potential.

[0222] In addition, it may be that one or more metal components 85A are made of the same material as the third metal plate 75A and are integrated with the third metal plate 75A, as Figure 2A shown. Thus, a structure composed of the third metal plate 75A and one or more metal components 85A can be realized relatively simply.

[0223] Alternatively, one or more metal components 85A may not be integrated with the third metal plate 75A, but may be independent of the third metal plate 75A. In this case, as a non-limiting example, the one or more metal components 85A are made of a metal material containing copper, nickel, or stainless steel.

[0224] Figure 8 FIG. is a plan view of the first semiconductor device 1A as viewed from the second main surface side of the first metal plate 70A, which is an example showing the case where the first semiconductor device 1A includes one or more metal components 85A. Figure 8 In, for a part of the portion that cannot be directly recognized in practice, it is shown by a dotted line as if it can be recognized.

[0225] For example, it may be, as Figure 8 shown, the first semiconductor element 2A has two sides in a direction parallel to the length direction of the protection circuit board 60, and the one or more metal components 85A include two metal components 85A arranged so as to face each other over the entire length of these two sides.

[0226] Accordingly, a part of the stress acting on the first semiconductor element 2A is dispersed to these two metal components 85A. Therefore, it is difficult for the first semiconductor element 2A to peel off from the protection circuit board 60.

[0227] In addition, accordingly, since the one or more metal components 85A are arranged parallel to the length direction of the protection circuit board 60, the width of the limited protection circuit board 60 can be used as wiring to the maximum extent, and it is easy to ensure the pattern width of the large current path in the protection circuit board 60.

[0228] Figure 9 FIG. is a plan view of the first semiconductor device 1A as viewed from the second main surface side of the first metal plate 70A, which is another example showing the case where the first semiconductor device 1A includes one or more metal components 85A. Figure 9 In, for a part of the portion that cannot be directly recognized in practice, it is shown by a dotted line as if it can be recognized as shown in the figure.

[0229] For example, it may be, as Figure 9 shown, the first semiconductor element 2A has two sides in a direction orthogonal to the long side direction of the protection circuit board 60, and the one or more metal components 85A include two metal components 85A arranged so as to face each other over the entire length of these two sides.

[0230] Accordingly, a part of the stress acting on the first semiconductor element 2A is dispersed to these two metal components 85A. Therefore, it is difficult for the first semiconductor element 2A to peel off from the protection circuit board 60.

[0231] In addition, as a result, it is possible to further reduce the width in the direction orthogonal to the length direction of the protection circuit board 60. Therefore, it is possible to further reduce the width in the direction orthogonal to the above length direction of the power storage pack 100. At this time, when the size of the power storage pack 100 is fixed, it is possible to make the size of the power storage unit 3 larger and make the power storage capacity of the power storage unit 3 larger.

[0232] Figure 10 It is a plan view of the first semiconductor device 1A viewed from the second main surface side of the first metal plate 70A, which is another example showing the case where the first semiconductor device 1A includes one or more metal components 85A. In Figure 10 For a part of the part that cannot be directly recognized in reality, it is shown by a dotted line as if it can be recognized.

[0233] For example, it can be, as Figure 10 shown, one or more metal components 85A include four metal components 85A arranged near each of the four corners of the first semiconductor element 2A. Here, the vicinity of the corner of the first semiconductor element 2A, as Figure 11 shown, refers to the range inside the extended area of ±40% of each side length of the first semiconductor element 2A in the area around each corner of the first semiconductor element 2A.

[0234] As a result, a part of the stress acting on the first semiconductor element 2A is dispersed to these four metal components 85A. Therefore, it is difficult for the first semiconductor element 2A to peel off from the protection circuit board 60.

[0235] In addition, regarding the arrangement of the metal component 85A, it should be noted that it is only necessary to prevent the path of the wiring provided in the protection circuit board 60 to which the substrate connection terminal of the first semiconductor element 2A is connected from being unnecessarily extended and its direction from being unnecessarily changed. Therefore, preferably, no metal component 85A is provided between the substrate connection terminal of the first semiconductor element 2A and the terminal of the power storage pack 100 to which the wiring provided in the protection circuit board 60 connected to the substrate connection terminal is connected.

[0236] In addition, as a result, it is possible to easily balance the ease of ensuring the pattern width of the large-current path in the protection circuit board 60, the reduction of the width of the power storage pack 100, or the increase in the power storage capacity of the power storage unit 3.

[0237] In addition, the first semiconductor device 1A does not necessarily have to be limited to a structure including one or more metal components 85A. However, in this case, an alternative means for making the first metal plate 70A and the second source terminal 121 have the same potential is required. As an alternative means, for example, a means such as connecting the first metal plate 70A and the first wiring 61 with a lead can be considered.

[0238] Returning again to Figure 1 、 Figure 2A 、 Figure 2B , continue with the description of the power storage pack 100.

[0239] The second semiconductor device 1B includes a second semiconductor element 2B, a second power storage sheet bonding metal plate 70B, a third metal plate 75B, and one or more metal components 85B. In addition, in this specification, the second power storage sheet bonding metal plate 70B is also referred to as the first metal plate 70B.

[0240] The second semiconductor device 1B is the same as the first semiconductor device 1A. That is, the second semiconductor device 1B is the same as the case where the first semiconductor element 2A is renamed the second semiconductor element 2B, the first power storage sheet bonding metal plate 70A is renamed the second power storage sheet bonding metal plate 70B, the third metal plate 75A is renamed the third metal plate 75B, and the metal component 85A is renamed the metal component 85B for the first semiconductor device 1A.

[0241] As described above, the second semiconductor element 2B is the same as the first semiconductor element 2A. More specifically, the second semiconductor element 2B is the same as the case where the first gate terminal 119 is renamed the first gate terminal 219, the first source terminal 111 is renamed the first source terminal 211, the second gate terminal 129 is renamed the second gate terminal 229, the second source terminal 121 is renamed the second source terminal 221, and the drain electrode 30 is renamed the drain electrode 31 for the first semiconductor element 2A.

[0242] As described above, the first metal plate 70B is the same as the first metal plate 70A. More specifically, the first metal plate 70B is the same as the case where the bonding preparation region 73A is renamed the bonding preparation region 73B for the first metal plate 70A.

[0243] Regarding the one or more metal components 85B, similar to the one or more metal components 85A, at least one of the one or more metal components 85B is connected to the third wiring 63 provided in the mounting substrate 60 via the conductive material 81, and the third wiring 63 is connected to one of the plurality of external connection terminals of the second semiconductor element 2B, that is, the second source terminal 221, via the conductive material 81. Thus, the first metal plate 70B has the same potential as the second source terminal 221, and in addition, the second power storage sheet 80B has the same potential as the third wiring 63.

[0244] The protection circuit board 60 includes a first wiring 61, a second wiring 62, a third wiring 63, a fourth wiring 64, a power storage pack positive terminal 66, and a power storage pack negative terminal 67.

[0245] In the protection circuit board 60, the first semiconductor element 2A and the second semiconductor element 2B are mounted via the conductive material 81.

[0246] The first wiring 61 is connected to at least one of the one or more metal components 85A via the conductive material 81, and is connected to the second source terminal 121 via the conductive material 81.

[0247] The second wiring 62 is connected to the first source terminal 111 via the conductive material 81, and is connected to the positive electrode terminal 66 of the power storage battery pack.

[0248] The third wiring 63 is connected to at least one of the one or more metal components 85B via the conductive material 81, and is connected to the second source terminal 221 via the conductive material 81.

[0249] The fourth wiring 64 is connected to the first source terminal 211 via the conductive material 81, and is connected to the negative electrode terminal 67 of the power storage battery pack.

[0250] The positive electrode terminal 66 of the power storage battery pack is a terminal for allowing current to flow out to an external device of the power storage battery pack 100 or for allowing current to flow in from an external terminal of the power storage battery pack 100. The positive electrode terminal 66 of the power storage battery pack functions as the positive electrode terminal of the power storage battery pack 100.

[0251] The negative electrode terminal 67 of the power storage battery pack is a terminal for allowing current to flow out to an external device of the power storage battery pack 100 or for allowing current to flow in from an external terminal of the power storage battery pack 100. The negative electrode terminal 67 of the power storage battery pack functions as the negative electrode terminal of the power storage battery pack 100.

[0252] <Examination>

[0253] Figure 12 It is the circuit diagram of the power storage battery pack 100 having the above structure.

[0254] As Figure 12 shown, the first semiconductor element 2A functions as a switching element for the current path flowing from the positive electrode terminal 36 of the power storage unit 3 to the positive electrode terminal 66 of the power storage battery pack and the current path flowing from the positive electrode terminal 66 of the power storage battery pack to the positive electrode terminal 36 of the power storage unit 3.

[0255] That is, the first semiconductor element 2A as a switching element: (1) When it becomes conductive from the second source terminal 121 to the first source terminal 111, the potential on the second source terminal 121 side is higher than the potential on the first source terminal 111 side, thereby forming a current path in which current flows from the power storage unit 3 in the order of the first power storage sheet 80A, the first power storage sheet bonding metal plate 70A, and the first semiconductor element 2A. (2) When it becomes conductive from the first source terminal 111 to the second source terminal 121, the potential on the first source terminal 111 side is higher than the potential on the second source terminal 121 side, thereby forming a current path in which current flows from the first semiconductor element 2A in the order of the first power storage sheet bonding metal plate 70A, the first power storage sheet 80A, and the power storage unit 3.

[0256] In addition, the second semiconductor element 2B functions as a switching element for the current path from the negative terminal 37 of the power storage unit 3 to the battery pack negative terminal 67 and the current path from the battery pack negative terminal 67 to the negative terminal 37 of the power storage unit 3.

[0257] That is, the second semiconductor element 2B as a switching element: (1) When it becomes conductive from the second source terminal 221 to the first source terminal 211, the potential on the second source terminal 221 side is higher than the potential on the first source terminal 211 side, thereby forming a current path in which current flows from the power storage unit 3 in the order of the second power storage sheet 80B, the second power storage sheet bonding metal plate 70B, and the second semiconductor element 2B. (2) When it becomes conductive from the first source terminal 211 to the second source terminal 221, the potential on the first source terminal 211 side is higher than the potential on the second source terminal 221 side, thereby forming a current path in which current flows from the second semiconductor element 2B in the order of the second power storage sheet bonding metal plate 70B, the second power storage sheet 80B, and the power storage unit 3.

[0258] Therefore, the first semiconductor element 2A as a switching element and the second semiconductor element 2B as a switching element can control the charging of the power storage unit 3 or the discharging from the power storage unit 3 in the protection circuit board 60.

[0259] As Figure 12 shown, the battery pack 100 has, on the high potential side of the power storage unit 3, the first semiconductor element 2A as a switching element that controls the current path from the positive terminal 36 to the battery pack positive terminal 66 and the current path from the battery pack positive terminal 66 to the positive terminal 36, and on the low potential side of the power storage unit 3, the second semiconductor element 2B as a switching element that controls the current path from the negative terminal 37 to the battery pack negative terminal 67 and the current path from the battery pack negative terminal 67 to the negative terminal 37.

[0260] Thus, the power storage pack 100 can achieve double protection of the power storage unit 3 on the high potential side and the low potential side of the power storage unit 3.

[0261] In the power storage pack 100 having the above structure, as described above, the first power storage sheet 80A and the second power storage sheet 80B are respectively joined to the first power storage sheet joining metal plate 70A and the second power storage sheet joining metal plate 70B.

[0262] Thus, in the power storage pack 100 having the above structure, there is no need for the areas in the protection circuit board 60 for connecting the first power storage sheet 80A and the areas for connecting the second power storage sheet 80B, which are required in the conventional power storage pack in which the first power storage sheet 80A and the second power storage sheet 80B are directly connected to the protection circuit board 60.

[0263] Therefore, according to the power storage pack 100 having the above structure, miniaturization of the protection circuit board 60 can be achieved.

[0264] In addition, in the power storage pack 100 having the above structure, the first power storage sheet joining metal plate 70A and the first power storage sheet 80A are connected to the first semiconductor element 2A, and the second power storage sheet joining metal plate 70B and the second power storage sheet 80B are connected to the second semiconductor element 2B, so that the heat dissipation of the first semiconductor element 2A and the second semiconductor element 2B can be improved, and the high temperature of the first semiconductor element 2A and the second semiconductor element 2B can be suppressed.

[0265] In addition, in the power storage pack 100, it is possible to further reinforce the strength of the first semiconductor element 2A, the third metal plate 75A, and the first metal plate 70A by molding reinforcement, and to further reinforce the strength of the second semiconductor element 2B, the third metal plate 75B, and the first metal plate 70B by molding reinforcement.

[0266] In addition, in the power storage pack 100, the protection circuit board 60 is a protection circuit board having embedded wiring, and the first semiconductor element 2A and the second semiconductor element 2B can be formed by embedding the protection circuit board having embedded wiring.

[0267] Figure 13 It is a cross-sectional view of the protection circuit board 60A and the first semiconductor element 2A in the case where the first semiconductor element 2A and the second semiconductor element 2B (the second semiconductor element 2B is not shown in

[0268] As Figure 13 shown, the substrate connection terminals of the first semiconductor element 2A and the second semiconductor element 2B (the second semiconductor element 2B is not shown in Figure 13 the figure) can be mounted on the wiring embedded in the protection circuit board 60A.

[0269] In this case, the conductive material 81 can be realized by, for example, silver paste or the crimping (ultrasonic, thermal) of copper or gold, and the conductive material 71 can be realized by, for example, solder.

[0270] In addition, in the power storage battery pack 100, the protection circuit board 60 can be a protection circuit board corresponding to resin embedding, and the first semiconductor element 2A and the second semiconductor element 2B can be embedded in the protection circuit board corresponding to resin embedding to form a structure.

[0271] Figure 14 FIG. is a cross-sectional view of the protection circuit board 60B and the first semiconductor element 2A in the case where the first semiconductor element 2A and the second semiconductor element 2B are embedded in the protection circuit board 60B corresponding to resin embedding.

[0272] As Figure 14 shown, the substrate connection terminals of the first semiconductor element 2A and the second semiconductor element 2B (the second semiconductor element 2B is not shown in Figure 14 ) can be mounted on the wiring embedded in the resin 60C.

[0273] In this case, the conductive material 81 can be realized by, for example, silver paste or the crimping (ultrasonic, thermal) of copper or gold, and the conductive material 71 can be realized by, for example, solder.

[0274] In addition, in the power storage battery pack 100, regarding the length of the first metal plate 70A in the direction extending from the bonding preparation region 73A to the region connected to the first semiconductor element 2A, in the plan view of the first semiconductor element 2A, it can be, as Figure 2A shown, a length that extends beyond the first semiconductor element 2A, or it can be a length that stops at a position not exceeding the first semiconductor element 2A.

[0275] (Embodiment 2) <0,

[0276] Hereinafter, a power storage battery pack of Embodiment 2 formed by changing a part of the structure from the power storage battery pack 100 of Embodiment 1 will be described.

[0277] The power storage battery pack 100 is an example of the following structure: the first semiconductor device 1A includes a third metal plate 75A sandwiched between the first metal plate 70A and the first semiconductor element 2A, the first metal plate 70A is connected to the first semiconductor element 2A with the third metal plate 75A interposed therebetween, the second semiconductor device 1B includes a third metal plate 75B sandwiched between the first metal plate 70B and the second semiconductor element 2B, and the first metal plate 70B is connected to the second semiconductor element 2B with the third metal plate 75B interposed therebetween.

[0278] In contrast, the power storage pack of Embodiment 2 is an example of the following structure: the first semiconductor device of Embodiment 2 does not include the third metal plate 75A, and the first metal plate 70A is not connected to the first semiconductor element 2A with the third metal plate 75A interposed therebetween; the second semiconductor device of Embodiment 2 does not include the third metal plate 75B, and the first metal plate 70B is not connected to the second semiconductor element 2B with the third metal plate 75B interposed therebetween.

[0279] Here, with respect to the power storage pack of Embodiment 2, the same components as those of the power storage pack 100 are considered to have been described and are given the same reference numerals, and their detailed descriptions are omitted, and the description will be centered on the differences from the power storage pack 100.

[0280] <Structure>

[0281] Figure 15 is a plan view showing the structure of the power storage pack 100A of Embodiment 2. Figure 16A is showing Figure 15 a cross-sectional view of the cut surface taken along line I-I of Figure 16B is showing Figure 15 a cross-sectional view of the cut surface taken along line II-II of Figure 15 In

[0282] As Figure 15 , Figure 16A , Figure 16B shown, the power storage pack 100A is formed by changing the first semiconductor device 1A to the first semiconductor device 1AA and the second semiconductor device 1B to the second semiconductor device 1BA in the power storage pack 100 of Embodiment 1.

[0283] The first semiconductor device 1AA is formed by deleting the third metal plate 75A from the first semiconductor device 1A and changing the metal member 85A to the metal member 85AA.

[0284] In the first semiconductor device 1AA, the first metal plate 70A is connected to one main surface of the first semiconductor element 2A via an insulating material 72 in the first main surface. Therefore, the first metal plate 70A is insulated from the drain electrode 30.

[0285] In the first semiconductor device 1AA, one or more metal members 85AA are, as Figure 16A shown, connected to the first main surface of the first metal plate 70A where the first metal plate 70A is connected to the first semiconductor element 2A. Here, the positions where the first main surface is connected to one or more metal members 85AA are positions where the respective regions where the first main surface is connected to one or more metal members 85AA do not overlap with the bonding preparation region 73A in the plan view of the first metal plate 70A.

[0286] When mounting the first semiconductor element 2A on the mounting substrate 60, one or more metal components 85AA are mounted on the mounting substrate 60 together with the first semiconductor element 2A. That is, the height of one or more metal components 85AA from the first main surface of the first metal plate 70A is equal to the distance from the first main surface of the first metal plate 70A to the other main surface of the first semiconductor element 2A.

[0287] The first semiconductor device 1AA includes one or more metal components 85AA, thereby enabling the pressure resistance of the first semiconductor element 2A to be improved, and this pressure resistance is the pressure resistance against the pressure applied to one main surface of the first semiconductor element 2A from the second main surface side of the first metal plate 70A.

[0288] In the first semiconductor device 1AA, at least one of the one or more metal components 85AA is connected to the first wiring 61 provided on the mounting substrate 60 via the conductive material 81. As a result, the first metal plate 70A and the second source terminal 121 have the same potential, and in addition, the first storage sheet 80A and the first wiring 61 have the same potential.

[0289] Alternatively, one or more metal components 85AA may be made of the same material as the first metal plate 70A and integrated with the first metal plate 70A as Figure 16A shown. Thus, a structure composed of the first metal plate 70A and one or more metal components 85AA can be realized relatively simply.

[0290] Or, one or more metal components 85AA may not be integrated with the first metal plate 70A and be independent of the first metal plate 70A. In this case, as a non-limiting example, one or more metal components 85AA are made of copper, nickel, or a metal material including stainless steel.

[0291] Alternatively, in the first semiconductor device 1AA, similar to the case of the first semiconductor device 1A exemplified in Figure 8 , the first semiconductor element 2A has two sides in a direction parallel to the length direction of the protection circuit substrate 60, and one or more metal components 85AA include two metal components 85AA arranged opposite to each other along the entire length of these two sides.

[0292] As a result, a part of the stress acting on the first semiconductor element 2A is dispersed to these two metal components 85AA. Therefore, the first semiconductor element 2A is less likely to peel off from the protection circuit substrate 60.

[0293] In addition, since one or more metal components 85AA are arranged parallel to the length direction of the protection circuit board 60, the width of the limited protection circuit board 60 can be used as wiring to the maximum extent, and it is easy to ensure the pattern width of the large current path in the protection circuit board 60.

[0294] In addition, in the first semiconductor device 1AA, Figure 9 Similar to the case of the first semiconductor device 1A illustrated in, the first semiconductor element 2A has two sides in a direction orthogonal to the length direction of the protection circuit board 60, and one or more metal components 85AA include two metal components 85AA arranged opposite to each other along the entire length of these two sides.

[0295] As a result, a part of the stress acting on the first semiconductor element 2A is dispersed to these two metal components 85AA. Therefore, it is difficult for the first semiconductor element 2A to peel off from the protection circuit board 60.

[0296] In addition, as a result, the width of the protection circuit board 60 in the direction orthogonal to the length direction can be further reduced. Therefore, the width of the power storage pack 100A in the direction orthogonal to the above length direction can be further reduced. At this time, when the size of the power storage pack 100A is fixed, the size of the power storage unit 3 can be made larger, and the power storage capacity of the power storage unit 3 can be made larger.

[0297] In addition, in the first semiconductor device 1AA, Figure 10 Similar to the case of the first semiconductor device 1A illustrated in, one or more metal components 85AA include four metal components 85AA arranged near each of the four corners of the first semiconductor element 2A.

[0298] As a result, a part of the stress acting on the first semiconductor element 2A is dispersed to these four metal components 85AA. Therefore, it is difficult for the first semiconductor element 2A to peel off from the protection circuit board 60.

[0299] In addition, as a result, it is easy to balance the ease of ensuring the pattern width of the large current path in the protection circuit board 60, the reduction of the width of the power storage pack 100, or the increase in the power storage capacity of the power storage unit 3.

[0300] In addition, the first semiconductor device 1AA does not necessarily have to be limited to a structure having one or more metal components 85AA. However, in this case, alternative means are required to make the first metal plate 70A and the second source terminal 121 have the same potential. As an alternative means, for example, means such as connecting the first metal plate 70A and the first wiring 61 with a lead can be considered.

[0301] The second semiconductor device 1BA is formed by removing the third metal plate 75B from the second semiconductor device 1B and changing the metal component 85B to a metal component 85BA.

[0302] The second semiconductor device 1BA is the same as the first semiconductor device 1AA. That is, the second semiconductor device 1BA has the same structure as that obtained by renaming the first semiconductor element 2A as the second semiconductor element 2B, the first storage sheet bonding metal plate 70A as the second storage sheet bonding metal plate 70B, and the metal component 85AA as the metal component 85BA with respect to the first semiconductor device 1AA.

[0303] One or more metal components 85BA in the second semiconductor device 1BA are the same as one or more metal components 85AA in the first semiconductor device 1AA. At least one of the one or more metal components 85BA is connected to the third wiring 63 provided on the mounting substrate 60 via the conductive material 81. As a result, the first metal plate 70B has the same potential as the second source terminal 221, and the second storage sheet 80B has the same potential as the third wiring 63.

[0304] <Examination>

[0305] The circuit diagram of the power storage pack 100A with the above structure is the same as the Figure 12 circuit diagram shown as the circuit diagram of the power storage pack 100 of Embodiment 1.

[0306] Therefore, in the power storage pack 100A, the first semiconductor element 2A functions as the same switching element as the first semiconductor element 2A in the power storage pack 100. In addition, in the power storage pack 100A, the second semiconductor element 2B functions as the same switching element as the second semiconductor element 2B in the power storage pack 100.

[0307] (Embodiment 3)

[0308] Hereinafter, a power storage pack of Embodiment 3 formed by changing a part of the structure from the power storage pack 100 of Embodiment 1 will be described.

[0309] The power storage pack of Embodiment 3 is an example of the following structure: with respect to the power storage pack 100, the first storage sheet bonding metal plate 70A and the second storage sheet bonding metal plate 70B are changed from the first storage sheet bonding metal plate 70A and the second storage sheet bonding metal plate 70B to the first storage sheet bonding metal plate of Embodiment 3 and the second storage sheet bonding metal plate of Embodiment 3 bent along the bending axis 74.

[0310] Here, regarding the battery pack of Embodiment 3, for the same components as those of the battery pack 100, it is considered that they have been described and the same reference numerals are attached, and the detailed description thereof is omitted, and the description will be centered on the differences from the battery pack 100.

[0311] <Structure>

[0312] Figure 17 is a plan view showing the structure of the battery pack 100B of Embodiment 3. Figure 18A is showing Figure 17 a sectional view taken along line I - I of Figure 18B is showing Figure 17 a sectional view taken along line II - II of Figure 17 In, for a part of the part that cannot be directly recognized actually, it is shown by a dashed line as can be recognized in the figure.

[0313] As Figure 17 , Figure 18A , [[ID= shown, the battery pack 100B is constituted by changing the first semiconductor device 1A to the first semiconductor device 1AB, the second semiconductor device 1B to the second semiconductor device 1BB, the first storage sheet 80A to the first storage sheet 80AB, and the second storage sheet 80B to the second storage sheet 80BB from the battery pack 100 of Embodiment 1. In addition, in this specification, the first storage sheet 80AB is also referred to as the second metal plate 80AB, and the second storage sheet 80BB is also referred to as the second metal plate 80BB.

[0314] The first semiconductor device 1AB is constituted by changing the first metal plate 70A to the first metal plate 70AB from the first semiconductor device 1A. In addition, in this specification, the first metal plate 70AB is also referred to as the first storage sheet bonding metal plate 70AB.

[0315] The first metal plate 70AB is the same as the case where the first metal plate 70A is bent at the bending axis 74 so that the portions with the second main surfaces facing each other are formed. Here, in the plan view of the first semiconductor element 2A, the position of the bending axis 74 becomes the position where there is a portion where the first semiconductor element 2A and the bonding preparation region 73A overlap with each other across the first metal plate 70A. Therefore, in the first semiconductor device 1AB, in the plan view of the first semiconductor element 2A, there is a portion where the first semiconductor element 2A and the bonding preparation region 73A overlap with each other across the first metal plate 70AB. In addition, in the first semiconductor device 1AB, in the plan view of the first semiconductor element 2A, there is a portion where the first semiconductor element 2A and the first storage sheet 80AB overlap with each other across the first storage sheet bonding metal plate 70AB. Thus, in the plan view of the protection circuit board 60, the first semiconductor device 1AB has a portion where the first storage sheet 80AB, the first metal plate 70AB, the first semiconductor element 2A, and the protection circuit board 60 overlap with each other.

[0316] Accordingly, in the power storage pack 100B, in the plan view of the protection circuit board 60, there is a portion where the region where current can flow between the first storage sheet 80AB and the protection circuit board 60 overlaps with the region where the first storage sheet 80AB, the first metal plate 70AB, the first semiconductor element 2A, and the protection circuit board 60 overlap with each other.

[0317] Here, the region where current can flow between the first storage sheet 80AB and the protection circuit board 60 refers to the entire region where current can flow between the first storage sheet 80AB and the protection circuit board 60, that is, the entire region of the conductor continuously existing between the first storage sheet 80AB and the protection circuit board 60. In addition, this conductor also includes the first storage sheet 80AB itself. For example, in ​ the case, it corresponds to the whole of the first storage sheet 80AB, the whole of the first metal plate 70AB, the whole of the conductive material 71, the whole of the third metal plate 75A, the whole of the metal component 85A, the whole of the conductive material 81, the first wiring 61, the whole of the first semiconductor element, and the second wiring 62.

[0318] In addition, here, as ​ , ​The description has been made on the assumption that the orientation of the bending axis 74 is orthogonal to the first side 2A1 of the first semiconductor element 2A as shown. However, regarding the orientation of the bending axis 74, as long as (1) the first metal plate 70A is bent at the bending axis 74 so as to have portions where the second main surfaces face each other, and (2) in the plan view of the first semiconductor element 2A, there can be a portion where the first semiconductor element 2A and the bonding preparation region 73A overlap with each other across the first metal plate 70A, the orientation of the bending axis 74 does not need to be limited to being orthogonal to the first side 2A1 of the first semiconductor element 2A.

[0319] The second semiconductor device 1BB is formed by changing the first metal plate 70B of the second semiconductor device 1B to the first metal plate 70BB. In addition, in this specification, the first metal plate 70BB is also referred to as the second power storage sheet bonding metal plate 70BB.

[0320] The second semiconductor device 1BB is the same as the first semiconductor device 1AB. That is, the second semiconductor device 1BB is the same as the case where the first semiconductor element 2A in the first semiconductor device 1AB is renamed as the second semiconductor element 2B and the first power storage sheet bonding metal plate 70AB is renamed as the second power storage sheet bonding metal plate 70BB.

[0321] The first power storage sheet 80AB is the same as the case where the first power storage sheet 80A of the first embodiment is bent so as to have portions where the surfaces for bonding to the first metal plate 70A face each other at the bonding preparation region 73A.

[0322] The second power storage sheet 80BB is the same as the case where the second power storage sheet 80B of the first embodiment is bent so as to have portions where the surfaces for bonding to the first metal plate 70B face each other at the bonding preparation region 73B.

[0323] <Examination>

[0324] The circuit diagram of the power storage pack 100B having the above structure is the same as the ​ circuit diagram illustrated as the circuit diagram of the power storage pack 100 of the first embodiment.

[0325] Therefore, in the power storage pack 100B, the first semiconductor element 2A functions as the same switching element as the first semiconductor element 2A in the power storage pack 100. In addition, in the power storage pack 100B, the second semiconductor element 2B functions as the same switching element as the second semiconductor element 2B in the power storage pack 100.

[0326] Furthermore, compared with the power storage pack 100, in the plan view of the protection circuit board 60 of the power storage pack 100B with the above structure, not only do the first power storage sheet 80AB and the first power storage sheet bonding metal plate 70AB overlap, but there is a region where the first power storage sheet 80AB, the first power storage sheet bonding metal plate 70AB, the first semiconductor element 2A, and the protection circuit board 60 overlap, and there is also a region where the second power storage sheet 80BB, the second power storage sheet bonding metal plate 70BB, the second semiconductor element 2B, and the protection circuit board 60 overlap. Correspondingly, the size of the power storage pack 100B can be made smaller. At this time, when the size of the power storage pack 100B is fixed, the size of the power storage unit 3 can be made larger, and the power storage capacity of the power storage unit 3 can be made larger.

[0327] In addition, by bonding the first power storage sheet 80AB and the first power storage sheet bonding metal plate 70AB in a non-bent state, it is possible to reduce the adverse effects of the heat generated during bonding on the first semiconductor element 2A and the adverse effects of the physical impact generated when bonding the first power storage sheet 80AB and the first power storage sheet bonding metal plate 70AB on the semiconductor element 2A. And since the first power storage sheet 80AB and the first power storage sheet bonding metal plate 70AB can be bent later, it is possible to achieve miniaturization of the protection circuit board 60 and an increase in the power storage capacity of the power storage unit 3.

[0328] Moreover, in the power storage pack 100B, when the area of the portion where the first power storage sheet 80AB and the first power storage sheet bonding metal plate 70AB are joined in the plan view of the protection circuit board 60, that is, area A, is larger than the area of the first semiconductor element 2A in the plan view of the protection circuit board 60, that is, area B, the characteristics of the first semiconductor element 2A can be improved by using the area C (area A - area B), which is the difference between area A and area B. For example, the area of the first semiconductor element 2A in the plan view of the protection circuit board 60 can be enlarged to the same extent as area A, and the on-resistance of the first semiconductor element 2A as a switching element can be reduced.

[0329] In addition, regarding a conventional type of power storage module in which the first power storage sheet 80AB is directly connected to the protection circuit board 60, when the area D in the plan view of the protection circuit board 60 at the portion where the first power storage sheet 80AB is connected to the protection circuit board 60 is larger than the area A in the power storage module 100B, there is a case where the width of the first power storage sheet 80AB in the power storage module 100B can be made smaller than the width of the first power storage sheet 80AB in the conventional type of power storage module. In this case, due to the dual effects of not requiring the area on the protection circuit board 60 for connecting the first power storage sheet 80AB to the protection circuit board 60 in the conventional type of power storage module and the effect of being able to make the width of the first power storage sheet 80AB smaller, the power storage module 100 can be miniaturized. At this time, when the size of the power storage module 100B is fixed, due to the above dual effects, the size of the power storage unit 3 can be made larger, and the power storage capacity of the power storage unit 3 can be made larger.

[0330] (Embodiment 4)

[0331] Hereinafter, a power storage module of Embodiment 4, which is formed by changing a part of the structure of the power storage module 100A of Embodiment 2, will be described.

[0332] The power storage module of Embodiment 4 is an example of a structure obtained by changing the first power storage sheet bonding metal plate 70A and the second power storage sheet bonding metal plate 70B of the power storage module of Embodiment 4 from the first power storage sheet bonding metal plate 70A and the second power storage sheet bonding metal plate 70B to the first power storage sheet bonding metal plate of Embodiment 4 and the second power storage sheet bonding metal plate of Embodiment 4 that are bent at the bending axis 74.

[0333] Here, for the power storage module of Embodiment 4, regarding the same constituent elements as those of the power storage module 100A, it is considered that they have been described, and the same reference numerals are attached and their detailed descriptions are omitted, and the description will be centered on the differences from the power storage module 100A.

[0334] <Structure>

[0335] ​ is a plan view showing the structure of the power storage module 100C of Embodiment 4. ​ is showing ​ a cross-sectional view taken along the line I-I. ​ is showing ​ a cross-sectional view taken along the line II-II. In ​ for a part of the portion that cannot be directly recognized in practice, it is shown by a dashed line as if it can be recognized.

[0336] As ​ , ​ , ​As shown, the power storage pack 100C is formed by changing the first semiconductor device 1AA to the first semiconductor device 1AC, the second semiconductor device 1BA to the second semiconductor device 1BC, the first power storage sheet 80A to the first power storage sheet 80AC, and the second power storage sheet 80B to the second power storage sheet 80BC in the power storage pack 100A of Embodiment 2. In addition, in this specification, the first power storage sheet 80AC is also referred to as the second metal plate 80AC, and the second power storage sheet 80BC is also referred to as the second metal plate 80BC.

[0337] The first semiconductor device 1AC is formed by changing the first metal plate 70A to the first metal plate 70AC in the first semiconductor device 1AA. In addition, in this specification, the first metal plate 70AC is also referred to as the first power storage sheet bonding metal plate 70AC.

[0338] The first metal plate 70AC is the same as the case where the first metal plate 70A is bent at the bending axis 74 so that the second main surfaces face each other. Here, the position of the bending axis 74 is the position where there is a portion where the first semiconductor element 2A and the bonding preparation region 73A overlap with each other across the first metal plate 70A in the plan view of the first semiconductor element 2A. Therefore, in the first semiconductor device 1AC, in the plan view of the first semiconductor element 2A, there is a portion where the first semiconductor element 2A and the bonding preparation region 73A overlap with each other across the first metal plate 70AC. In addition, in the first semiconductor device 1AC, in the plan view of the first semiconductor element 2A, there is a portion where the first semiconductor element 2A and the first power storage sheet 80AC overlap with each other across the first power storage sheet bonding metal plate 70AB.

[0339] Thus, in the power storage pack 100C, in the plan view of the protection circuit board 60, there is a portion that overlaps with the region where current can flow between the first power storage sheet 80AC and the protection circuit board 60 and the region where the first semiconductor element 2A and the first power storage sheet 80AC overlap with each other across the first power storage sheet bonding metal plate 70AC.

[0340] The second semiconductor device 1BC is formed by changing the first metal plate 70B to the first metal plate 70BC in the second semiconductor device 1BA. In addition, in this specification, the first metal plate 70BC is also referred to as the second power storage sheet bonding metal plate 70BC.

[0341] The second semiconductor device 1BC is the same as the first semiconductor device 1AC. That is, the second semiconductor device 1BC is the same as the case where the first semiconductor element 2A is renamed as the second semiconductor element 2B and the first power storage sheet bonding metal plate 70AC is renamed as the second power storage sheet bonding metal plate 70BC with respect to the first semiconductor device 1AC.

[0342] The first storage battery piece 80AC is the same as the case where the first storage battery piece 80A of the second embodiment is bent so that the surfaces facing each other for bonding to the first metal plate 70A are formed in the bonding preparation region 73A.

[0343] The second storage battery piece 80BC is the same as the case where the second storage battery piece 80B of the second embodiment is bent so that the surfaces facing each other for bonding to the first metal plate 70B are formed in the bonding preparation region 73B.

[0344] <Examination>

[0345] The circuit diagram of the storage battery pack 100C with the above structure is the same as the ​ circuit diagram shown as the circuit diagram of the storage battery pack 100 of the first embodiment.

[0346] Therefore, in the storage battery pack 100C, the first semiconductor element 2A functions as the same switching element as the first semiconductor element 2A in the storage battery pack 100. In addition, in the storage battery pack 100C, the second semiconductor element 2B functions as the same switching element as the second semiconductor element 2B in the storage battery pack 100.

[0347] (Embodiment 5)

[0348] Hereinafter, a storage battery pack of Embodiment 5, which is formed by changing a part of the structure from the storage battery pack 100B of Embodiment 3, will be described.

[0349] The storage battery pack 100B has a structure in which the first semiconductor element 2A and the second semiconductor element 2B include two vertical MOS transistors, i.e., the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0350] In contrast, the storage battery pack of Embodiment 5 is an example of a structure in which the first semiconductor element and the second semiconductor element of Embodiment 5 do not include the second vertical MOS transistor 20 and include only one vertical MOS transistor, i.e., the first vertical MOS transistor 10.

[0351] Here, for the storage battery pack of Embodiment 5, regarding the constituent elements that are the same as those of the storage battery pack 100, it is considered that they have been described and the same reference numerals are attached, and the detailed description thereof is omitted, and the description will be centered on the differences from the storage battery pack 100.

[0352] <Structure>

[0353] ​ is a plan view showing the structure of the storage battery pack 100D of Embodiment 5. ​ is showing ​ the cross-sectional view taken along the line I - I of ​ is showing​ Cross-sectional view of the cross-section taken along line II-II. ​ In the figure, for a part of the portion that cannot actually be directly recognized, it is illustrated with a dashed line as if it can be recognized.

[0354] As ​ , ​ , ​ As shown in [relevant figures], the battery pack 100D is constituted by changing the first semiconductor device 1AB to the first semiconductor device 1AD, the second semiconductor device 1BB to the second semiconductor device 1BD, and the protection circuit board 60 to the protection circuit board 60D from the battery pack 100B of Embodiment 3.

[0355] The protection circuit board 60D is constituted by deleting the first wiring 61 and the third wiring 63 from the protection circuit board 60.

[0356] The first semiconductor device 1AD is constituted by changing the first semiconductor element 2A to the first semiconductor element 2AD, the insulating material 72 to the conductive material 72D (e.g., solder), and the metal part 85A to the metal part 85AD from the first semiconductor device 1AB.

[0357] ​ is the circuit diagram of the first semiconductor element 2AD.

[0358] As ​ shown, the first semiconductor element 2AD is constituted by deleting the second vertical MOS transistor 20 from the first semiconductor element 2A and accordingly deleting the second gate terminal 129 and the second source terminal 121 from the first semiconductor element 2A.

[0359] Returning again to ​ , ​ , ​ , the description of the structure of the battery pack 100D is continued.

[0360] The conductive material 72D connects the third metal plate 75A to one main surface of the first semiconductor element 2AD. Accordingly, the third metal plate 75A is conducted to the drain electrode 30. Thereby, the first metal plate 70AB has the same potential as the drain electrode 30.

[0361] One or more metal parts 85AD, similar to one or more metal parts 85A in the first semiconductor device 1AB, when the first semiconductor element 2AD is mounted on the mounting substrate 60D, are mounted on the mounting substrate 60D together with the first semiconductor element 2AD. That is, the height of one or more metal parts 85AD from the main surface of the third metal plate 75A is equal to the distance from the main surface of the third metal plate 75A to the other main surface of the first semiconductor element 2AD.

[0362] Here, as described above, the protection circuit board 60D does not have the first wiring 61. Therefore, there is no board connection terminal having the same potential as the first metal plate 70AB.

[0363] In addition, the first semiconductor device 1AD does not necessarily need to be limited to a structure having one or more metal components 85AD.

[0364] The second semiconductor device 1BD is constituted by changing the second semiconductor element 2B to the second semiconductor element 2BD, changing the insulating material 72 to the conductive material 72D, and changing the metal component 85B to the metal component 85BD in the second semiconductor device 1BB.

[0365] The second semiconductor device 1BD is the same as the first semiconductor device 1AD. That is, the second semiconductor device 1BD is the same as the case where the first semiconductor element 2AD is renamed the second semiconductor element 2BD, the first power storage sheet bonding metal plate 70AB is renamed the second power storage sheet bonding metal plate 70BB, and the metal component 85AD is renamed the metal component 85BD with respect to the first semiconductor device 1AD.

[0366] The second semiconductor element 2BD is the same as the first semiconductor element 2AD. That is, the second semiconductor element 2BD is constituted by deleting the second vertical MOS transistor 20 from the second semiconductor element 2B, then deleting the second gate terminal 229 and the second source terminal 221 from the second semiconductor element 2B, and changing the drain electrode 30 to the drain electrode 31.

[0367] Here, as described above, the protection circuit board 60D does not have the third wiring 63. Therefore, there is no board connection terminal having the same potential as the first metal plate 70BB.

[0368] <Examination>

[0369] ​ It is the circuit diagram of the power storage pack 100D having the above structure.

[0370] As ​ shown, the first semiconductor element 2AD functions as a switching element of the current path flowing from the positive terminal 36 of the power storage unit 3 to the power storage pack positive terminal 66.

[0371] That is, by becoming conductive from the drain electrode 30 to the first source terminal 111 as the switching element of the first semiconductor element 2AD, the potential on the drain electrode 30 side becomes higher than the potential of the first source terminal 111, thereby forming a current path in which current flows from the power storage unit 3 in the order of the first power storage sheet 80AB, the first power storage sheet bonding metal plate 70AB, and the first semiconductor element 2AD.

[0372] In addition, the second semiconductor element 2BD functions as a switching element for the current path flowing from the negative terminal 37 of the power storage unit 3 to the power storage pack negative terminal 67.

[0373] That is, by making the second semiconductor element 2BD, which is a switching element, conductive from the drain electrode 31 to the first source terminal 211, the potential on the drain electrode 31 side becomes higher than the potential of the first source terminal 211, thereby forming a current path in which current flows from the power storage unit 3 in the order of the second power storage sheet 80BB, the second power storage sheet bonding metal plate 70BB, and the second semiconductor element 2BD.

[0374] Therefore, the first semiconductor element 2AD, which is a switching element, and the second semiconductor element 2BD, which is a switching element, can control the charging of the power storage unit 3 or the discharging from the power storage unit 3 in the protection circuit board 60D.

[0375] As ​ shown, the power storage pack 100D has, on the high side of the power storage unit 3, a first semiconductor element 2AD, which is a switching element, for controlling the current path flowing from the positive terminal 36 to the power storage pack positive terminal 66, and on the low side of the power storage unit 3, a second semiconductor element 2BD, which is a switching element, for controlling the current path flowing from the negative terminal 37 to the power storage pack negative terminal 67.

[0376] Thereby, the power storage pack 100D can achieve double protection of the power storage unit 3 on the high side and the low side of the power storage unit 3.

[0377] In addition, the power storage pack 100D can achieve double protection of the power storage unit 3 by having a structure in which, as ​ shown, a switching element 300A is also provided on the high side of the power storage unit 3, or by having a structure in which, as ​ shown, a switching element 300B is also provided on the low side of the power storage unit 3.

[0378] Here, when the power storage pack 100D is ​In the case of the structure shown, in a plan view of the protection circuit board 60D, when the shape of the first power storage sheet 80AB is such that it covers the first semiconductor element 2AD and there is room to cover others, or when the second power storage sheet 80BB is such that it covers the second semiconductor element 2BD and there is room to cover others, by arranging the switching element 300A at a position overlapping the first power storage sheet 80AB or the second power storage sheet 80BB in the plan view of the protection circuit board 60D, compared with the case where the switching element 300A is not arranged at a position overlapping the first power storage sheet 80AB or the second power storage sheet 80BB in the plan view of the protection circuit board 60D, the protection circuit board 60D can be miniaturized.

[0379] In addition, in the case where the power storage pack 100D is ​ In the case of the structure shown, by arranging the switching element 300B at a position overlapping the first power storage sheet 80AB or the second power storage sheet 80BB in the plan view of the protection circuit board 60D, compared with the case where the switching element 300B is not arranged at a position overlapping the first power storage sheet 80AB or the second power storage sheet 80BB in the plan view of the protection circuit board 60D, the protection circuit board 60D can be miniaturized.

[0380] Alternatively, the first semiconductor device 1AD may not include the third metal plate 75A, the first main surface of the first metal plate 70AB may be directly connected to one main surface of the first semiconductor element 2AD via the conductive material 72D, the second semiconductor device 1BD may not include the third metal plate 75B, and the first main surface of the first metal plate 70BB may be directly connected to one main surface of the second semiconductor element 2BD via the conductive material 72D.

[0381] (Modification Example 1)

[0382] Hereinafter, a power storage pack of Modification Example 1 formed by changing a part of the structure from the power storage pack 100B of Embodiment 3 will be described.

[0383] The structure of the power storage pack 100B is such that the first semiconductor element 2A and the second semiconductor element 2B included in the power storage pack 100B each include two vertical MOS transistors, namely, the first vertical MOS transistor 10 and the second vertical MOS transistor 20.

[0384] In contrast, the power storage pack of Modification Example 1 is an example of a structure in which the first semiconductor element of Modification Example 1 and the second semiconductor element of Modification Example 1 included in the power storage pack of Modification Example 1 each include three vertical MOS transistors.

[0385] <Structure>

[0386] ​ is the circuit diagram of the first semiconductor element 2AE of the power storage pack 100E in Modification 1 (refer to ​ ).

[0387] As ​ shown, the first semiconductor element 2AE further includes a third vertical MOS transistor 20E with respect to the first semiconductor element 2A of Embodiment 3. In addition, the first semiconductor element 2AE further includes a third gate terminal 139 which is the gate terminal of the third vertical MOS transistor 20E, and a third source terminal 131 which is the source terminal of the third vertical MOS transistor 20E with respect to the first semiconductor element 2A. At this time, the low-concentration impurity layer 33 and the semiconductor substrate 32 function as a common drain region that commons the first drain region of the first vertical MOS transistor 10, the second drain region of the second vertical MOS transistor 20, and the third drain region of the third vertical MOS transistor 20E.

[0388] The second semiconductor element 2BE of the power storage pack 100E in Modification 1 (refer to ​ ) is the same as the first semiconductor element 2AE. More specifically, the second semiconductor element 2BE is the same as the case where the first gate terminal 119 is renamed as the first gate terminal 219, the first source terminal 111 is renamed as the first source terminal 211, the second gate terminal 129 is renamed as the second gate terminal 229, the second source terminal 121 is renamed as the second source terminal 221, the third gate terminal 139 is renamed as the third gate terminal 239, and the third source terminal 131 is renamed as the third source terminal 231 with respect to the first semiconductor element 2AE.

[0389] ​ is the circuit diagram of the power storage pack 100E in Modification 1.

[0390] As ​ shown, the power storage pack 100E is constituted by changing the first semiconductor element 2A to the first semiconductor element 2AE, changing the second semiconductor element 2B to the second semiconductor element 2BE, and adding a power storage pack positive terminal 66E and a power storage pack negative terminal 67E from the power storage pack 100B of Embodiment 3.

[0391] The power storage pack positive terminal 66E and the power storage pack negative terminal 67E are provided, for example, on a protection circuit board (not shown) of Modification 1 which is constituted by adding the power storage pack positive terminal 66E and the power storage pack negative terminal 67E to the protection circuit board 60 of Embodiment 3.

[0392] <Examination>

[0393] As ​As shown, the power storage pack 100E includes, on the high side of the power storage unit 3, a first semiconductor element 2AE as a switching element that controls a dual-system current path including a current path flowing from the positive terminal 36 to the positive terminal 66 of the power storage pack and a current path flowing from the positive terminal 66 of the power storage pack to the positive terminal 36, and a current path flowing from the positive terminal 36 to the positive terminal 66E of the power storage pack and a current path flowing from the positive terminal 66E of the power storage pack to the positive terminal 36. On the low side of the power storage unit 3, it includes a second semiconductor element 2BE as a switching element that controls a dual-system current path including a current path flowing from the negative terminal 37 to the negative terminal 67 of the power storage pack and a current path flowing from the negative terminal 67 of the power storage pack to the negative terminal 37, and a current path flowing from the negative terminal 37 to the negative terminal 67E of the power storage pack and a current path flowing from the negative terminal 67E of the power storage pack to the negative terminal 37.

[0394] Thus, the power storage pack 100E can achieve double protection of the power storage unit 3 in the dual systems on the high side and the low side of the power storage unit 3, respectively.

[0395] (Modification Example 2)

[0396] Hereinafter, a power storage pack of Modification Example 2, which is formed by changing a part of the structure from the power storage pack 100B of Embodiment 3, will be described.

[0397] The power storage pack 100B is an example of a structure in which a first semiconductor element 2A is provided at a position overlapping the first power storage sheet 80AB in a plan view of the protection circuit board 60 and a second semiconductor element 2B is provided at a position overlapping the second power storage sheet 80BB.

[0398] In contrast, the power storage pack of Modification Example 2 is an example of the following structure: with respect to the power storage pack 100B, in a plan view of the protection circuit board of Modification Example 2 included in the power storage pack of Modification Example 2, at a position overlapping the first power storage sheet 80AB, in addition to the first semiconductor element 2A, a third semiconductor element of Modification Example 2 is further provided, and at a position overlapping the second power storage sheet 80BB, in addition to the second semiconductor element 2B, a fourth semiconductor element of Modification Example 2 is further provided.

[0399] ​ It is a circuit diagram of the power storage pack 100F of Modification Example 2.

[0400] As ​As shown, the electricity storage pack 100F has the following structure: with respect to the electricity storage pack 100B of Embodiment 3, in a plan view of the protection circuit board (not shown) of Modification 2, a third semiconductor element 2AF disposed at a position overlapping with the first electricity storage sheet 80AB is added, in a plan view of the protection circuit board of Modification 2, a fourth semiconductor element 2BF disposed at a position overlapping with the second electricity storage sheet 80BB is added, and an electricity storage pack positive terminal 66F and an electricity storage pack negative terminal 67F are added.

[0401] The electricity storage pack positive terminal 66F and the electricity storage pack negative terminal 67F are provided, for example, on the protection circuit board of Modification 2 obtained by adding the electricity storage pack positive terminal 66F and the electricity storage pack negative terminal 67F to the protection circuit board 60 of Embodiment 3.

[0402] The third semiconductor element 2AF is the same as the first semiconductor element 2A. More specifically, the third semiconductor element 2AF is the same as the case where, with respect to the first semiconductor element 2A, the first gate terminal 119 is renamed the first gate terminal 319, the first source terminal 111 is renamed the first source terminal 311, the second gate terminal 129 is renamed the second gate terminal 329, and the second source terminal 121 is renamed the second source terminal 321.

[0403] The fourth semiconductor element 2BF is the same as the first semiconductor element 2A. More specifically, the fourth semiconductor element 2BF is the same as the case where, with respect to the first semiconductor element 2A, the first gate terminal 119 is renamed the first gate terminal 419, the first source terminal 111 is renamed the first source terminal 411, the second gate terminal 129 is renamed the second gate terminal 429, and the second source terminal 121 is renamed the second source terminal 421.

[0404] <Examination>

[0405] As ​As shown, the power storage pack 100F includes, on the high side of the power storage unit 3, a first semiconductor element 2A as a switching element that controls the current path flowing from the positive terminal 36 to the positive terminal 66 of the power storage pack and the current path flowing from the positive terminal 66 of the power storage pack to the positive terminal 36, and a third semiconductor element 2AF as a switching element that controls the current path flowing from the positive terminal 36 to the positive terminal 66F of the power storage pack and the current path flowing from the positive terminal 66F of the power storage pack to the positive terminal 36. On the low side of the power storage unit 3, it includes a second semiconductor element 2B as a switching element that controls the current path flowing from the negative terminal 37 to the negative terminal 67 of the power storage pack and the current path flowing from the negative terminal 67 of the power storage pack to the negative terminal 37, and a fourth semiconductor element 2BF as a switching element that controls the current path flowing from the negative terminal 37 to the negative terminal 67F of the power storage pack and the current path flowing from the negative terminal 67F of the power storage pack to the negative terminal 37.

[0406] Thus, the power storage pack 100F can achieve double protection of the power storage unit 3 in the dual systems on the high side and the low side of the power storage unit 3 respectively.

[0407] Furthermore, in the power storage pack 100F, compared with the structure in which the third semiconductor element 2AF is not arranged at a position overlapping with the first power storage sheet 80AB in the plan view of the protection circuit board in Modification 2, and the fourth semiconductor element 2BF is not arranged at a position overlapping with the first power storage sheet 80AB in the plan view of the protection circuit board in Modification 2, the protection circuit board in Modification 2 can be miniaturized.

[0408] (Modification 3)

[0409] Hereinafter, a power storage pack of Modification 3 formed by changing a part of the structure from the power storage pack 100D of Embodiment 5 will be described.

[0410] The power storage pack 100D is an example of a structure including a power storage unit 3, a first semiconductor element 2AD, and a second semiconductor element 2BD.

[0411] In contrast, the power storage pack of Modification 3 is an example of a structure that, compared with the power storage pack 100D, further includes a power storage unit of Modification 3 similar to the power storage unit 3, a third semiconductor element of Modification 3 similar to the first semiconductor element 2AD, and a fourth semiconductor element of Modification 3 similar to the second semiconductor element 2BD.

[0412] <Structure>

[0413] ​ is the circuit diagram of the power storage pack 100G of Modification 3.

[0414] As ​As shown, the power storage pack 100G is formed by adding a power storage unit 3G, a third semiconductor element 2AG, and a fourth semiconductor element 2BG to the power storage pack 100D of Embodiment 5.

[0415] The power storage unit 3G is the same as the power storage unit 3. More specifically, the power storage unit 3G is the same as the case where the positive terminal 36 of the power storage unit 3 is renamed the positive terminal 36G and the negative terminal 37 is renamed the negative terminal 37G.

[0416] The third semiconductor element 2AG is the same as the first semiconductor element 2AD. More specifically, the third semiconductor element 2AG is the same as the case where, with respect to the first semiconductor element 2AD, the first gate terminal 119 is renamed the first gate terminal 119G, the first source terminal 111 is renamed the first source terminal 111G, and the drain electrode 30 is renamed the drain electrode 30G.

[0417] The fourth semiconductor element 2BG is the same as the second semiconductor element 2BD. More specifically, the fourth semiconductor element 2BG is the same as the case where, with respect to the second semiconductor element 2BD, the first gate terminal 219 is renamed the first gate terminal 219G, the first source terminal 211 is renamed the first source terminal 211G, and the drain electrode 31 is renamed the drain electrode 31G.

[0418] As ​ shown, the first semiconductor element 2AD, the power storage unit 3, the second semiconductor element 2BD, the third semiconductor element 2AG, the power storage unit 3G, and the fourth semiconductor element 2BG are connected in series in this order between the power storage pack positive terminal 66 and the power storage pack negative terminal 67.

[0419] <Examination>

[0420] With the power storage pack 100G having the above structure, double protection of the power storage unit 3 and double protection of the power storage unit 3G can be achieved.

[0421] (Embodiment 6)

[0422] Hereinafter, a power storage pack of Embodiment 6 formed by changing a part of the structure from the power storage pack 100C of Embodiment 4 will be described.

[0423] The power storage pack 100C is an example of a structure having a first semiconductor element 2A on the high side of the power storage unit 3 and a second semiconductor element 2B on the low side of the power storage unit 3.

[0424] In contrast, the power storage pack of Embodiment 6 is an example of a structure having a first semiconductor element 2A and a second semiconductor element 2B on the low side of the power storage unit 3.

[0425] Here, regarding the electricity storage pack of Embodiment 6, for the same constituent elements as those of the electricity storage pack 100C, it is considered that they have been described and the same reference numerals are attached, and their detailed descriptions are omitted, and the description will be centered on the differences from the electricity storage pack 100C.

[0426] <Structure>

[0427] ​ It is a plan view showing the structure of the electricity storage pack 100H of Embodiment 6. ​ It shows ​ a cross-sectional view of the cut section at I-I. ​ It shows ​ a cross-sectional view of the cut section at II-II. In ​ for a part of the part that cannot be directly recognized actually, it is shown by a dotted line as can be recognized in the figure.

[0428] As ​ , ​ , ​ shown, the electricity storage pack 100H is constituted by changing the protection circuit board 60 to a protection circuit board 60H from the electricity storage pack 100C of Embodiment 4.

[0429] The protection circuit board 60H is constituted by changing the first wiring 61 to a first wiring 161, the second wiring 62 to a second wiring 162, and the fourth wiring 64 to a fourth wiring 164 from the protection circuit board 60 of Embodiment 4.

[0430] The first wiring 161 is connected to the positive electrode terminal 66 of the electricity storage pack, and is connected to at least one of more than one metal component 85A via a conductive material 81.

[0431] Accordingly, in the electricity storage pack 100H, in the plan view of the protection circuit board 60H, there is a part that overlaps with a region where current flows between the first storage sheet 80AC and the protection circuit board 60H and a region that overlaps with the first semiconductor element 2A and the first storage sheet 80AC with the first storage sheet bonding metal plate 70AC interposed therebetween.

[0432] The second wiring 162 is connected to the second source terminal 121 via a conductive material 81, and is connected to the first source terminal 211 via a conductive material 81.

[0433] The fourth wiring 164 is connected to the negative electrode terminal 67 of the electricity storage pack, and is connected to the first source terminal 111 via a conductive material 81.

[0434] <Consideration>

[0435] ​ It is a circuit diagram of the electricity storage pack 100H having the above structure.

[0436] As shown in ​ , the first semiconductor element 2A and the second semiconductor element 2B function as switching elements for the current path flowing from the negative terminal 37 of the power storage unit 3 to the negative terminal 67 of the power storage battery pack and the current path flowing from the negative terminal 67 of the power storage battery pack to the negative terminal 37 of the power storage unit 3.

[0437] That is, (1) the first semiconductor element 2A as a switching element becomes conductive from the second source terminal 121 to the first source terminal 111 and the second semiconductor element 2B as a switching element becomes conductive from the second source terminal 221 to the first source terminal 211, so that the potential on the second source terminal 221 side is higher than the potential on the first source terminal 111 side. Thus, a current path is formed in which current flows from the power storage unit 3 in the order of the second power storage sheet 80BC, the second power storage sheet bonding metal plate 70BC, the second semiconductor element 2B, the second wiring 162 of the protection circuit board 60H, the first semiconductor element 2A, and the fourth wiring 164 of the protection circuit board 60H. (2) The first semiconductor element 2A as a switching element becomes conductive from the first source terminal 111 to the second source terminal 121 and the second semiconductor element 2B as a switching element becomes conductive from the first source terminal 211 to the second source terminal 221, so that the potential on the first source terminal 111 side is higher than the potential on the second source terminal 221 side. Thus, a current path is formed in which current flows from the fourth wiring 164 of the protection circuit board 60H in the order of the first semiconductor element 2A, the second wiring 162 of the protection circuit board 60H, the second semiconductor element 2B, the second power storage sheet bonding metal plate 70BC, the second power storage sheet 80BC, and the power storage unit 3.

[0438] Therefore, the first semiconductor element 2A as a switching element and the second semiconductor element 2B as a switching element can control the charging of the power storage unit 3 or the discharging from the power storage unit 3 in the protection circuit board 60H.

[0439] As shown in ​ , the power storage battery pack 100H has the first semiconductor element 2A and the second semiconductor element 2B as switching elements that control the current path flowing from the negative terminal 37 to the negative terminal 67 of the power storage battery pack and the current path flowing from the negative terminal 67 of the power storage battery pack to the negative terminal 37 on the lower side of the power storage unit 3.

[0440] Thus, the power storage battery pack 100H can achieve double protection of the power storage unit 3 on the lower side of the power storage unit 3.

[0441] (Embodiment 7)

[0442] Hereinafter, a method for manufacturing a semiconductor device when manufacturing the first semiconductor device 1AB in a state where it is mounted on the mounting substrate 60 will be described.

[0443] ​ It is a cross-sectional view of the first semiconductor device 1AB during the manufacturing process of each process implemented in the method for manufacturing a semiconductor device.

[0444] As ​ shown, the method for manufacturing a semiconductor device includes ​ the zero-th process shown in ​ the first process shown in ​ the second process shown in ​ the third process shown in ​ the fourth process shown in ​ and the fifth process shown in, a total of 6 processes. In addition, as will be described later, the method for manufacturing a semiconductor device including 5 processes from the first process to the fifth process, excluding the zero-th process, becomes the method for manufacturing the first semiconductor device 1AC in a state where it is mounted on the mounting substrate 60.

[0445] Hereinafter, each process will be described in sequence.

[0446] The zero-th process is the first process to be executed.

[0447] As ​ shown, the zero-th process is a process of connecting the third metal plate 75A having one or more metal components 85A to the first semiconductor element 2A. In addition, in the case of manufacturing the first semiconductor device 1AC in a state where it is mounted on the mounting substrate 60, this zero-th process is not executed.

[0448] The first process is a process executed after the zero-th process is executed, or a process executed first by omitting the zero-th process.

[0449] As ​ shown, the first process is a process of connecting the first semiconductor element 2A to the first main surface of the first metal plate 70AB. In addition, when the first process is executed after the zero-th process is executed, the first semiconductor element 2A is connected to the first main surface via the third metal plate 75A. When the first process is executed first by omitting the zero-th process, that is, in the case of manufacturing the first semiconductor device 1AC in a state where it is mounted on the mounting substrate 60, the first semiconductor element 2A is connected to the first main surface without passing through the third metal plate 75A.

[0450] The second process is a process executed after the first process is executed.

[0451] As ​ shown, the second process is a process of mounting the first semiconductor element 2A on the mounting substrate 60.

[0452] Alternatively, it may also be a manufacturing method in which the second process is performed before the first process.

[0453] The third process is a process performed after the execution of the second process.

[0454] As ​ shown, the third process is a process of joining the second main surface of the second metal plate 80AB facing away from the first main surface to the first metal plate 70AB.

[0455] The fourth process is a process performed after the execution of the third process in a sequence different from the fifth process described later.

[0456] As ​ shown, the fourth process is as follows: the first metal plate 70AB is bent so that (1) there is a portion where the second main surfaces face each other, and (2) in a plan view of the first semiconductor element 2A, there is an overlapping portion between the region where the first metal plate 70AB and the first semiconductor element 2A are connected and the region where the first metal plate 70AB and the second metal plate 80AB are joined, with the first metal plate 70AB in between.

[0457] In the fourth process, as ​ shown, for example, a die can be used to bend the first metal plate 70AB.

[0458] The fifth process is a process performed after the execution of the third process in a sequence different from the above-mentioned fourth process.

[0459] As ​ shown, the fifth process is a process of bending the second metal plate 80AB so that there is a portion where the surfaces joined to the first metal plate 70AB face each other.

[0460] In the fifth process, as ​ shown, for example, a die can be used to bend the second metal plate 80AB.

[0461] (Supplementary)

[0462] As described above, regarding the power storage pack, semiconductor device, and manufacturing method of the semiconductor device according to an embodiment of the present disclosure, explanations have been given based on Embodiments 1 to 7 and Variants 1 to 3. However, the present disclosure is not limited to these embodiments and variants. As long as it does not deviate from the gist of the present disclosure, forms obtained by applying various deformations conceivable by those skilled in the art to these embodiments, and forms constructed by combining constituent elements in different embodiments and variants are also included within the scope of one or more forms of the present disclosure.

[0463] (1) In Embodiment 6, as described above, the metal plate 70AC for bonding the first power storage sheet is bent. In the power storage module 100H, in a plan view of the protection circuit board 60H, there is a portion where a region where current can flow between the first power storage sheet 80AC and the protection circuit board 60H overlaps with a region where the first power storage sheet 80AC, the metal plate 70AC for bonding the first power storage sheet, the first semiconductor element 2A, and the protection circuit board 60H overlap.

[0464] In contrast, even if the metal plate 70AC for bonding the first power storage sheet is not bent, the power storage module 100H can be configured such that, in a plan view of the protection circuit board 60H, there is a portion where a region where current can flow between the first power storage sheet 80AC and the protection circuit board 60H overlaps with a region where the first power storage sheet 80AC, the metal plate 70AC for bonding the first power storage sheet, the first semiconductor element 2A, and the protection circuit board 60H overlap.

[0465] ​ It is a cross-sectional view showing an example of a form, that is, a power storage module 100H having a non-bent metal plate 70AC for bonding the first power storage sheet and a non-bent first power storage sheet 80AC, and in a plan view of the protection circuit board 60H, there is a portion where a region where current can flow between the first power storage sheet 80AC and the protection circuit board 60H overlaps with a region where the first power storage sheet 80AC, the metal plate 70AC for bonding the first power storage sheet, the first semiconductor element 2A, and the protection circuit board 60H overlap.

[0466] In addition, the following structural example can also be considered, that is: ​ In the power storage module 100H having the above-described structure exemplified in [ ], a structural example in which the bonding preparation region 73A includes a portion overlapping with a connection region connected to the first metal plate 70AC and the first semiconductor element 2A in a plan view of the first metal plate 70AC, but the bonding preparation region 73A may not include a portion overlapping with the above connection region in a plan view of the first metal plate 70AC.

[0467] (2) In Embodiment 3, it was described that the power storage module 100B is a structural example in which the metal plate 70AB for bonding the first power storage sheet and the metal plate 70BB for bonding the second power storage sheet are each bent once as shown in [ ]. ​ 、 ​ As a structural example, the power storage module 100B may also be a structure in which the metal plate 70AB for bonding the first power storage sheet and the metal plate 70BB for bonding the second power storage sheet are bent two or more times.

[0468]

[0469] ​ ​ ​​In the case of the structure in which the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB are bent two or more times in the battery pack 100B of Embodiment 3, it represents ​ A sectional view taken along line I-I.

[0470] As ​ shown, in the battery pack 100B of Embodiment 3, the structure may also be such that the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB are bent twice and the first battery plate 80AB and the second battery plate 80BB are not bent.

[0471] Thus, the surface areas of the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB can be made relatively large, so the heat dissipation effects of the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB can be made relatively large.

[0472] In addition, as ​ shown, the structure may also be such that the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB are bent twice and the first battery plate 80AB and the second battery plate 80BB are bent once.

[0473] Thus, the bonding (e.g., welding bonding) of the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB to the first battery plate 80AB and the second battery plate 80BB can be performed at multiple locations, so the bonding strength between the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB and the first battery plate 80AB and the second battery plate 80BB can be made greater. Furthermore, thus, the surface areas of the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB can be made relatively large, so the heat dissipation effects of the first battery plate bonding metal plate 70AB and the second battery plate bonding metal plate 70BB can be made relatively large.

[0474] (3) In Embodiment 2, regarding the battery pack 100A, it has been described that the first battery plate 80A is connected to the first semiconductor element 2A via the first battery plate bonding metal plate 70A, and the second battery plate 80B is connected to the second semiconductor element 2B via the second battery plate bonding metal plate 70B. However, as another structural example, the battery pack 100A may not include the first battery plate bonding metal plate 70A and the second battery plate bonding metal plate 70B, and the first battery plate 80A may be connected to the first semiconductor element 2A without passing through the first battery plate bonding metal plate 70A, and the second battery plate 80B may be connected to the second semiconductor element 2B without passing through the second battery plate bonding metal plate 70B.

[0475] Industrial Applicability

[0476] The present disclosure can be widely applied to a power storage battery pack, a semiconductor device constituting the power storage battery pack, a manufacturing method of the semiconductor device for manufacturing the semiconductor device, and the like.

[0477] Reference Numeral Explanation

[0478] 1A, 1AA, 1AB, 1AC, 1AD First semiconductor device

[0479] 1B, 1BA, 1BB, 1BC, 1BD Second semiconductor device

[0480] 2A, 2AD, 2AE First semiconductor element

[0481] 2A1 First side

[0482] 2B, 2BD, 2BE Second semiconductor element [[ID=2k]]

[0483] 2AF, 2AG Third semiconductor element

[0484] 2BF, 2BG Fourth semiconductor element

[0485] 3, 3G Power storage unit

[0486] 10 First vertical MOS transistor

[0487] 11 First source electrode

[0488] 12, 13, 22, 23 Portions

[0489] 14 First source region

[0490] 15 First gate conductor

[0491] 16 First gate insulating film

[0492] 18 First body region

[0493] 20 Second vertical MOS transistor

[0494] 20E Third vertical MOS transistor

[0495] 21 Second source electrode

[0496] 24 Second source region

[0497] 25 Second gate conductor

[0498] 26 Second gate insulating film

[0499] 28 Second body region

[0500] 30, 30G Metal layer (drain electrode)

[0501] 31, 31G Drain electrode

[0502] 32 Semiconductor substrate

[0503] 33 Low-concentration impurity layer

[0504] 34 Oxide film

[0505] 35 Protective layer

[0506] 36, 36G Positive terminal

[0507] 37, 37G Negative terminal

[0508] 40 Semiconductor layer

[0509] 60, 60A, 60B, 60D, 60H Protection circuit board (mounting board)

[0510] 60C Resin

[0511] 61, 161 First wiring

[0512] 62, 162 Second wiring

[0513] 63 Third wiring

[0514] 64, 164 Fourth wiring

[0515] 66, 66E, 66F Storage battery positive terminal

[0516] 67, 67E, 67F Storage battery negative terminal

[0517] 70A, 70AB, 70AC First battery sheet bonding metal plate (first metal plate)

[0518] 70B, 70BB, 70BC Second battery sheet bonding metal plate (first metal plate)

[0519] 71, 72D, 81 Conductive material

[0520] 72 Insulating material

[0521] 73A, 73B Bonding preparation area

[0522] 74, 74A, 74B, 74C Bending axis

[0523] 75A, 75B Third metal plate

[0524] 76A First substantially straight edge

[0525] 76B Second substantially straight edge

[0526] 77A, 77B Recess

[0527] 80A, 80AB, 80AC first energy storage sheet (second metal plate)

[0528] 80B, 80BB, 80BC Second energy storage sheet (second metal plate)

[0529] 85A, 85B, 85AA, 85BA, 85AD, 85BD metal parts

[0530] 90 Central Line

[0531] 90C Boundary

[0532] 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H battery pack

[0533] 111, 111a, 111b, 111c, 111d, 111e, 111f, 111G, 211, 211G, 311, 411 first source terminal

[0534] 119, 119G, 219, 219G, 319, 419 first gate terminal

[0535] 121, 121a, 121b, 121c, 121d, 121e, 121f, 221, 321, 421 second source terminal

[0536] 129, 229, 329, 429 second gate terminal

[0537] 131 Third source terminal

[0538] 139 Third gate terminal

[0539] 231 Third source terminal

[0540] 239 Third gate terminal

[0541] 300A, 300B switching elements

[0542] A1 First Area

[0543] A2 Second Area

Claims

1. A semiconductor device, characterized in that: It includes: A chip scale package type semiconductor element having a plurality of external connection terminals; and A first metal plate having a portion with a thickness of 0.2 mm or less, The first metal plate is connected to one main surface of the semiconductor element, On the other main surface of the semiconductor element facing away from the one main surface, a substrate connection terminal among the plurality of external connection terminals that is connected to a mounting substrate on which the semiconductor element is mounted is provided, On a second main surface of the first metal plate facing away from the first main surface, a joining preparation area for joining with a second metal plate is provided, and the first main surface is the main surface of the first metal plate that is connected to the semiconductor element, In a plan view of the first metal plate, the joining preparation area does not overlap with a connection area where the first metal plate and the semiconductor element are connected, The potential of the first metal plate is the same as the potential of at least one of the plurality of external connection terminals, The first metal plate can be bent at the portion with a thickness of 0.2 mm or less to have a portion where the second main surfaces face each other, One or more metal components that are mounted on the mounting substrate together with the semiconductor element when the semiconductor element is mounted on the mounting substrate are further provided on the first main surface, In a plan view of the first metal plate, areas where the first main surface is connected to the one or more metal components do not overlap with the joining preparation area.

2. The semiconductor device according to claim 1, characterized in that: The one or more metal components are made of the same material as the first metal plate, The one or more metal components and the first metal plate are integrated.

3. A semiconductor device, characterized in that: It includes: A chip scale package type semiconductor element having a plurality of external connection terminals; and A first metal plate having a portion with a thickness of 0.2 mm or less, The first metal plate is connected to one main surface of the semiconductor element, On the other main surface of the semiconductor element facing away from the one main surface, a substrate connection terminal among the plurality of external connection terminals that is connected to a mounting substrate on which the semiconductor element is mounted is provided, On a second main surface of the first metal plate facing away from the first main surface, a joining preparation area for joining with a second metal plate is provided, and the first main surface is the main surface of the first metal plate that is connected to the semiconductor element, In a plan view of the first metal plate, the joining preparation area does not overlap with a connection area where the first metal plate and the semiconductor element are connected, The potential of the first metal plate is the same as the potential of at least one of the plurality of external connection terminals, The first metal plate can be bent at the portion with a thickness of 0.2 mm or less to have a portion where the second main surfaces face each other, A third metal plate is further provided between the semiconductor element and the first metal plate, The third metal plate is connected to the semiconductor element on the one main surface and is connected to the first metal plate on the first main surface, The above-mentioned first metal plate is connected to the above-mentioned one main surface via the above-mentioned third metal plate.

4. The semiconductor device according to claim 3, wherein: One or more metal components that are mounted on the mounting substrate together with the semiconductor element when the semiconductor element is mounted on the mounting substrate are further provided on the main surface of the third metal plate where the third metal plate is connected to the semiconductor element. In a plan view of the first metal plate, the regions of the main surface that are connected to the one or more metal components do not overlap with the bonding preparation regions.

5. The semiconductor device according to claim 1 or 4, wherein: The first metal plate is bent to have a portion where the second main surfaces face each other. In a plan view of the semiconductor element, there is a portion where the semiconductor element and the bonding preparation region overlap with each other across the first metal plate.

6. The semiconductor device according to claim 1 or 4, wherein: The semiconductor element is mounted on the mounting substrate with its face downward via the substrate connection terminal. The first metal plate is bonded to the second metal plate in the bonding preparation region.

7. The semiconductor device according to claim 5, wherein: The semiconductor element is mounted on the mounting substrate with its face downward via the substrate connection terminal. The first metal plate is bonded to the second metal plate in the bonding preparation region. The second metal plate is bent to have a portion where the surfaces bonded to the first metal plate face each other across the first metal plate. In a plan view of the mounting substrate, there is an overlapping portion where the second metal plate, the first metal plate, the semiconductor element, and the mounting substrate overlap with each other. In a plan view of the mounting substrate, there is a portion where a region where current can flow between the second metal plate and the mounting substrate overlaps with the overlapping portion.

8. A power storage pack, wherein: It includes the semiconductor device according to claim 7, the above-mentioned second metal plate, the above-mentioned mounting substrate, and a power storage unit. The second metal plate is a power storage sheet that is connected to the power storage unit and serves as a conduction path for charging the power storage unit or discharging from the power storage unit. The first metal plate is a metal plate for bonding the power storage sheet that is bonded to the power storage sheet. The mounting substrate is a protection circuit substrate that protects the power storage unit against overcharging or over-discharging. From the power storage unit, the conduction path is formed in the order of the power storage sheet, the metal plate for bonding the power storage sheet, and the semiconductor element, or in the reverse order thereof.

9. The power storage pack according to claim 8, wherein: The one or more metal components are connected to the protection circuit substrate.

10. The power storage pack according to claim 9, wherein: In a plan view of the semiconductor element, the semiconductor element is rectangular and has two sides in a direction parallel to the length direction of the protection circuit substrate. The one or more metal components include two metal components that are arranged opposite to each other along the two sides over at least the entire lengths of the two sides.

11. The electricity storage package according to claim 9, wherein: In a plan view of the semiconductor element, the semiconductor element is rectangular and has two sides in a direction orthogonal to the longitudinal direction of the protection circuit board. The one or more metal components include two metal components that are arranged opposite to each other along the two sides over at least the entire lengths of the two sides.

12. The electricity storage package according to claim 9, wherein: In a plan view of the semiconductor element, the semiconductor element is rectangular. The one or more metal components include four metal components that are arranged near respective corners of the semiconductor element.

13. The electricity storage package according to claim 8, wherein: The semiconductor element is a switching element. The switching element controls charging of the electricity storage unit or discharging from the electricity storage unit in the protection circuit board.

14. The electricity storage package according to claim 13, wherein: In a plan view of the switching element, the switching element has a plurality of regions including a first region and a second region that are adjacent to each other and divide the switching element on the other main surface side. The switching element further includes: A first vertical MOS transistor formed in the first region; and A second vertical MOS transistor formed in the second region. The substrate connection terminals are multiple. The first vertical MOS transistor has on the other main surface: A first source terminal as the substrate connection terminal; and A first gate terminal as the substrate connection terminal that controls the conduction state of the first vertical MOS transistor. The second vertical MOS transistor has on the other main surface: A second source terminal as the substrate connection terminal; and A second gate terminal as the substrate connection terminal that controls the conduction state of the second vertical MOS transistor. The switching element further has a drain electrode common to the first vertical MOS transistor and the second vertical MOS transistor on the one main surface. The drain electrode is connected to the metal plate for bonding the electricity storage sheet via an insulating bonding member. At least one of the one or more metal components is connected to only the first source terminal among the substrate connection terminals via a wiring formed in the protection circuit board.

15. The electricity storage package according to claim 13, wherein: The substrate connection terminals are multiple. The switching element is a vertical MOS transistor, has a source terminal as the substrate connection terminal and a gate terminal as the substrate connection terminal on the other main surface, and has a drain electrode as the external connection terminal on the one main surface. The drain electrode is connected to the metal plate for bonding the electricity storage sheet via a conductive bonding member.

16. A power storage pack, characterized in that ， A semiconductor device according to claim 1 or claim 4, the second metal plate, the mounting substrate, and the electricity storage unit are provided. The second metal plate is bonded to the first metal plate in the bonding preparation region. The second metal plate is connected to the power storage unit and is a power storage sheet that forms a conduction path for charging the power storage unit or discharging from the power storage unit. The first metal plate is a metal plate for bonding the power storage sheet that is bonded to the power storage sheet. The mounting substrate is a protection circuit substrate that protects the power storage unit against overcharging or over-discharging. From the power storage unit, a current path through which current flows is formed in the order of the power storage sheet, the metal plate for bonding the power storage sheet, and the semiconductor element, or in the reverse order thereof. The semiconductor element is a switching element. The switching element controls charging of the power storage unit or discharging from the power storage unit in the protection circuit substrate.

17. A power storage pack, characterized in that, Comprising: A first semiconductor device and a second semiconductor device that are the semiconductor devices according to claim 7; A fourth metal plate that is the second metal plate is bonded to the bonding preparation region in the first semiconductor device. A fifth metal plate that is the second metal plate is bonded to the bonding preparation region in the second semiconductor device. The mounting substrate mounts a first semiconductor element that is the semiconductor element in the first semiconductor device and a second semiconductor element that is the semiconductor element in the second semiconductor device. And A power storage unit, The fourth metal plate is a first power storage sheet connected to the positive terminal of the power storage unit. The fifth metal plate is a second power storage sheet connected to the negative terminal of the power storage unit. The mounting substrate is a protection circuit substrate that protects the power storage unit against overcharging or over-discharging. The first metal plate in the first semiconductor device is a first metal plate for bonding the first power storage sheet that is bonded to the first power storage sheet. The first metal plate in the second semiconductor device is a second metal plate for bonding the second power storage sheet that is bonded to the second power storage sheet. The first semiconductor element is a first switching element. The second semiconductor element is a second switching element. From the power storage unit, a current path through which current flows is formed in the order of the first power storage sheet, the first metal plate for bonding the first power storage sheet, and the first semiconductor element, or in the reverse order thereof. From the power storage unit, a current path through which current flows is formed in the order of the second power storage sheet, the second metal plate for bonding the second power storage sheet, and the second semiconductor element, or in the reverse order thereof. The first switching element and the second switching element control charging of the power storage unit or discharging from the power storage unit in the protection circuit substrate. The substrate connection terminals in the first switching element are plural. The substrate connection terminals in the second switching element are plural. The power storage pack further comprises: A first wiring that is provided on the protection circuit substrate and has the same potential as the first power storage sheet, and is connected to a first substrate connection terminal that is one of the substrate connection terminals of the first switching element; A second wiring that is a second wiring provided on the protection circuit substrate and is connected to one other than the first substrate connection terminal among the substrate connection terminals of the first switching element; The positive terminal of the power storage pack is connected to the second wiring described above; The third wiring is the third wiring provided on the protection circuit board and having the same potential as the second power storage sheet, and is connected to the second substrate connection terminal, which is one of the substrate connection terminals of the second switching element; The fourth wiring is the fourth wiring provided on the protection circuit board and is connected to one of the substrate connection terminals of the second switching element other than the second substrate connection terminal; and The negative terminal of the power storage pack is connected to the fourth wiring.

18. A power storage pack, characterized in that, It includes: A first semiconductor device as the semiconductor device described in claim 7; A fourth metal plate as the second metal plate is joined to the joining preparation region of the first semiconductor device; The mounting substrate mounts the first semiconductor element as the semiconductor element in the first semiconductor device; A chip scale package type second semiconductor element is mounted face down on the mounting substrate; A power storage unit; A second power storage sheet is connected to the positive terminal of the power storage unit; and A metal plate for joining the second power storage sheet is connected to the third main surface with the second semiconductor element and joined to the second power storage sheet with the fourth main surface facing away from the third main surface, and has a portion with a thickness of 0.2 mm or less, The fourth metal plate is a first power storage sheet connected to the negative terminal of the power storage unit, The mounting substrate is a protection circuit board that protects the power storage unit against overcharging or over-discharging, The first metal plate in the first semiconductor device is a first power storage sheet joining metal plate joined to the first power storage sheet, The first semiconductor element is a first switching element, The second semiconductor element is a second switching element, From the power storage unit, a current path for current flow is formed in the order of the first power storage sheet, the first power storage sheet joining metal plate, the first semiconductor element or the reverse order thereof, From the power storage unit, a current path for current flow is formed in the order of the second power storage sheet, the second power storage sheet joining metal plate, the protection circuit board or the reverse order thereof, In a plan view of the protection circuit board, there is an overlapping portion, which is a portion where the second power storage sheet, the second power storage sheet joining metal plate, the second semiconductor element and the protection circuit board overlap, In a plan view of the protection circuit board, there is a portion where a region capable of flowing current between the second power storage sheet and the protection circuit board overlaps with the overlapping portion, The second power storage sheet joining metal plate is bent to have a portion where the fourth main surfaces face each other, In a plan view of the second power storage sheet joining metal plate in the state before bending, the region where the second power storage sheet joining metal plate is joined to the second power storage sheet does not overlap with the region where the second power storage sheet joining metal plate is connected to the second semiconductor element, The first switching element and the second switching element control charging of the power storage unit or discharging from the power storage unit in the protection circuit board. The above-mentioned substrate connection terminals in the above-mentioned first switching element are multiple. The above-mentioned power storage pack further includes: The first wiring is the first wiring provided on the above-mentioned protection circuit board and having the same potential as the above-mentioned first storage sheet, and is connected to one of the above-mentioned substrate connection terminals of the above-mentioned first switching element, that is, the first substrate connection terminal. The second wiring is the second wiring provided on the above-mentioned protection circuit board and is connected to one other than the above-mentioned first substrate connection terminal among the above-mentioned substrate connection terminals of the above-mentioned first switching element. The third wiring is the third wiring provided on the above-mentioned protection circuit board and is connected to the above-mentioned second wiring via the above-mentioned second switching element. The power storage pack negative terminal is connected to the above-mentioned third wiring. The fourth wiring is provided on the above-mentioned protection circuit board and has the same potential as the above-mentioned second storage sheet; and The power storage pack positive terminal is connected to the above-mentioned fourth wiring.

19. A method for manufacturing a semiconductor device, characterized by comprising: including: The sixth step of connecting a third metal plate having one or more metal components to the above-mentioned one main surface of the semiconductor element having a metal layer on one main surface via an insulating material. The first step of, after the above-mentioned sixth step, connecting the above-mentioned semiconductor element to the first main surface of the first metal plate via the above-mentioned third metal plate, and connecting the above-mentioned third metal plate to the above-mentioned first main surface via a conductive material. The second step of, after the above-mentioned first step, mounting the other main surface of the above-mentioned semiconductor element facing away from the above-mentioned one main surface face down on the mounting substrate. The third step of, after the above-mentioned second step, bonding the second metal plate to the second main surface of the above-mentioned first metal plate opposite to the above-mentioned first main surface. The fourth step of, after the above-mentioned third step, bending the above-mentioned first metal plate so as to have a portion where the above-mentioned second main surfaces face each other, and such that in a plan view of the above-mentioned semiconductor element, a region where the above-mentioned first metal plate and the above-mentioned semiconductor element are connected and a region where the above-mentioned first metal plate and the above-mentioned second metal plate are bonded have a portion overlapping with each other across the above-mentioned first metal plate; and The fifth step of, after the above-mentioned third step, bending the above-mentioned second metal plate so as to have a portion where the surfaces bonded to the above-mentioned first metal plate face each other.

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