Communication method, apparatus, device, and storage medium

Abstract

The embodiment of the application provides a communication method, device, equipment and storage medium, the method comprises the following steps: determining target data to be processed, and performing first data processing on the target data, the first data processing comprises data sending and data storage, sending an interrupt signal to a target central processing unit corresponding to the target data, the interrupt signal is used for instructing the target central processing unit to perform second data processing on the target data, and the second data processing is releasing a storage space or service processing occupied by the target data. The method of the application improves the efficiency of data transmission.

Description

Technical Field

[0001] This application belongs to the technical field of communications, specifically relating to a communication method, apparatus, device, and storage medium. Background Technology

[0002] In communication between devices, data transmission can be carried out through communication interfaces. Examples of communication interfaces include Universal Asynchronous Receiver / Transmitter (UART), Serial Peripheral Interface (SPI), and Universal Serial Bus (USB). Each communication interface uses only one hardware channel for transmission.

[0003] When transmitting multiple services simultaneously, multiple communication interfaces can be set up, with different communication interfaces used for different channels; alternatively, a single communication interface can be set up, and a software protocol can be added to add frame formats to the data of each channel. The central processing unit (CPU) can then encapsulate and process the data of each channel to achieve multi-channel service transmission.

[0004] In the above transmission process, setting up multiple communication interfaces increases hardware costs, while setting up a single interface increases CPU overhead, resulting in lower data transmission efficiency. Summary of the Invention

[0005] This application relates to a communication method, apparatus, device, and storage medium, which addresses the shortcomings of low data transmission efficiency in the prior art.

[0006] In a first aspect, embodiments of this application provide a communication method applied in a transceiver processor, comprising:

[0007] The target data to be processed is determined, and the target data is subjected to a first data processing, which includes data transmission and data storage.

[0008] An interrupt signal is sent to the target central processing unit corresponding to the target data. The interrupt signal is used to instruct the target central processing unit to perform a second data processing on the target data. The second data processing is to release the storage space occupied by the target data or to perform business processing.

[0009] In one possible implementation, the first data processing is data transmission; determining the target data to be processed, and performing the first data processing on the target data, including:

[0010] The target data is determined in at least one transmit buffer and then transmitted.

[0011] Accordingly, the second data processing involves releasing the storage space occupied by the target data.

[0012] In one possible implementation, determining the target data in at least one transmit buffer and transmitting the target data includes:

[0013] Determine a first buffer quantity for the at least one transmission buffer, wherein the first buffer quantity is an integer greater than or equal to 1;

[0014] If the first buffer quantity is 1, then the target data is determined in the sending buffer and the target data is sent;

[0015] If the number of the first buffers is greater than 1, then an interrupt feedback type is determined, and the target data is determined in at least one transmit buffer according to the interrupt feedback type, and the target data is transmitted. The interrupt feedback type is used to indicate that an interrupt signal is fed back when the data in a single transmit buffer is successfully transmitted, or that an interrupt signal is fed back after the data in all transmit buffers is successfully transmitted.

[0016] In one possible implementation, the interrupt feedback type indicates that an interrupt signal is fed back when data in a single transmit buffer is successfully transmitted; determining the target data in at least one transmit buffer based on the interrupt feedback type includes:

[0017] Determine the target cache to be polled from among multiple send caches;

[0018] Based on the priority of the target cache, determine the target data volume corresponding to the target cache;

[0019] Based on the target data volume, the target data is determined in the target cache, wherein the data volume of the target data is less than or equal to the target data volume.

[0020] In one possible implementation, the interrupt feedback type indicates that an interrupt signal is fed back after all data in the transmit buffer has been successfully transmitted; determining the target data in at least one transmit buffer according to the interrupt feedback type and transmitting the target data includes:

[0021] Determine the priority of the i-th send buffer, determine the i-th data volume based on the priority of the i-th send buffer, determine the i-th data in the i-th send buffer based on the i-th data volume, and send the i-th data;

[0022] Where i takes the values ​​1, 2, ..., N in sequence, and N is the number of the at least one transmission buffer. The target data includes the data determined in each transmission buffer.

[0023] In one possible implementation, sending an interrupt signal to the target central processing unit corresponding to the target data includes:

[0024] After the target data is successfully transmitted, an interrupt signal is sent to the target central processing unit corresponding to the target cache; or,

[0025] If it is determined that there is no unsent data in the transmit buffer where the target data is located, an interrupt signal is sent to the target central processing unit corresponding to the transmit buffer.

[0026] In one possible implementation, the first data processing is data storage; performing the first data processing on the target data includes:

[0027] The target data is parsed to determine at least one receiving buffer corresponding to the target data, and the parsed target data is stored in the at least one receiving buffer.

[0028] Accordingly, the second data processing is business processing.

[0029] In one possible implementation, storing the parsed target data in the at least one receive buffer includes:

[0030] Determine the second cache number of the at least one receive cache, wherein the second cache number is an integer greater than or equal to 1;

[0031] If the second cache size is 1, then the parsed target data is stored in the receiving cache;

[0032] If the number of the second buffer is greater than 1, the parsed target data is split into received data corresponding to at least one receive buffer, and each received data is stored in the corresponding receive buffer.

[0033] In one possible implementation, sending an interrupt signal to the target central processing unit corresponding to the target data includes:

[0034] After storing the parsed target data in the receive buffer, an interrupt signal is sent to the target central processing unit corresponding to the receive buffer; or,

[0035] After storing each received data into its corresponding receive buffer, an interrupt signal is sent to at least one target central processing unit corresponding to the receive buffer.

[0036] Secondly, embodiments of this application provide a communication device applied in a transceiver processor, comprising:

[0037] A processing module is used to determine the target data to be processed and to perform a first data processing on the target data, the first data processing including data transmission and data storage;

[0038] The sending module is used to send an interrupt signal to the target central processing unit corresponding to the target data. The interrupt signal is used to instruct the target central processing unit to perform a second data processing on the target data. The second data processing is to release the storage space occupied by the target data or to perform business processing.

[0039] In one possible implementation, the first data processing is data transmission; the processing module is specifically used for:

[0040] The target data is determined in at least one transmit buffer and then transmitted.

[0041] Accordingly, the second data processing involves releasing the storage space occupied by the target data.

[0042] In one possible implementation, the processing module is specifically used for:

[0043] Determine a first buffer quantity for the at least one transmission buffer, wherein the first buffer quantity is an integer greater than or equal to 1;

[0044] If the first buffer quantity is 1, then the target data is determined in the sending buffer and the target data is sent;

[0045] If the number of the first buffers is greater than 1, then an interrupt feedback type is determined, and the target data is determined in at least one transmit buffer according to the interrupt feedback type, and the target data is transmitted. The interrupt feedback type is used to indicate that an interrupt signal is fed back when the data in a single transmit buffer is successfully transmitted, or that an interrupt signal is fed back after the data in all transmit buffers is successfully transmitted.

[0046] In one possible implementation, the interrupt feedback type indicates that an interrupt signal is fed back when data in a single transmit buffer is successfully transmitted; the processing module is specifically used for:

[0047] Determine the target cache to be polled from among multiple send caches;

[0048] Based on the priority of the target cache, determine the target data volume corresponding to the target cache;

[0049] Based on the target data volume, the target data is determined in the target cache, wherein the data volume of the target data is less than or equal to the target data volume.

[0050] In one possible implementation, the interrupt feedback type indicates that an interrupt signal is fed back after all data in the transmit buffer has been successfully transmitted; the processing module is specifically used for:

[0051] Determine the priority of the i-th send buffer, determine the i-th data volume based on the priority of the i-th send buffer, determine the i-th data in the i-th send buffer based on the i-th data volume, and send the i-th data;

[0052] Where i takes the values ​​1, 2, ..., N in sequence, and N is the number of the at least one transmission buffer. The target data includes the data determined in each transmission buffer.

[0053] In one possible implementation, the sending module is specifically used for:

[0054] After the target data is successfully transmitted, an interrupt signal is sent to the target central processing unit corresponding to the target cache; or,

[0055] If it is determined that there is no unsent data in the transmit buffer where the target data is located, an interrupt signal is sent to the target central processing unit corresponding to the transmit buffer.

[0056] In one possible implementation, the first data processing is data storage; the processing module is specifically used for:

[0057] The target data is parsed to determine at least one receiving buffer corresponding to the target data, and the parsed target data is stored in the at least one receiving buffer.

[0058] Accordingly, the second data processing is business processing.

[0059] In one possible implementation, the processing module is specifically used for:

[0060] Determine the second cache number of the at least one receive cache, wherein the second cache number is an integer greater than or equal to 1;

[0061] If the second cache size is 1, then the parsed target data is stored in the receiving cache;

[0062] If the number of the second buffer is greater than 1, the parsed target data is split into received data corresponding to at least one receive buffer, and each received data is stored in the corresponding receive buffer.

[0063] In one possible implementation, the sending module is specifically used for:

[0064] After storing the parsed target data in the receive buffer, an interrupt signal is sent to the target central processing unit corresponding to the receive buffer; or,

[0065] After storing each received data into its corresponding receive buffer, an interrupt signal is sent to at least one target central processing unit corresponding to the receive buffer.

[0066] Thirdly, this application provides a chip on which a computer program is stored, and when the computer program is executed by the chip, it implements the communication method as described in any of the first aspects.

[0067] Fourthly, this application provides a chip module on which a computer program is stored, and when the computer program is executed by the chip module, it implements the communication method as described in any of the first aspects.

[0068] Fifthly, embodiments of this application provide an electronic device, including: a memory, a processor, and a transceiver;

[0069] The memory stores computer-executed instructions;

[0070] The processor executes computer execution instructions stored in the memory to implement the communication method as described in any of the first aspects.

[0071] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the communication method described in any one of the first aspects.

[0072] In a seventh aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the communication method described in any one of the first aspects.

[0073] This application provides a communication method, apparatus, device, and storage medium. In this method, target data to be processed is determined, and the target data undergoes first data processing, including data transmission and data storage. An interrupt signal is sent to the target central processing unit (CPU) corresponding to the target data. The interrupt signal instructs the CPU to perform second data processing, which involves releasing the storage space occupied by the target data or performing business processing. This reduces the CPU load by using a transceiver processor, ensuring timely data processing and enabling multiple CPUs to share a single communication interface, thus improving data transmission efficiency. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 A schematic diagram of a general asynchronous transceiver communication structure provided in this application embodiment;

[0076] Figure 2 A schematic diagram of the frame structure of a universal asynchronous transceiver provided in an embodiment of this application;

[0077] Figure 3 This is a schematic diagram of an existing application scenario provided in an embodiment of this application;

[0078] Figure 4 A flowchart illustrating a communication method provided in an embodiment of this application;

[0079] Figure 5 A flowchart illustrating another communication method provided in an embodiment of this application;

[0080] Figure 6 A schematic diagram illustrating a process for sending an interrupt signal, provided in an embodiment of this application;

[0081] Figure 7 A schematic diagram illustrating another process for sending an interrupt signal, provided in an embodiment of this application;

[0082] Figure 8 A schematic diagram illustrating another method for transmitting an interrupt signal, provided in an embodiment of this application;

[0083] Figure 9 A flowchart illustrating yet another communication method provided in an embodiment of this application;

[0084] Figure 10 A flowchart illustrating another communication method provided in an embodiment of this application;

[0085] Figure 11 A flowchart illustrating yet another communication method provided in an embodiment of this application;

[0086] Figure 12 A schematic diagram illustrating another process for sending an interrupt signal, provided in an embodiment of this application;

[0087] Figure 13 A schematic diagram illustrating another method for transmitting an interrupt signal, provided in an embodiment of this application;

[0088] Figure 14A schematic diagram illustrating another process for sending an interrupt signal, provided in an embodiment of this application;

[0089] Figure 15 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0090] Figure 16 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0091] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0092] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0093] It should be noted that although the terms "first," "second," etc., are used to describe various types of information in the embodiments of this application, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. Optionally, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information.

[0094] It should be understood that the terms "comprising" or "including" indicate the presence of the previously mentioned features, steps, or operations, but do not preclude the presence, occurrence, or addition of one or more other features, steps, or operations. The terms "and / or," etc., used in this application can be interpreted as inclusive, or mean any one or any combination thereof. Optionally, "A and / or B" means "any one of the following: A; B; A and B." Additionally, the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0095] In communication between devices, data transmission can be carried out through communication interfaces. Examples of communication interfaces include Universal Asynchronous Receiver / Transmitter (UART), Serial Peripheral Interface (SPI), and Universal Serial Bus (USB). Each communication interface uses only one hardware channel for transmission.

[0096] Below, in conjunction with Figure 1 This section explains the communication process using a universal asynchronous transceiver.

[0097] Figure 1 This is a schematic diagram illustrating the structure of a universal asynchronous transceiver communication system provided in an embodiment of this application. Please refer to [link / reference]. Figure 1 , Figure 1 It may include device A and device B. Device A may include a first universal asynchronous transceiver (UAST), and device B may include a second UAST.

[0098] The first or second general asynchronous transceiver may include four interfaces.

[0099] The four interfaces will be explained below with reference to Table 1.

[0100] Table 1

[0101]

[0102] The first universal asynchronous transceiver includes four interfaces: a first transmit interface, a first receive interface, a first request to transmit interface, and a first enable to transmit interface. The second universal asynchronous transceiver includes four interfaces: a second transmit interface, a second receive interface, a second request to transmit interface, and a second enable to transmit interface.

[0103] The first sending interface can be connected to the second receiving interface, the first receiving interface can be connected to the second sending interface, the first request sending interface can be connected to the second allow sending interface, and the first allow sending interface can be connected to the second request sending interface.

[0104] When device A sends data to the second receiving interface of device B through the first sending interface, if device B encounters an abnormal situation, the state of the second sending interface of device B switches to a high level. The abnormal situation may be that device B's receiving buffer is insufficient.

[0105] When the state of the second request sending interface switches to a high level, the first enable sending interface in device A connects to the second request sending interface. When the first enable sending interface detects that the second request sending interface has switched to a high level, device A stops sending data.

[0106] When the state of the second request sending interface switches from a high level to a low level, the first enable sending interface detects that the second request sending interface has switched to a low level, and device A continues to send data.

[0107] Below, in conjunction with Figure 2 The frame structure of the Universal Asynchronous Receiver / Transmitter (UART) is explained.

[0108] Figure 2 This is a schematic diagram of the frame structure of a universal asynchronous transceiver provided in an embodiment of this application. Please refer to... Figure 2 , Figure 2 It can include start bit, data bit, parity bit and stop bit.

[0109] The start bit can be used to indicate the start of data transmission.

[0110] For example, sending a 1-bit logic 0 (low level) indicates the start of data transmission.

[0111] Data bits can include 5 to 8 bits of data.

[0112] For example, the data is 8 bits, or the data is 7 bits of ASCII code.

[0113] The parity bit can be used for parity checking.

[0114] For example, in the data bits and parity bits, if the number of 1s is even, the parity bit is represented as even parity; if the number of 1s is odd, the parity bit is represented as odd parity.

[0115] The stop bit is used to indicate the end of data transmission.

[0116] For example, it could be a 1-bit, 1.5-bit, or 2-bit logic 1 (high level) to indicate the end of data transmission.

[0117] In related technologies, when multiple channels are transmitted simultaneously, multiple communication interfaces can be set up, with different communication interfaces used for different channels; alternatively, a single communication interface can be set up, and a software protocol can be added to add frame formats to the data of each channel. The central processing unit (CPU) can then encapsulate and process the data of each channel to achieve multi-channel service transmission.

[0118] Below, in conjunction with Figure 3This section explains the scenario of setting up a single communication interface to transmit multi-channel services.

[0119] Figure 3 This is a schematic diagram of an existing application scenario provided for an embodiment of this application. Please refer to [link / reference]. Figure 3 , Figure 3 The device may include device C and device D. Device C may include a third universal asynchronous transceiver, a third central processing unit, a third transmitting channel, and a third receiving channel, while device D may include a fourth universal asynchronous transceiver, a fourth central processing unit, a fourth transmitting channel, and a fourth receiving channel.

[0120] The third universal asynchronous transceiver can be connected to the third central processing unit through the third transmit channel and the third receive channel, and the fourth universal asynchronous transceiver can be connected to the fourth central processing unit through the fourth transmit channel and the fourth receive channel. The third universal asynchronous transceiver can also be connected to the fourth universal asynchronous transceiver.

[0121] Assume device C transmits multi-channel services to device D. In device C, a third central processing unit (CPU) encapsulates the data to be transmitted from each channel and sequentially sends the encapsulated data to a third universal asynchronous transceiver (UART) via a third transmit channel. The third UART then transmits the data to a fourth UART. The fourth UART can then send the data to a fourth CPU via a fourth receive channel. The fourth CPU processes the received data and distributes it to the corresponding channels to complete the multi-channel service transmission.

[0122] In the above transmission process, setting up multiple communication interfaces increases hardware costs, while setting up a single interface increases CPU overhead. Due to the increased CPU overhead, the CPU needs to operate at a high clock frequency for a longer period of time, resulting in lower data transmission efficiency.

[0123] To address the aforementioned technical problems, embodiments of this application provide a communication method. This method, applied to a transceiver processor, determines target data to be processed, performs first data processing on the target data, and then sends an interrupt signal to the target central processing unit corresponding to the target data. In this way, the transceiver processor reduces the load on the central processing unit, ensures timely data processing, and allows multiple central processing units to share a single communication interface, thereby improving data transmission efficiency.

[0124] The technical solutions shown in this application will now be described in detail through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; for the same or similar content, the description will not be repeated in different embodiments.

[0125] Figure 4 This is a flowchart illustrating a communication method provided in an embodiment of this application. The execution entity in this embodiment can be a transceiver processor, which can be implemented through a combination of software and hardware. Please refer to... Figure 4 The method includes:

[0126] S401. Determine the target data to be processed and perform the first data processing on the target data.

[0127] The target data can be data to be sent, or data to be stored that is forwarded through the communication interface. The communication interface can be used to receive data sent by other devices.

[0128] The first data processing may include data transmission and data storage.

[0129] If a send command is received from the target central processing unit, the target data to be processed is determined according to the send command, and the target data is sent; if data to be processed is received from the communication interface, the target data to be processed is determined from the data to be processed, and the target data is stored.

[0130] The sending instruction may include a sending buffer address. The sending instruction can be used to instruct the transceiver processor to obtain the target data to be processed from the sending buffer address and enable the transceiver processor to perform sending processing.

[0131] The communication interface can be used to receive data to be processed from other devices and send the data to the transceiver processor.

[0132] The data to be processed may include multiple frames of data, and the frame structure of each frame of data may include start bit, data bit, parity bit and stop bit.

[0133] Alternatively, the target data can be data located in the data bits.

[0134] Optionally, when the first data processing is data transmission, the target data to be processed can be determined and the target data can be processed in the following way: the target data is determined in at least one transmission buffer and the target data is transmitted; correspondingly, the second data processing is to release the storage space occupied by the target data.

[0135] The transmit buffer can be pre-configured by the central processing unit. The transmit buffer can include multiple transmit buffer addresses in the storage space, and these addresses can store the target data to be processed.

[0136] Optionally, when the first data processing is data storage, the target data can be processed in the following way: the target data is parsed to determine at least one receiving buffer corresponding to the target data, and the parsed target data is stored in at least one receiving buffer; correspondingly, the second data processing is business processing.

[0137] The target data can be the data received by the transceiver processor from the communication interface in a single transaction, or the sum of the data received by the transceiver processor from the communication interface multiple times.

[0138] Parsing can be used to parse the target data and determine the receive buffer identifier corresponding to the target data. The receive buffer identifier indicates the receive buffer corresponding to the target data, and the receive buffer can store the target data. The target CPU can retrieve the target data from the receive buffer.

[0139] S402: Send an interrupt signal to the target central processing unit corresponding to the target data.

[0140] The target data can be the processing data corresponding to the target central processing unit in at least one central processing unit. The at least one central processing unit can be located in the device where the transceiver processor is located.

[0141] The target central processing unit can be a single central processing unit or multiple central processing units.

[0142] Interrupt signals can be used to instruct the target central processing unit to perform secondary data processing on the target data, which may involve releasing the storage space occupied by the target data or performing business processing.

[0143] After data transmission or data storage is completed, an interrupt signal is sent to the target central processing unit corresponding to the target data to instruct the target central processing unit to release the storage space occupied by the target data or perform business processing.

[0144] Optionally, after the target central processing unit performs business processing, it can also configure a new receive buffer for the transceiver processor to store data.

[0145] The communication method provided in this embodiment determines the target data to be processed and performs a first data processing on the target data, which includes data transmission and data storage. An interrupt signal is then sent to the target central processing unit (CPU) corresponding to the target data. The interrupt signal instructs the CPU to perform a second data processing, which involves releasing the storage space occupied by the target data or performing business processing. In this way, by using a transceiver processor, the CPU load can be reduced, ensuring timely data processing, and multiple CPUs can share a single communication interface, thus improving data transmission efficiency.

[0146] Below, in conjunction with Figure 5 The process of first data processing being data transmission and second data processing being the release of storage space occupied by the target data is explained.

[0147] Figure 5 This is a flowchart illustrating another communication method provided in an embodiment of this application. Based on the above embodiments, see [link to relevant documentation]. Figure 5 The method includes:

[0148] S501, Determine the first buffer quantity for at least one transmit buffer.

[0149] The first cache size can be an integer greater than or equal to 1.

[0150] At least one transmit buffer associated with at least one central processing unit can be identified, and the first buffer number of the at least one transmit buffer can be determined.

[0151] S502. If the first buffer quantity is 1, then determine the target data in the sending buffer and send the target data.

[0152] If the first cache size is 1, obtain at least one transmit cache address sent by the central processing unit, determine the target data in the transmit cache corresponding to the transmit cache address, and send the target data.

[0153] For example, suppose the device may include a universal asynchronous transceiver, a transceiver processor, multiple central processing units and a transmit buffer.

[0154] Multiple central processing units (CPUs) can send the cache address corresponding to each CPU in the transmit buffer to the transceiver processor. The transceiver processor can then set the cache addresses corresponding to the CPUs in the transmit buffer according to their priorities, so that the transceiver processor can determine the target data in the transmit buffer and send the target data to the universal asynchronous transceiver.

[0155] S503. If the number of first buffers is greater than 1, determine the interrupt feedback type, and determine the target data in at least one transmit buffer according to the interrupt feedback type, and transmit the target data.

[0156] Interrupt feedback type can be used to indicate whether an interrupt signal is fed back when data in a single transmit buffer is successfully transmitted, or when an interrupt signal is fed back after all data in the transmit buffer is successfully transmitted.

[0157] Feeding an interrupt signal when data in a single transmit buffer is successfully transmitted can mean feeding an interrupt signal every time data in the transmit buffer is successfully transmitted.

[0158] The interrupt signal fed back after all data in the transmit buffer has been successfully transmitted indicates that an interrupt signal is fed back when it is determined that there is no untransmitted data in the transmit buffer where the target data is located.

[0159] If the number of first buffers is greater than 1, the interrupt feedback type can be determined, and the target data can be determined in at least one transmit buffer according to the interrupt feedback type. The target data is then encapsulated and transmitted.

[0160] S504. After the target data is successfully transmitted, send an interrupt signal to the target CPU corresponding to the target buffer; or, when it is determined that there is no untransmitted data in the transmit buffer where the target data is located, send an interrupt signal to the target CPU corresponding to the transmit buffer.

[0161] The target central processing unit (CPU) can be one of at least one CPU. The transceiver processor device may include at least one CPU. Specifically, there is a correspondence between a transmit buffer and one of the at least one CPUs.

[0162] Interrupt signals can be used to instruct the target CPU to release the storage space occupied by the target data.

[0163] The number of processors in the central processing unit (CPU) of the transceiver processor device can be determined. If there is only one processor, the CPU is the target CPU. After successful transmission of the target data, an interrupt signal is sent to the target CPU; or, if it is determined that there is no untransmitted data in the transmit buffer containing the target data, an interrupt signal is sent to the target CPU. If there are multiple processors, after successful transmission of the target data, an interrupt signal is sent to the target CPU corresponding to the target buffer; or, if it is determined that there is no untransmitted data in the transmit buffer containing the target data, an interrupt signal is sent to the target CPU corresponding to the transmit buffer.

[0164] Below, in conjunction with Figure 6 An example is given for the case where the first cache size is 1 and the number of processors is multiple.

[0165] Figure 6 A flowchart illustrating the transmission of an interrupt signal provided in this application embodiment can be found here. Figure 6 , Figure 6 It may include a general asynchronous transceiver, a transceiver processor, three central processing units (CPUs), and a transmit buffer. The three CPUs are CPU 1, CPU 2, and CPU 3.

[0166] Assuming the target data corresponding to the send buffer is successfully sent, the CPUs corresponding to the target data are CPU1, CPU2, and CPU3.

[0167] Interrupt signals can be sent to CPU 1, CPU 2 and CPU 3 respectively. The interrupt signals can be used to instruct the CPU to release the storage space occupied by the target data in the transmit buffer.

[0168] Alternatively, assuming that there is no unsent data in the transmit buffer where the target data is located, an interrupt signal can be sent to CPU 1, CPU 2 and CPU 3. The interrupt signal can be used to instruct the CPU to release the storage space occupied by the transmit buffer where the target data is located.

[0169] Below, in conjunction with Figure 7 An example is given for the case where the number of first caches is greater than 1 and the number of processors is 1.

[0170] Figure 7 For another flowchart illustrating the transmission of an interrupt signal provided in this application embodiment, please refer to... Figure 7 , Figure 7 It may include a general asynchronous transceiver, a transceiver processor, a central processing unit and three transmit buffers, namely transmit buffer 1, transmit buffer 2 and transmit buffer 3.

[0171] Assuming the target data corresponding to transmit buffer 1 is successfully transmitted, an interrupt signal can be sent to the central processing unit. The interrupt signal can be used to instruct the central processing unit to release the storage space occupied by the target data in transmit buffer 1.

[0172] Alternatively, assuming that there is no unsent data in transmit buffer 1 where the target data is located, an interrupt signal can be sent to the central processing unit. The interrupt signal can be used to instruct the central processing unit to release the storage space occupied by transmit buffer 1 where the target data is located.

[0173] Below, in conjunction with Figure 8 An example is given for the case where the number of first caches is greater than 1 and there are multiple processors.

[0174] Figure 8 A flowchart illustrating another method for transmitting an interrupt signal, as provided in this application embodiment, can be found here. Figure 8 , Figure 8 It can include a general asynchronous transceiver, a transceiver processor, three central processing units and three transmit buffers.

[0175] Assuming the target data corresponding to transmit buffer 1 is successfully transmitted, and transmit buffer 1 corresponds to central processing unit 2, the target central processing unit can be determined to be central processing unit 2. An interrupt signal is sent to central processing unit 2, and the interrupt signal can be used to instruct central processing unit 2 to release the storage space occupied by the target data in transmit buffer 1.

[0176] Alternatively, assuming that there is no unsent data in the transmit buffer 1 where the target data is located, and the transmit buffer 1 corresponds to the central processing unit 2, an interrupt signal can be sent to the central processing unit 2. The interrupt signal can be used to instruct the central processing unit 2 to release the storage space occupied by the transmit buffer 1 where the target data is located.

[0177] The implementation details of each step in this application embodiment can be found in the description of the corresponding steps or operations in the above method embodiments; repeated content will not be repeated.

[0178] The communication method provided in this embodiment determines the first buffer quantity of at least one transmit buffer. If the first buffer quantity is 1, target data is determined in the transmit buffer and transmitted. If the first buffer quantity is greater than 1, an interrupt feedback type is determined, and target data is determined in at least one transmit buffer according to the interrupt feedback type and transmitted. After the target data is successfully transmitted, an interrupt signal is sent to the target CPU corresponding to the target buffer. Alternatively, if it is determined that there is no untransmitted data in the transmit buffer containing the target data, an interrupt signal is sent to the target CPU corresponding to the transmit buffer. In this way, the transceiver processor can reduce the load on the CPU, ensure timely data processing, and enable multiple CPUs to share a single communication interface, thereby improving data transmission efficiency.

[0179] Below, in conjunction with Figure 9 The process of determining the target data in at least one transmit buffer and transmitting the target data is explained when an interrupt signal is fed back when the interrupt feedback type indicates that the data in a single transmit buffer has been successfully transmitted.

[0180] Figure 9 This is a flowchart illustrating another communication method provided in an embodiment of this application. Based on the above embodiments, see [link to relevant documentation]. Figure 9 The method includes:

[0181] S901. Determine the target cache to be polled among multiple send caches.

[0182] The target cache can be a cache of data to be sent among multiple send caches.

[0183] It can obtain the sending order corresponding to multiple sending caches, determine whether there is a historical cache of the last sent target data, if not, then the sending cache corresponding to the first order in the sending order is determined as the target cache to be polled; if it exists, then the target cache to be polled is determined according to the sending order and the historical cache.

[0184] For example, suppose there are multiple send buffers, namely buffer 1, buffer 2, buffer 3 and buffer 4, and the sending order is buffer 1, buffer 2, buffer 3 and buffer 4 respectively.

[0185] If there is no historical cache of the last time the target data was sent, then cache 1 is determined as the target cache; if there is a historical cache of the last time the target data was sent, and the historical cache is cache 3, then cache 4 is determined as the target cache.

[0186] S902. Determine the target data volume corresponding to the target cache based on the priority of the target cache.

[0187] The higher the priority of the send buffer, the larger the target data volume corresponding to the send buffer.

[0188] The target data volume can be the maximum amount of data that the target cache is allowed to send in a single transaction.

[0189] It can obtain the priority of the target cache and determine the target data volume corresponding to the target cache based on the priority of the target cache.

[0190] S903. Based on the target data volume, determine the target data in the target cache and send the target data.

[0191] The amount of target data is less than or equal to the target data volume.

[0192] It can determine whether the data to be sent in the target cache is greater than the target data size. If so, the data corresponding to the target data size in the data to be sent is determined as the target data; otherwise, the data to be sent is determined as the target data and the target data is sent.

[0193] The implementation details of each step in this application embodiment can be found in the description of the corresponding steps or operations in the above method embodiments; repeated content will not be repeated.

[0194] The communication method provided in this embodiment determines the target cache to be polled from multiple transmit caches, determines the target data volume corresponding to the target cache based on the priority of the target cache, and determines the target data in the target cache based on the target data volume, wherein the data volume of the target data is less than or equal to the target data volume. In this way, the load on the central processing unit can be reduced by the transceiver processor, ensuring that data can be processed in a timely manner, and enabling multiple central processing units to share a single communication interface, thereby improving the efficiency of data transmission.

[0195] Below, in conjunction with Figure 10 The process of determining the target data in at least one transmission buffer and sending the target data according to the interrupt feedback type when the interrupt feedback type indicates that all data in the transmission buffer has been successfully transmitted and an interrupt signal is fed back is explained (S503).

[0196] Figure 10 This is a flowchart illustrating another communication method provided in an embodiment of this application. Based on the above embodiments, see [link to relevant documentation]. Figure 10 The method includes:

[0197] S1001. Determine the priority of the i-th transmit buffer.

[0198] Priorities can be pre-configured by the central processing unit.

[0199] The priority of the i-th send buffer can be determined from the priorities corresponding to each send buffer.

[0200] S1002. Determine the amount of data of the i-th data according to the priority of the i-th transmit buffer.

[0201] The amount of data i can be the maximum amount of data that can be sent in a single transmission buffer.

[0202] The first mapping relationship can be obtained, and the amount of data of the i-th sending buffer can be determined based on the priority of the i-th sending buffer and the first mapping relationship.

[0203] The first mapping relationship may include the priorities of multiple sending buffers and the maximum amount of data that can be sent in a single transmission corresponding to the priority of each sending buffer.

[0204] S1003. Determine the i-th data in the i-th transmission buffer based on the i-th data volume, and send the i-th data.

[0205] It can be determined whether the data to be sent in the i-th send buffer is greater than the i-th data quantity. If so, the data corresponding to the i-th data quantity in the data to be sent is determined as the i-th data; if not, the data to be sent is determined as the i-th data, and the i-th data is sent.

[0206] In steps S1001-S1003, i takes the values ​​1, 2, ..., N in sequence, where N is the number of at least one transmit buffer, and the target data includes the data determined in each transmit buffer.

[0207] The implementation details of each step in this application embodiment can be found in the description of the corresponding steps or operations in the above method embodiments; repeated content will not be repeated.

[0208] The communication method provided in this embodiment determines the priority of the i-th transmit buffer, determines the i-th data volume based on the priority of the i-th transmit buffer, determines the i-th data in the i-th transmit buffer based on the i-th data volume, and transmits the i-th data; where i takes values ​​of 1, 2, ..., N, and N is the number of at least one transmit buffer, and the target data includes the data determined in each transmit buffer. In this way, the transceiver processor can reduce the load on the central processing unit, ensure timely data processing, and enable multiple central processing units to share a single communication interface, thereby improving data transmission efficiency.

[0209] Below, in conjunction with Figure 11 The process of first data processing being data storage and second data processing being business processing is explained.

[0210] Figure 11 This is a flowchart illustrating another communication method provided in an embodiment of this application. Based on the above embodiments, see [link to relevant documentation]. Figure 11 The method includes:

[0211] S1101. Determine the number of second buffers for at least one receive buffer, and determine whether the number of second buffers is 1.

[0212] If so, then execute S1102;

[0213] If not, then execute S1104.

[0214] The second cache size can be an integer greater than or equal to 1.

[0215] It can determine at least one receive buffer associated with at least one central processing unit, determine the number of second buffers of at least one receive buffer, and determine whether the number of second buffers is 1. If yes, then execute S1102; if no, then execute S1104.

[0216] S1102. Store the parsed target data in the receive buffer.

[0217] After S1102, execute S1103.

[0218] The target data can be parsed and processed, and the parsed target data can be stored in the receiving buffer.

[0219] S1103. Send an interrupt signal to the target central processing unit corresponding to the receive buffer.

[0220] The target central processing unit can be one or more.

[0221] Based on the parsed target data, at least one target central processing unit corresponding to the target data is determined, and an interrupt signal is sent to at least one target central processing unit.

[0222] Below, in conjunction with Figure 12 An example is given for the case where the second cache size is 1 and interrupt signals are sent to multiple target CPUs.

[0223] Figure 12 For another flowchart illustrating the transmission of an interrupt signal provided in this application embodiment, please refer to... Figure 12 , Figure 12 It may include a general asynchronous transceiver, a transceiver processor, three central processing units (CPUs) and one receive buffer, wherein the three CPUs are CPU 1, CPU 2 and CPU 3.

[0224] Assume that the parsed target data corresponds to CPU 1 and CPU 3.

[0225] The transceiver processor stores the parsed target data in the receive buffer and sends a first interrupt signal to the central processing unit 1, which instructs the central processing unit 1 to perform service processing. It also sends a second interrupt signal to the central processing unit 3, which instructs the central processing unit 3 to perform service processing.

[0226] S1104. Split the parsed target data into at least one receive buffer corresponding to receive data, and store each receive data into the corresponding receive buffer.

[0227] The target data can be parsed to determine at least one cache identifier corresponding to the target data. The parsed target data can be split into at least one receive data corresponding to at least one receive cache based on the at least one cache identifier, and each receive data can be stored in the corresponding receive cache.

[0228] S1105. Send an interrupt signal to at least one target central processing unit corresponding to the receive buffer.

[0229] The number of processors corresponding to at least one central processing unit can be determined. When the number of processors is 1, the central processing unit is the target central processing unit, and an interrupt signal is sent to the target central processing unit corresponding to the receive buffer. When the number of processors is multiple, at least one target central processing unit corresponding to at least one receive buffer is determined among the multiple central processing units, and an interrupt signal is sent to at least one target central processing unit respectively.

[0230] Below, in conjunction with Figure 13 The process of sending an interrupt signal to the target central processing unit corresponding to the receiving cache is illustrated with an example when there are multiple second caches and only one processor.

[0231] Figure 13 A flowchart illustrating another method for transmitting an interrupt signal, as provided in this application embodiment, can be found here. Figure 13 , Figure 13 It may include a universal asynchronous transceiver, a transceiver processor, a central processing unit and three receive buffers, all of which are associated with the central processing unit. The three receive buffers are receive buffer 1, receive buffer 2 and receive buffer 3.

[0232] Assuming the parsed target data is split into receive data corresponding to receive buffer 1 and receive data corresponding to receive buffer 3, and each receive data is stored in its corresponding receive buffer, an interrupt signal can be sent to the central processing unit.

[0233] Below, in conjunction with Figure 14 The process of sending an interrupt signal to the target central processing unit corresponding to the receiving cache is illustrated with an example when there are multiple second caches and multiple processors.

[0234] Figure 14 For another flowchart illustrating the transmission of an interrupt signal provided in this application embodiment, please refer to... Figure 14 , Figure 14 It may include a general asynchronous transceiver, a transceiver processor, three central processing units (CPUs) and three receive buffers, namely CPU 1, CPU 2 and CPU 3, and receive buffers namely receive buffer 1, receive buffer 2 and receive buffer 3.

[0235] Assume that CPU 1 is associated with receive buffer 1, CPU 2 is associated with receive buffer 2, and CPU 3 is associated with receive buffer 3. The parsed target data is split into receive data corresponding to receive buffer 1 and receive data corresponding to receive buffer 3.

[0236] After storing each received data into its corresponding receive buffer, an interrupt signal can be sent to CPU 1 and CPU 3 respectively. The interrupt signal is used to indicate service processing.

[0237] The implementation details of each step in this application embodiment can be found in the description of the corresponding steps or operations in the above method embodiments; repeated content will not be repeated.

[0238] The communication method provided in this embodiment determines the number of second buffers (a number greater than or equal to 1) of at least one receive buffer. If the number of second buffers is 1, the parsed target data is stored in the receive buffer. If the number of second buffers is greater than 1, the parsed target data is split into receive data corresponding to multiple receive buffers, and each receive data is stored in its corresponding receive buffer. After storing the parsed target data in the receive buffer, an interrupt signal is sent to the target CPU corresponding to the receive buffer. Alternatively, after storing each receive data in its corresponding receive buffer, an interrupt signal is sent to the target CPU corresponding to the receive buffer. In this way, the transceiver processor reduces the load on the CPU, ensures timely data processing, and allows multiple CPUs to share a single communication interface, improving data transmission efficiency.

[0239] Figure 15 This is a schematic diagram of a communication device provided in an embodiment of this application. Please refer to [link / reference]. Figure 5 The device 1500 includes a processing module 1501 and a transmitting module 1502, wherein,

[0240] The processing module 1501 is used to determine the target data to be processed and to perform a first data processing on the target data, the first data processing including data transmission and data storage;

[0241] The sending module 1502 is used to send an interrupt signal to the target central processing unit corresponding to the target data. The interrupt signal is used to instruct the target central processing unit to perform a second data processing on the target data. The second data processing is to release the storage space occupied by the target data or to perform business processing.

[0242] In one possible implementation, the first data processing is data transmission; the processing module 1501 is specifically used for:

[0243] The target data is determined in at least one transmit buffer and then transmitted.

[0244] Accordingly, the second data processing involves releasing the storage space occupied by the target data.

[0245] In one possible implementation, the processing module 1501 is specifically used for:

[0246] Determine a first buffer quantity for the at least one transmission buffer, wherein the first buffer quantity is an integer greater than or equal to 1;

[0247] If the first buffer quantity is 1, then the target data is determined in the sending buffer and the target data is sent;

[0248] If the number of the first buffers is greater than 1, then an interrupt feedback type is determined, and the target data is determined in at least one transmit buffer according to the interrupt feedback type, and the target data is transmitted. The interrupt feedback type is used to indicate that an interrupt signal is fed back when the data in a single transmit buffer is successfully transmitted, or that an interrupt signal is fed back after the data in all transmit buffers is successfully transmitted.

[0249] In one possible implementation, the interrupt feedback type indicates that an interrupt signal is fed back when data in a single transmit buffer is successfully transmitted; the processing module 1501 is specifically used for:

[0250] Determine the target cache to be polled from among multiple send caches;

[0251] Based on the priority of the target cache, determine the target data volume corresponding to the target cache;

[0252] Based on the target data volume, the target data is determined in the target cache, wherein the data volume of the target data is less than or equal to the target data volume.

[0253] In one possible implementation, the interrupt feedback type indicates that an interrupt signal is fed back after all data in the transmit buffer has been successfully transmitted; the processing module 1501 is specifically used for:

[0254] Determine the priority of the i-th send buffer, determine the i-th data volume based on the priority of the i-th send buffer, determine the i-th data in the i-th send buffer based on the i-th data volume, and send the i-th data;

[0255] Where i takes the values ​​1, 2, ..., N in sequence, and N is the number of the at least one transmission buffer. The target data includes the data determined in each transmission buffer.

[0256] In one possible implementation, the sending module 1502 is specifically used for:

[0257] After the target data is successfully transmitted, an interrupt signal is sent to the target central processing unit corresponding to the target cache; or,

[0258] If it is determined that there is no unsent data in the transmit buffer where the target data is located, an interrupt signal is sent to the target central processing unit corresponding to the transmit buffer.

[0259] In one possible implementation, the first data processing is data storage; the processing module 1501 is specifically used for:

[0260] The target data is parsed to determine at least one receiving buffer corresponding to the target data, and the parsed target data is stored in the at least one receiving buffer.

[0261] Accordingly, the second data processing is business processing.

[0262] In one possible implementation, the processing module 1501 is specifically used for:

[0263] Determine the second cache number of the at least one receive cache, wherein the second cache number is an integer greater than or equal to 1;

[0264] If the second cache size is 1, then the parsed target data is stored in the receiving cache;

[0265] If the number of the second buffer is greater than 1, the parsed target data is split into received data corresponding to at least one receive buffer, and each received data is stored in the corresponding receive buffer.

[0266] In one possible implementation, the sending module 1502 is specifically used for:

[0267] After storing the parsed target data in the receive buffer, an interrupt signal is sent to the target central processing unit corresponding to the receive buffer; or,

[0268] After storing each received data into its corresponding receive buffer, an interrupt signal is sent to the target central processing unit corresponding to the receive buffer.

[0269] Figure 16 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Please refer to... Figure 16 The electronic device 1600 may include: a memory 1601, a processor 1602, and a transceiver 1603.

[0270] Memory 1601 is used to store program instructions;

[0271] The processor 1602 is used to execute the program instructions stored in the memory so that the electronic device 1600 performs any of the communication methods shown above.

[0272] Transceiver 1603 may include a transmitter and / or a receiver. The transmitter may also be referred to as a transmitter, transmitter port, or transmitter interface, and the receiver may also be referred to as a receiver, receiver port, or receiver interface. Exemplarily, memory 1601, processor 1602, and transceiver 1603 are interconnected via bus 1604.

[0273] This application also provides a chip on which a computer program is stored. When the computer program is executed by the chip, it implements the above-mentioned communication method. The corresponding content and effects can be referred to the method embodiment section, and will not be repeated here.

[0274] This application also provides a chip module on which a computer program is stored. When the computer program is executed by the chip module, it implements the above-mentioned communication method. The corresponding content and effects can be referred to the method embodiment section, and will not be repeated here.

[0275] This application also provides a computer program product that can be executed by a processor, and when the computer program product is executed, the above-mentioned communication method can be implemented.

[0276] The communication device, electronic device, computer-readable storage medium, and computer program product of the embodiments of this application can execute the technical solutions shown in the above-described communication method embodiments. Their implementation principles and beneficial effects are similar, and will not be described again here.

[0277] All or part of the steps in the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, it performs the steps of the above-described method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM), flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disc, and any combination thereof.

[0278] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0279] These computer-executable instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0280] These computer-executable instructions may also be loaded onto a computer or other programmable data processing equipment, causing a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0281] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A communication method, characterized in that, Used in transceiver processors, including: The target data to be processed is determined, and the target data is subjected to a first data processing, which includes data transmission or data storage. An interrupt signal is sent to the target central processing unit corresponding to the target data. The interrupt signal is used to instruct the target central processing unit to perform a second data processing on the target data. The second data processing is to release the storage space occupied by the target data or to perform business processing. If the first data processing is data storage; the first data processing of the target data includes: The target data is parsed to determine at least one receiving buffer corresponding to the target data, and the second buffer quantity of the at least one receiving buffer is determined, wherein the second buffer quantity is an integer greater than or equal to 1; If the second cache size is 1, then the parsed target data is stored in the receiving cache; If the number of the second buffer is greater than 1, the parsed target data is split into at least one received data corresponding to a received buffer, and each received data is stored in the corresponding received buffer. Accordingly, the second data processing is business processing; If the first data processing is data transmission; the first data processing of the target data includes: The target data is determined in at least one transmit buffer and then transmitted. Accordingly, the second data processing involves releasing the storage space occupied by the target data.

2. The method according to claim 1, characterized in that, Determining the target data in at least one transmit buffer and transmitting the target data includes: Determine a first buffer quantity for the at least one transmission buffer, wherein the first buffer quantity is an integer greater than or equal to 1; If the first buffer quantity is 1, then the target data is determined in the sending buffer and the target data is sent; If the number of the first buffers is greater than 1, then an interrupt feedback type is determined, and the target data is determined in at least one transmit buffer according to the interrupt feedback type, and the target data is transmitted. The interrupt feedback type is used to indicate that an interrupt signal is fed back when the data in a single transmit buffer is successfully transmitted, or that an interrupt signal is fed back after the data in all transmit buffers is successfully transmitted.

3. The method according to claim 2, characterized in that, The interrupt feedback type indicates that an interrupt signal is fed back when data in a single transmit buffer is successfully transmitted; determining the target data in at least one transmit buffer according to the interrupt feedback type includes: Determine the target cache to be polled from among multiple send caches; Based on the priority of the target cache, determine the target data volume corresponding to the target cache; Based on the target data volume, the target data is determined in the target cache, wherein the data volume of the target data is less than or equal to the target data volume.

4. The method according to claim 2, characterized in that, The interrupt feedback type indicates that an interrupt signal is fed back after all data in the transmit buffer has been successfully transmitted; determining the target data in at least one transmit buffer according to the interrupt feedback type and transmitting the target data includes: Determine the priority of the i-th send buffer, determine the i-th data volume based on the priority of the i-th send buffer, determine the i-th data in the i-th send buffer based on the i-th data volume, and send the i-th data; Where i takes the values ​​1, 2, ..., N in sequence, and N is the number of the at least one transmission buffer. The target data includes the data determined in each transmission buffer.

5. The method according to claim 1, characterized in that, Sending an interrupt signal to the target central processing unit corresponding to the target data includes: After the target data is successfully transmitted, an interrupt signal is sent to the target CPU corresponding to the target cache; or, If it is determined that there is no unsent data in the transmit buffer where the target data is located, an interrupt signal is sent to the target central processing unit corresponding to the transmit buffer.

6. The method according to claim 1, characterized in that, Sending an interrupt signal to the target central processing unit corresponding to the target data includes: After storing the parsed target data in the receive buffer, an interrupt signal is sent to the target central processing unit corresponding to the receive buffer; or, After storing each received data into its corresponding receive buffer, an interrupt signal is sent to at least one target central processing unit corresponding to the receive buffer.

7. A communication device, characterized in that, The device, used in a transceiver processor, includes: A processing module is used to determine the target data to be processed and to perform a first data processing on the target data, wherein the first data processing includes data transmission or data storage; The sending module is used to send an interrupt signal to the target central processing unit corresponding to the target data. The interrupt signal is used to instruct the target central processing unit to perform a second data processing on the target data. The second data processing is to release the storage space occupied by the target data or to perform business processing. If the first data processing is data storage; the processing module is specifically used for: parsing the target data, determining at least one receiving cache corresponding to the target data, determining the second cache quantity of the at least one receiving cache, the second cache quantity being an integer greater than or equal to 1; if the second cache quantity is 1, then storing the parsed target data in the receiving cache; if the second cache quantity is greater than 1, then splitting the parsed target data into receiving data corresponding to at least one receiving cache, storing each receiving data in the corresponding receiving cache, and correspondingly, the second data processing is business processing; If the first data processing involves data transmission, the processing module is specifically used for: The target data is determined in at least one transmit buffer and then transmitted. Accordingly, the second data processing involves releasing the storage space occupied by the target data.

8. An electronic device, characterized in that, include: Memory, processor, and transceiver; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the communication method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the communication method as described in any one of claims 1-6.

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