A method for preparing buried heterojunction edge-emitting laser

Abstract

The present invention discloses a method for preparing a buried heterojunction edge-emitting laser. The present invention etches the buried heterojunction structure by organically combining multiple selective wet etching with multiple dry etching steps. An ICP dry etching process, in which chemical etching with HI as the etching gas and SiCl4 as the protective gas plays a dominant role, is employed. This avoids the introduction of particles with strong bombardment effects, such as Ar and N2, greatly reducing the roughness and surface damage of the etched surface and circumventing the mask side etching effect of the ICP technique. The present invention's solution can achieve precise control of the verticality and horizontal and vertical dimensions of the buried heterojunction structure's side faces, while also achieving smooth, undamaged sidewall and bottom morphologies. AFM roughness testing shows that the etched surface is close to a primary epitaxial surface. Based on this surface morphology, a current-limiting structure is regrown, resulting in good coverage and flatness, thereby improving the performance stability and consistency of the laser.

Description

Technical Field

[0001] The invention relates to a method for preparing a buried heterojunction edge-emitting laser, and belongs to the technical field of semiconductor lasers. Background Art

[0002] The buried heterojunction (BH) structure is one of the commonly used laser structures and has been widely used in edge-emitting lasers including directly modulated lasers (DMLs) and electro-absorption modulated lasers (EMLs) to limit the lateral diffusion of current and improve laser performance.

[0003] The fabrication process for existing buried heterojunction edge-emitting lasers is typically as follows: An epitaxial wafer is first grown using an epitaxial growth process, consisting of a substrate layer, an N-type InP layer, an active layer, a lower P-type InP layer, a P-type InGaAs layer, and an upper P-type InP layer from bottom to top. An etching mask is then formed on the epitaxial wafer surface. The epitaxial wafer is then etched to the bottom surface of the N-type InP layer, forming a buried heterojunction structure. P-InP and N-InP are then grown on both sides of the buried heterojunction structure to form a current confinement structure. After removing the etching mask, highly doped P-InP and InGaAs contact layers are grown on the wafer surface. Specifically, a grating structure is embedded in the lower P-type InP layer of the DML and the lower P-type InP layer in the LD structure region of the EML, while no grating structure is present in the lower P-type InP layer in the EAM structure region of the EML.

[0004] Buried heterojunction structures are typically formed by etching. To ensure the overall product structure and meet performance and stability requirements, the etching process has stringent requirements, including vertical and lateral dimensions, sidewall smoothness, bottom smoothness, and damage-free etch. Existing buried heterojunction structures are etched using dry etching with Ar / N2 gases and wet etching with solutions containing Br2 or H2SO4 / H2O2. Dry etching with Ar / N2 gases results in a rough etched surface and causes surface damage. Wet etching with solutions containing Br2 or H2SO4 / H2O2 makes it difficult to control the selectivity and lateral etch rate on each side of the structure, resulting in unsatisfactory etched morphology. Deviations in feature size control, roughness, and damage can increase the threshold current density, severely impacting modal quality. Therefore, improvements are needed to achieve smoother sidewall and bottom morphologies while maintaining verticality and lateral and vertical dimensions, providing a good foundation for subsequent regrowth. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the shortcomings of the existing technology and provide a method for preparing a buried heterojunction edge-emitting laser, which can obtain relatively smooth sidewall and bottom morphologies while ensuring verticality and control of lateral and longitudinal dimensions, providing a good foundation for subsequent regrowth.

[0006] The present invention specifically adopts the following technical solutions to solve the above technical problems:

[0007] A method for preparing a buried heterojunction edge-emitting laser comprises the steps of etching an epitaxial wafer to form a buried heterojunction structure, and growing a current confinement structure on both sides of the buried heterojunction structure; the epitaxial wafer comprises, from bottom to top, a substrate layer, an N-type InP layer, an active layer, a lower P-type InP layer, a P-type InGaAs layer, an upper P-type InP layer, and an etching mask; the epitaxial wafer is etched to form the buried heterojunction structure using the following process:

[0008] S1. First dry etching: Use ICP etching process with HI as etching gas and SiCl4 as protective gas to etch the epitaxial wafer to the lower P-type InP layer, and ensure that the active layer is not exposed;

[0009] S2. First wet etching: using a selective etching solution to wet-etch only the P-type InGaAs layer, causing the P-type InGaAs layer to shrink laterally;

[0010] S3, second wet etching: using a selective etching solution to wet-etch only the lower P-type InP layer and the upper P-type InP layer, so that the lower P-type InP layer and the upper P-type InP layer are laterally retracted to overlap with the edge of the P-type InGaAs layer;

[0011] S4, second dry etching: using HI as etching gas and SiCl4 as protective gas to etch away the exposed portion of the active layer, so that the active layer is laterally retracted to overlap with the edges of the lower P-type InP layer, the P-type InGaAs layer, and the upper P-type InP layer;

[0012] S5. Third wet etching: Use a selective etching solution to wet-etch only the N-type InP layer, so that the N-type InP layer shrinks laterally to overlap with the edges of the active layer, the lower P-type InP layer, the P-type InGaAs layer, and the upper P-type InP layer.

[0013] Preferably, the flow ratio of HI to SiCl 4 in the first dry etching is 8:3.

[0014] Further preferably, the ratio of RF power to Bias power in the first dry etching is 5:1.

[0015] Preferably, the flow ratio of HI to SiCl 4 in the second dry etching is 50:3.

[0016] Further preferably, the ratio of RF power to Bias power in the second dry etching is 20:1.

[0017] Preferably, the selective etching solution in the first wet etching is a H2SO4 / H2O2 diluted solution.

[0018] Further preferably, the volume ratio of the selective etching solution is H2SO4:H2O2:H2O=1:1:5.

[0019] Preferably, the selective etching solution in the second wet etching and the third wet etching is a HCL / H3PO4 mixed solution.

[0020] Further preferably, the volume ratio of the HCl solution to the H3PO4 solution in the mixed solution is 1:4.

[0021] Based on the same inventive concept, the following technical solutions can also be obtained:

[0022] A buried heterojunction edge-emitting laser is prepared using the method described in any of the above technical solutions.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] The present invention etches the buried heterojunction structure by organically combining multiple selective wet etching and multiple dry etching, and adopts an ICP dry etching process in which chemical etching plays a dominant role, using HI as the etching gas and SiCl4 as the protective gas. This avoids the introduction of particles with strong bombardment effects such as Ar and N2, greatly reduces the roughness and surface damage of the etched surface, and circumvents the mask side etching effect of the ICP technology. The scheme of the present invention can achieve precise control of the verticality and horizontal and vertical dimensions of the buried heterojunction structure, and at the same time obtain a flat, smooth and damage-free sidewall and bottom morphology. AFM test roughness shows that the etched surface is close to the primary epitaxial surface. Based on this surface morphology, the current confinement structure is regrown, with good coverage and flatness, thereby improving the performance stability and consistency of the laser. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 6 The figure is a schematic diagram of the preparation process of a specific embodiment of the present invention. DETAILED DESCRIPTION

[0026] In response to the problem that the existing buried heterojunction structure etching process is difficult to meet the requirements, the solution of the present invention is to adopt an organic combination of multiple selective wet etching and multiple dry etching, and adopt an ICP dry etching process in which chemical etching plays a dominant role using HI as the etching gas and SiCl4 as the protective gas, instead of using particles with strong bombardment such as Ar and N2; while achieving precise control of the verticality and lateral and longitudinal dimensions of the buried heterojunction structure, the roughness and surface damage of the etched surface are reduced, thereby avoiding the mask side etching effect of the ICP technology.

[0027] ICP (inductively coupled plasma) is a commonly used etching technique for III-V semiconductor materials. This isotropic technique, and due to the integrated optical etching monitoring system in current ICP equipment, ICP offers superior control over etching precision and stability compared to wet etching processes. ICP technology utilizes bias voltages between upper and lower electrodes and radio frequency to generate a high-density plasma, which then performs longitudinal ion etching under the bias voltage. Because the physical etching action of most gas plasmas is stronger than chemical etching, ICP etching results in rougher surfaces compared to wet etching processes that rely solely on electrochemical reactions, and damage from the bombardment effect is unavoidable. To address this issue, the present invention utilizes HI (hydrogen iodide) as the etching gas, taking into account the vapor pressures of different etching products of III-V materials. This method utilizes a predominantly chemical etching gas, HI, to achieve ICP etching, significantly reducing surface roughness and damage. Furthermore, the use of a SiCl4 shielding gas with a higher vapor pressure provides sidewall protection during the etching process, thus mitigating the mask undercutting effect of ICP etching. While achieving better etching size control, smoother sidewall and bottom morphologies are obtained, and since particles with strong bombardment effects such as Ar / N2 are not introduced, minimum etching damage is guaranteed.

[0028] The technical solutions proposed in the present invention are as follows:

[0029] A method for preparing a buried heterojunction edge-emitting laser comprises the steps of etching an epitaxial wafer to form a buried heterojunction structure, and growing a current confinement structure on both sides of the buried heterojunction structure; the epitaxial wafer comprises, from bottom to top, a substrate layer, an N-type InP layer, an active layer, a lower P-type InP layer, a P-type InGaAs layer, an upper P-type InP layer, and an etching mask; the epitaxial wafer is etched to form the buried heterojunction structure using the following process:

[0030] S1. First dry etching: Use ICP etching process with HI as etching gas and SiCl4 as protective gas to etch the epitaxial wafer to the lower P-type InP layer, and ensure that the active layer is not exposed;

[0031] S2. First wet etching: using a selective etching solution to wet-etch only the P-type InGaAs layer, causing the P-type InGaAs layer to shrink laterally;

[0032] S3, second wet etching: using a selective etching solution to wet-etch only the lower P-type InP layer and the upper P-type InP layer, so that the lower P-type InP layer and the upper P-type InP layer are laterally retracted to overlap with the edge of the P-type InGaAs layer;

[0033] S4, second dry etching: using HI as etching gas and SiCl4 as protective gas to etch away the exposed portion of the active layer, so that the active layer is laterally retracted to overlap with the edges of the lower P-type InP layer, the P-type InGaAs layer, and the upper P-type InP layer;

[0034] S5. Third wet etching: Use a selective etching solution to wet-etch only the N-type InP layer, so that the N-type InP layer shrinks laterally to overlap with the edges of the active layer, the lower P-type InP layer, the P-type InGaAs layer, and the upper P-type InP layer.

[0035] Preferably, the flow ratio of HI to SiCl 4 in the first dry etching is 8:3.

[0036] Further preferably, the ratio of RF power to Bias power in the first dry etching is 5:1.

[0037] Preferably, the flow ratio of HI to SiCl 4 in the second dry etching is 50:3.

[0038] Further preferably, the ratio of RF power to Bias power in the second dry etching is 20:1.

[0039] Preferably, the selective etching solution in the first wet etching is a H2SO4 / H2O2 diluted solution.

[0040] Further preferably, the volume ratio of the selective etching solution is H2SO4:H2O2:H2O=1:1:5.

[0041] Preferably, the selective etching solution in the second wet etching and the third wet etching is a HCL / H3PO4 mixed solution.

[0042] Further preferably, the volume ratio of the HCl solution to the H3PO4 solution in the mixed solution is 1:4.

[0043] To facilitate public understanding, the technical solution of the present invention is described in detail below through an embodiment with reference to the accompanying drawings:

[0044] In this embodiment, a 3-inch epitaxial wafer is used, such as Figure 1 As shown, the epitaxial wafer includes, from bottom to top, a substrate layer, an N-type InP layer, an active layer (typically including a quantum well and an upper and lower confinement layer sandwiching the quantum well, in this embodiment, an aluminum-doped quantum well AL-MQW / SCH with a separate confinement heterojunction structure), a lower P-type InP layer, a P-type InGaAs layer, an upper P-type InP layer, and an etch mask. The thickness of the epitaxial wafer below the etch mask is 3.5 μm. The etch mask can be manufactured using a conventional yellow light process. The specific manufacturing process of the etch mask in this embodiment is as follows:

[0045] (1) A 200 nm SiO2 film was deposited on the epitaxial wafer surface using the PECVE process, using a gas of 5% SiH4 / N2O = 250 sccm / 450 sccm and a temperature of 350°C;

[0046] (2) Surface modification was performed using an HMDS oven, and positive photoresist AZ1518 was spin-coated using a coater at a speed of 2500 rpm. The pre-bake temperature before exposure was 95 °C for 1 min.

[0047] (3) UV exposure was performed using a SUSS MA6 lithography machine to transfer the buried heterojunction structure pattern to the epitaxial wafer surface. The exposure power was 15 mW, the exposure time was 11.5 s, and the post-exposure baking temperature was 120 °C for 1 min.

[0048] (4) Developed with AZ MIR60 at room temperature for 1 min, rinsed with deionized water, and baked at 115 °C for 1 min;

[0049] (5) O2 plasma cleaning machine, power 250W, remove the tail morphology of the photoresist, cleaning time 1min;

[0050] (6) Etch the SiO2 film using RIE dry etching equipment, using CF4 / CHF3 gas = 15sccm / 30sccm, power 100W;

[0051] (7) Use O2 / Ar plasma and NMP degumming solution to complete the post-etching degumming, and then obtain the SiO2 etching mask required subsequently.

[0052] Use the following process Figure 1 The epiwafer shown is etched to form a buried heterojunction structure:

[0053] S1. First dry etching: Use ICP etching process with HI as etching gas and SiCl4 as protective gas to etch the epitaxial wafer to the lower P-type InP layer, and ensure that the active layer is not exposed;

[0054] This embodiment uses ULVAC ICP etching equipment, etching gas HI / SiCl4=40sccm / 15sccm, RF power 300W, Bias power 60W; this ratio of etching gas can achieve better sidewall protection, and the optical endpoint monitoring system of the ICP etching equipment is used in conjunction with the etching process to control the etching depth and achieve the first step of vertical etching; the etching stage temperature is 220℃, and the etching products can leave the etching surface by thermal evaporation, without the need to use bombarding gases such as Ar and N2. The etching time of this step is 1.5min and the etching depth is 2.2um; the completed epitaxial wafer is as follows Figure 2 shown.

[0055] S2. First wet etching: using a selective etching solution to wet-etch only the P-type InGaAs layer, causing the P-type InGaAs layer to shrink laterally;

[0056] In this embodiment, H2SO4 / H2O2 dilution solution is used for the first wet etching. This dilution solution is a selective etching solution and does not corrode the InP layer structure, but only corrodes the P-InGaAs layer. Since the active layer of the key structure is not exposed, the key structure will not be affected by the wet etching solution. By controlling the etching time, the side etching size of the P-InGaAs layer is generally controlled to be between 0.5 and 1 μm. In this embodiment, H2SO4:H2O2:H2O=50ml:50ml:250ml, the solution temperature is 20-23°C, the etching time is 3 minutes, and the side etching depth of the P-InGaAs is greater than 0.5 μm. The epitaxial wafer after completion is as shown in FIG. Figure 3 shown.

[0057] S3, second wet etching: using a selective etching solution to wet-etch only the lower P-type InP layer and the upper P-type InP layer, so that the lower P-type InP layer and the upper P-type InP layer are laterally retracted to overlap with the edge of the P-type InGaAs layer;

[0058] In this embodiment, a HCL / H3PO4 mixed solution is used for the second wet etching. This mixed solution is a selective etching solution that only etches InP materials. Therefore, the key structure is not affected by this wet etching solution even in the exposed state. Because it has extremely stable crystal orientation selectivity, the lateral shrinkage size of the lower P-type InP layer and the upper P-type InP layer obtained by this etching is determined by the lateral size of the first wet etching, and the vertical size is determined by the thickness of the epitaxial layer of the epitaxial wafer. In this embodiment, HCL:H3PO4=100ml:400ml, the solution temperature is 20-23℃, and the etching time is 1min. The completed epitaxial wafer is as follows Figure 4 shown.

[0059] S4, second dry etching: using HI as etching gas and SiCl4 as protective gas to etch away the exposed portion of the active layer, so that the active layer is laterally retracted to overlap with the edges of the lower P-type InP layer, the P-type InGaAs layer, and the upper P-type InP layer;

[0060] Similar to the first dry etching, ULVAC ICP etching equipment is also used, the etching gas is HI, and the protective gas is SiCl4; however, in the second dry etching of this embodiment, HI / SiCl4=50sccm / 3sccm, RF power 400W, Bias power 20W, this ratio of etching gas for side wall protection is weaker than the first step, this step of etching tends to chemical corrosion, and the Bias power is low, and the RF radio frequency power is high, both of which are to meet the dominant role of chemical etching; the etching stage temperature is 220°C, and the etching products can leave the etching surface by thermal evaporation, without the use of bombarding gases such as Ar and N2. The etching time of this step is 30s and the etching depth is 0.35um; this step is used in conjunction with the optical endpoint monitoring system to achieve precise control of the etching depth, and the lateral etching depth control is achieved by controlling the vertical etching depth (the lateral and vertical etching ratio is directly determined by the etching program and the etching material); the etching in this step should ensure that the active layer is completely etched and the N-INP layer is completely exposed; the completed epitaxial wafer is as follows Figure 5 shown.

[0061] S5, third wet etching: using a selective etching solution to wet-etch only the N-type InP layer, so that the N-type InP layer is laterally retracted to overlap with the edges of the active layer, the lower P-type InP layer, the P-type InGaAs layer, and the upper P-type InP layer;

[0062] In this embodiment, a HCL / H3PO4 mixed solution is used for the third wet etching. This mixed solution is a selective etching solution that only etches InP materials. Therefore, even in the exposed state, the key structure is not affected by this wet etching solution. Due to its extremely stable crystal orientation selectivity, the exposed INP will not be further etched. The etching direction only extends in the direction of the target depth. The etching can be stopped when the target depth is reached. In this embodiment, HCL:H3PO4=100ml:400ml, the solution temperature is 20-23℃, and the etching time is 1min. The completed epitaxial wafer is as follows. Figure 6 shown.

[0063] exist Figure 6 Based on the buried heterojunction structure shown, P-InP and N-InP can be grown on both sides of the buried heterojunction structure to form a current limiting structure; since the subsequent epitaxial growth is selective growth, the SiO2 etching mask does not need to be removed.

Claims

1. A method for preparing a buried heterojunction edge-emitting laser, comprising etching an epitaxial wafer to form a buried heterojunction structure, and growing a current confinement structure on both sides of the buried heterojunction structure; the epitaxial wafer comprises, from bottom to top, a substrate layer, an N-type InP layer, an active layer, a lower P-type InP layer, a P-type InGaAs layer, an upper P-type InP layer, and an etching mask; characterized in that: The epitaxial wafer is etched to form the buried heterojunction structure using the following process: S1. First dry etching: Use ICP etching process with HI as etching gas and SiCl4 as protective gas to etch the epitaxial wafer to the lower P-type InP layer, and ensure that the active layer is not exposed; S2. First wet etching: using a selective etching solution to wet-etch only the P-type InGaAs layer, causing the P-type InGaAs layer to shrink laterally; S3, second wet etching: using a selective etching solution to wet-etch only the lower P-type InP layer and the upper P-type InP layer, so that the lower P-type InP layer and the upper P-type InP layer are laterally retracted to overlap with the edge of the P-type InGaAs layer; S4, second dry etching: using HI as etching gas and SiCl4 as protective gas to etch away the exposed portion of the active layer, so that the active layer is laterally retracted to overlap with the edges of the lower P-type InP layer, the P-type InGaAs layer, and the upper P-type InP layer; S5. Third wet etching: Use a selective etching solution to wet-etch only the N-type InP layer, so that the N-type InP layer shrinks laterally to overlap with the edges of the active layer, the lower P-type InP layer, the P-type InGaAs layer, and the upper P-type InP layer.

2. The method for preparing a buried heterojunction edge-emitting laser according to claim 1, wherein: The flow ratio of HI to SiCl4 in the first dry etching is 8:

3.

3. The method for preparing a buried heterojunction edge-emitting laser according to claim 2, wherein: The ratio of RF power to Bias power in the first dry etching is 5:

1.

4. The method for preparing a buried heterojunction edge-emitting laser according to claim 1, wherein: The flow ratio of HI to SiCl4 in the second dry etching is 50:

3.

5. The method for preparing a buried heterojunction edge-emitting laser according to claim 4, wherein: The ratio of RF power to Bias power in the second dry etching is 20:

1.

6. The method for preparing a buried heterojunction edge-emitting laser according to claim 1, wherein: The selective etching solution in the first wet etching is a H2SO4 / H2O2 dilution solution.

7. The method for preparing a buried heterojunction edge-emitting laser according to claim 6, wherein: The volume ratio of the selective etching solution is H2SO4:H2O2:H2O=1:1:

5.

8. The method for preparing a buried heterojunction edge-emitting laser according to claim 1, wherein: The selective etching solution in the second wet etching and the third wet etching is a HCL / H3PO4 mixed solution.

9. The method for preparing a buried heterojunction edge-emitting laser according to claim 8, wherein: The volume ratio of the HCL solution to the H3PO4 solution in the mixed solution is 1:

4.

10. A buried heterojunction edge-emitting laser, characterized in that: The method is used to prepare the product according to any one of claims 1 to 9.

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