Soc chip testing method, device, apparatus, and storage medium

Abstract

The application discloses a SOC chip test method, device, equipment and storage medium, and the method comprises the following steps: a to-be-tested SOC chip sends a boot success instruction to an ATE tester, the ATE tester sends a test command to the to-be-tested SOC chip; when a first CPU core receives the test command, target resources are allocated to each second CPU core; the first CPU core starts each second CPU core, controls each second CPU core to perform a test based on the target resources, and obtains a sub-test result; the first CPU core detects test state information of each second CPU core, acquires each sub-test result, and sends the test state information and the test result to the ATE tester; and the ATE tester generates a target chip test result based on the sub-test result. The application can realize that the to-be-tested SOC chip is in multi-core simultaneous operation, different test items are tested in parallel at the same time, and the chip test efficiency is improved compared with the single-core test scheme.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of chip testing technology, and in particular to a SOC chip testing method, apparatus, device, and storage medium. Background Technology

[0002] After semiconductor chips are manufactured, they need to undergo final testing (FT) to screen out defect-free chips. In FT, the SOC chip under test needs to receive commands from an automated test equipment (ATE) and execute the corresponding module test cases. After execution, the test results are returned to the ATE. Currently, in the module functional testing phase, most SOC chips rely on their own CPU to execute test programs, using only a single CPU core. That is, after receiving commands from the ATE for all modules, the SOC chip uses a single CPU core to perform serial tests on different commands. Furthermore, a single CPU core can only test one module at a time. As the number of SOC chips to be tested increases and the testing process becomes more complex, more testing time is required. Summary of the Invention

[0003] This application provides a SOC chip testing method, apparatus, device, and storage medium, which can improve the testing efficiency of SOC chips and thus reduce testing time costs.

[0004] In a first aspect, embodiments of this application provide a SOC chip testing method applied to an SOC chip testing device. The SOC chip testing device includes an ATE tester, a test motherboard, and an FT test board. The test motherboard is communicatively connected to the ATE tester and the FT test board, respectively. The FT test board is electrically connected to the SOC chip under test. The SOC chip under test includes at least a first CPU core and multiple second CPU cores. The first CPU core is communicatively connected to each of the second CPU cores. The method includes:

[0005] After the SOC chip under test is powered on, the SOC chip under test sends a boot success command to the ATE test machine through the FT test board and the test motherboard. When the ATE test machine detects the boot success command, the ATE test machine sends test commands to the SOC chip under test through the test motherboard and the FT test board.

[0006] When the first CPU core in the SOC chip under test receives the test command, the first CPU core allocates corresponding target resources to each of the second CPU cores. Each of the target resources is different and independent of each other. The target resources are chip test resources used for chip testing.

[0007] The first CPU core starts each of the second CPU cores and controls each of the second CPU cores to perform chip testing based on the corresponding target resources, and obtains sub-test results;

[0008] The first CPU core detects the test status information of each of the second CPU cores, obtains each of the sub-test results, and sends all the test status information and all the test results to the ATE test machine through the FT test board and the test motherboard.

[0009] The ATE test machine generates target chip test results based on the results of each of the sub-tests.

[0010] In some embodiments, the first CPU core allocates corresponding target resources to each of the second CPU cores, including:

[0011] The first CPU core initializes the chip test resources of the SOC chip under test;

[0012] The first CPU core divides the chip test resources based on the core capacity of each of the second CPU cores to obtain multiple target resources;

[0013] The first CPU core allocates each of the target resources to the corresponding second CPU cores;

[0014] The first CPU core uses the lock_mutex function to lock the target resources in each of the second CPU cores.

[0015] The first CPU core starts each of the second CPU cores and controls each of the second CPU cores to perform chip testing based on the corresponding target resources and the test commands, obtaining sub-test results, including:

[0016] After the first CPU core starts each of the second CPU cores, each of the second CPU cores determines the locking status of the corresponding target resource;

[0017] When the locking state indicates that the target resource is not locked, the first CPU core controls the second CPU core corresponding to the unlocked target resource to perform chip testing based on the corresponding target resource and the test command, and obtain the sub-test result.

[0018] In some embodiments, before each of the second CPU cores determines the locking state of the corresponding target resource, the method includes:

[0019] Each of the second CPU cores receives the test command;

[0020] The target CPU core unlocks the corresponding target resources based on the test command, wherein the target CPU core belongs to the second CPU core.

[0021] In some embodiments, before the SOC chip under test sends a boot success command to the ATE test machine via the FT test board and the test motherboard, the method further includes:

[0022] The ATE tester is powered on, thereby starting the SOC chip under test;

[0023] The ATE tester performs power consumption performance tests on the SOC chip under test.

[0024] In some embodiments, the first CPU core boots each of the second CPU cores, including:

[0025] The first CPU core sends a power-on reset signal to each of the second CPU cores;

[0026] The first CPU core sends a core reset signal to each of the second CPU cores;

[0027] The first CPU core sets the power switch registers of all the second CPU cores so that all the second CPU cores are in the power-on state;

[0028] The first CPU core performs a power gating state clearing operation on all second CPU cores;

[0029] The first CPU core controls each of the second CPU cores to release the power-on reset signal;

[0030] The first CPU core controls each of the second CPU cores to release the core reset signal;

[0031] The first CPU core starts each of the second CPU cores.

[0032] Secondly, embodiments of this application provide a SOC chip testing device for performing the SOC chip testing method as described in any one of claims 1 to 6. The SOC chip testing device includes an ATE tester, a test motherboard, and an FT test board. The test motherboard is communicatively connected to the ATE tester and the FT test board, respectively. The FT test board is electrically connected to the SOC chip under test. The SOC chip under test includes at least a first CPU core and a plurality of second CPU cores. The first CPU core is communicatively connected to each of the second CPU cores.

[0033] Thirdly, embodiments of this application provide a control device, including at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, which, when executed by the at least one control processor, enable the at least one control processor to perform the SOC chip testing method as described in the first aspect.

[0034] Fourthly, embodiments of this application also provide an electronic device, including the control device of the third aspect.

[0035] Fifthly, embodiments of this application also provide a computer-readable storage medium storing computer-executable instructions for performing the SOC chip testing method as described in the first aspect.

[0036] This application provides a SOC chip testing method, apparatus, device, and storage medium. The method includes: after the SOC chip under test is powered on, the SOC chip under test sends a boot success command to the ATE test machine through the FT test board and the test motherboard; when the ATE test machine detects the boot success command, the ATE test machine sends a test command to the SOC chip under test through the test motherboard and the FT test board; when the first CPU core in the SOC chip under test receives the test command, the first CPU core allocates corresponding target resources to each of the second CPU cores, and each of the target resources is different and independent of each other, wherein the target resources are chip test resources used for chip testing; the first CPU core starts each of the second CPU cores and controls each of the second CPU cores to perform chip testing based on the corresponding target resources to obtain sub-test results; the first CPU core detects the test status information of each of the second CPU cores, obtains each of the sub-test results, and sends all the test status information and all the test results to the ATE test machine through the FT test board and the test motherboard; the ATE test machine generates target chip test results based on each of the sub-test results. According to the solution provided in the embodiments of this application, the SOC chip under test can be started to achieve multi-core simultaneous operation and test different test items in parallel at the same time, thereby improving the testing efficiency of the SOC chip and reducing the testing time cost. Attached Figure Description

[0037] Figure 1 This is a flowchart of the steps of a SOC chip testing method provided in one embodiment of this application;

[0038] Figure 2This is a flowchart illustrating the steps of a first CPU core allocating target resources to each of the second CPU cores, as provided in another embodiment of this application.

[0039] Figure 3 This is a flowchart of the steps for obtaining sub-test results provided in another embodiment of this application;

[0040] Figure 4 This is a flowchart of the steps for obtaining sub-test results provided in another embodiment of this application;

[0041] Figure 5 This is a flowchart of the steps for testing the power consumption performance of a SOC chip under test, provided in another embodiment of this application;

[0042] Figure 6 This is a flowchart of the steps for a first CPU core to start each of the second CPU cores, provided in another embodiment of this application;

[0043] Figure 7 This is a structural diagram of a control device provided in another embodiment of this application;

[0044] Figure 8 This is a schematic diagram of a module of a SOC chip testing device provided in another embodiment of this application. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0046] It is understandable that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, or the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0047] After semiconductor chips are manufactured, they need to undergo final testing (FT) to screen out defect-free chips. In FT, the SOC chip under test needs to receive commands from an automated test equipment (ATE) and execute the corresponding module test cases. After execution, the test results are returned to the ATE. Currently, in the module functional testing phase, most SOC chips rely on their own CPU to execute test programs, using only a single CPU core. That is, after receiving commands from the ATE for all modules, the SOC chip uses a single CPU core to perform serial tests on different commands. Furthermore, a single CPU core can only test one module at a time. As the number of SOC chips to be tested increases and the testing process becomes more complex, more testing time is required.

[0048] To address the aforementioned problems, this application provides a SOC chip testing method, apparatus, device, and storage medium. The method includes: after the SOC chip under test is powered on, the SOC chip under test sends a boot success command to the ATE test machine through the FT test board and the test motherboard; when the ATE test machine detects the boot success command, the ATE test machine sends a test command to the SOC chip under test through the test motherboard and the FT test board; when the first CPU core in the SOC chip under test receives the test command, the first CPU core allocates corresponding target resources to each of the second CPU cores. The target resources are all different and independent of each other, wherein the target resources are chip testing resources used for chip testing; the first CPU core starts each of the second CPU cores and controls each of the second CPU cores to perform chip testing based on the corresponding target resources, and obtains sub-test results; the first CPU core detects the test status information of each of the second CPU cores, obtains each of the sub-test results, and sends all the test status information and all the test results to the ATE test machine through the FT test board and the test motherboard; the ATE test machine generates target chip test results based on each of the sub-test results. According to the solution provided by the embodiments of this application, it is possible to realize the simultaneous operation of multiple cores of the SOC chip under test, and to test different test items in parallel at the same time, thereby improving the testing efficiency of the SOC chip and reducing the testing time cost.

[0049] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0050] refer to Figure 1 , Figure 1This is a flowchart illustrating the steps of a SOC chip testing method according to an embodiment of this application. This application provides a SOC chip testing method applied to an SOC chip testing device. The SOC chip testing device includes an ATE tester, a test motherboard, and an FT test board. The test motherboard is communicatively connected to both the ATE tester and the FT test board. The FT test board is electrically connected to the SOC chip under test. The SOC chip under test includes at least a first CPU core and multiple second CPU cores. The first CPU core is communicatively connected to each of the second CPU cores. The method includes, but is not limited to, the following steps:

[0051] Step S110: After the SOC chip under test is powered on, the SOC chip under test sends a boot success command to the ATE tester through the FT test board and the test motherboard. When the ATE tester detects the boot success command, the ATE tester sends the test command to the SOC chip under test through the test motherboard and the FT test board.

[0052] Step S120: When the first CPU core in the SOC chip under test receives the test command, the first CPU core allocates corresponding target resources to each second CPU core. Each target resource is different from and independent of the others. The target resources are chip test resources used for chip testing.

[0053] In step S130, the first CPU core starts each of the second CPU cores and controls each of the second CPU cores to perform chip testing based on the corresponding target resources to obtain sub-test results.

[0054] In step S140, the first CPU core detects the test status information of each second CPU core, obtains the results of each sub-test, and sends all the test status information and all the test results to the ATE test machine through the FT test board and the test motherboard.

[0055] In step S150, the ATE tester generates the target chip test results based on the results of each sub-test.

[0056] It should be noted that the SOC chip testing device in this application embodiment is as follows: Figure 8As shown, the SOC chip testing device includes an ATE tester 810, a test motherboard 820, and an FT test board 830. The test motherboard 820 is communicatively connected to both the ATE tester 810 and the FT test board 830. The FT test board 830 is electrically connected to the SOC chip under test 840. The ATE tester 810 is directly connected to the FT test board 830, which is used to connect the SOC chip under test, through the test motherboard 820, and can provide power and control signals to the SOC chip under test 840. The SOC chip under test 840 includes at least a first CPU core CPU0 and multiple second CPU cores (CPU1, CPU2...CPUN). The first CPU core is communicatively connected to each of the second CPU cores. The specific number of second CPU cores is determined by the specific attributes of the SOC chip under test 840, and this embodiment does not impose any restrictions. The CPU0 core acts as a communication and control information relay station in the SOC chip 840 after power-on. When the ATE tester 810 sends test commands to the SOC chip 840, the first CPU core CPU0 of the SOC chip 840 starts each of the second CPU cores according to the process. Each of the second CPU cores works in parallel and independently, and begins to execute the corresponding module test cases. Since the second CPU cores are tested in parallel, the module test time is not particularly sensitive. Test patterns with high test pressure and full coverage can be selected to ensure test quality. After the test of each second CPU core is completed, the first CPU core CPU0 feeds back the corresponding test results to the ATE tester 810. The ATE determines whether the chip is good or not based on the test results, and thus classifies the chip.

[0057] Understandably, based on such Figure 8The SOC chip testing apparatus shown in this application and the SOC chip testing method specifically include: after the SOC chip under test 840 is powered on, the SOC chip under test 840 sends a boot success command to the ATE test machine 810 through the FT test board 830 and the test motherboard 820. When the ATE test machine 810 detects the boot success command, the ATE test machine 810 sends a test command to the SOC chip under test 840 through the test motherboard 820 and the FT test board 830; when the first CPU core in the SOC chip under test 840 receives the test command, the first CPU core parses the test command and allocates corresponding target resources to each second CPU core. Each target resource is different and independent of the others. The target resources are chip test resources used for chip testing; the first CPU core... The U kernel starts each of the second CPU cores and controls each of the second CPU cores to perform chip testing based on the corresponding target resources, obtaining sub-test results. Each second CPU core works independently and executes different test items in parallel. The first CPU core detects the test status information of each second CPU core, obtains each sub-test result, and sends all test status information and all test results to the ATE test machine 810 through the FT test board 830 and the test motherboard 820. The ATE test machine 810 generates the target chip test results based on each sub-test result, utilizes the CPU computing power of the SOC core under test to accelerate the execution speed of test cases, and realizes that the multiple cores of the SOC chip under test 840 work simultaneously, testing different test items in parallel at the same time, thereby improving the testing efficiency of the SOC chip and reducing the testing time cost.

[0058] It should be noted that, in this embodiment of the application, the first CPU core CPU0 is responsible for receiving test commands, task scheduling, and resource management signals sent by the ATE test machine, rationally allocating test tasks to the second CPU cores to ensure full utilization of each second CPU core, and managing the shared resources of each second CPU core to avoid resource conflicts and competition that could affect the chip testing process. The first CPU core CPU0 is also responsible for enabling the second CPU cores, controlling their test processes, forwarding sub-test results, and storing these results in variables. As a communication and control information relay station, the first CPU core CPU0 is specifically responsible for processing communication information, efficiently handling test commands and test results. Specifically, the first CPU core CPU0 detects the sub-test result flags of each second CPU core and feeds the sub-test results back to the ATE test machine.

[0059] It should be noted that the ATE tester in this embodiment is responsible for sending test commands and receiving sub-test results, controlling the entire mass production test system, generating target chip test results based on the sub-test results, and classifying the SOC chips to be tested.

[0060] It should be noted that the embodiments of this application do not limit the specific number of second CPU cores. For example, the second CPU cores in this embodiment may include three second CPU cores: CPU1, CPU2, and CPU3. CPU1 is used to receive test information sent by CPU0 and is responsible for testing the analog module circuit functions of the SOC chip under test, such as LDO calibration, audio module function testing, etc. It independently executes the corresponding test cases and returns the corresponding sub-test results to CPU0, which then feeds them back to the ATE test machine. CPU2 is responsible for testing the algorithm modules of the SOC chip under test and loading related test data, such as GPU, VE, DE, ISP, etc. It executes the algorithm test pattern and returns the corresponding sub-test results to CPU0, which then feeds them back to the ATE test machine. CPU3 is responsible for testing the interface modules of the SOC chip under test, such as UART, CAN, CSI, HDMI, LVDS, etc. It returns the corresponding sub-test results to CPU0, which then feeds them back to the ATE test machine.

[0061] Additionally, refer to Figure 2 In some embodiments, Figure 1 Step S120 includes, but is not limited to, the following steps:

[0062] Step S210: The first CPU core initializes the chip test resources of the SOC chip under test;

[0063] Step S220: The first CPU core divides the chip test resources based on the core capacity of each second CPU core to obtain multiple target resources;

[0064] In step S230, the first CPU core allocates each target resource to the corresponding second CPU core;

[0065] In step S240, the first CPU core locks the target resources in each of the second CPU cores based on the lock_mutex function.

[0066] Understandably, when a multi-core CPU operates in a SoC chip under test (DUT), it becomes a multi-tasking system. Since different tasks compete for shared resources, the system needs to provide synchronization and mutual exclusion mechanisms. When the first CPU core (CPU0) receives the test command from the ATE (Automatic Test Equipment), it initializes the chip test resources of the DUT. Based on the core capacity of each second CPU core, it divides the chip test resources into multiple target resources and allocates each target resource to its corresponding second CPU core. This includes allocating DMA channels, configuring interrupt responses, and time-sharing resource reuse for each second CPU core, allowing different second CPU cores to test different functional modules of the DUT. Then, the first CPU core uses the `lock_mutex` function to lock the target resources in each second CPU core, successfully locking the resources used by each second CPU core and blocking other cores from accessing the resources in use. This resolves the instability caused by resource conflicts resulting from simultaneous multi-core operation and ensures stable operation of each second CPU core.

[0067] Additionally, refer to Figure 3 In some embodiments, Figure 1 Step S130 includes, but is not limited to, the following steps:

[0068] Step S310: After the first CPU core starts each of the second CPU cores, each of the second CPU cores determines the locking status of the corresponding target resource.

[0069] Step S320: When the locking state indicates that the target resource is not locked, the first CPU core controls the second CPU core corresponding to the unlocked target resource to perform chip testing based on the corresponding target resource and test command, and obtains the sub-test result.

[0070] Understandably, since different second CPU cores are responsible for different test items, and the test order of different test items is determined by the test commands sent by the ATE test machine, whether the target resources corresponding to each second CPU core are locked is also determined by the test commands. When the locked state indicates that the target resource is not locked, it means that the test process at this time requires the second CPU core corresponding to the target resource to execute. At this time, the first CPU core controls the second CPU core corresponding to the unlocked target resource to perform chip testing simultaneously based on the corresponding target resource and test commands. Multiple second CPU cores with unlocked target resources perform parallel testing to obtain the corresponding sub-test results, thereby providing an effective data foundation for obtaining the target chip test results later.

[0071] It should be noted that when the locked state indicates that the target resource is locked, the second CPU core corresponding to the locked target resource continues to wait for a new test command to unlock the resource.

[0072] Additionally, refer to Figure 4 In some embodiments, during execution Figure 3 Before each second CPU core determines the locking status of the corresponding target resource in step S310, the SOC chip testing method of this embodiment includes, but is not limited to, the following steps:

[0073] Step S410: Each second CPU core receives a test command;

[0074] In step S420, the target CPU core unlocks the corresponding target resources based on the test command, wherein the target CPU core belongs to the second CPU core.

[0075] It is understandable that before each second CPU core determines the locked state of the corresponding target resource, each second CPU core receives a test command. Different second CPU cores perform different operations on the target resource based on the test command. For example, referring to the description of the above embodiment, after CPU1, CPU2 and CPU3 in the second CPU cores receive the test command, they need to be tested simultaneously. Then, CPU1, CPU2 and CPU3 are all target CPU cores and all need to unlock the corresponding target resource based on the test command. When the test command only instructs CPU1 and CPU2 to perform the unlocking operation of the target resource, then CPU1 and CPU2 are the target CPU cores, while CPU3 needs to continue to wait for unlocking.

[0076] Additionally, refer to Figure 5 In some embodiments, during execution Figure 1 Before the SOC chip under test sends a boot success command to the ATE test machine via the FT test board and test motherboard in step S110, the SOC chip testing method provided in this application embodiment includes, but is not limited to, the following steps:

[0077] Step S510: The ATE tester is powered on, thereby starting the SOC chip under test;

[0078] Step S520: The ATE tester performs power consumption performance testing on the SOC chip under test.

[0079] Understandably, due to the connection between the ATE tester and the SOC chip under test, the ATE tester powers on the SOC chip under test simultaneously, starting the SOC chip. Furthermore, power consumption testing is an important part of evaluating chip performance and stability, and power-on current is one of the key indicators in power consumption testing. The ATE tester performs power consumption performance tests on the SOC chip under test, such as power-on current testing, thereby providing strong support for chip performance evaluation.

[0080] Additionally, refer to Figure 6 In some embodiments, Figure 1 The first CPU core in step S130 starts each of the second CPU cores, including but not limited to the following steps:

[0081] Step S610: The first CPU core sends a power-on reset signal to each of the second CPU cores;

[0082] In step S620, the first CPU core sends a core reset signal to each of the second CPU cores;

[0083] Step S630: The first CPU core sets the power switch registers of all the second CPU cores so that all the second CPU cores are in the power-on state.

[0084] Step S640: The first CPU core performs a power gating state clearing operation on all second CPU cores;

[0085] In step S650, the first CPU core controls each of the second CPU cores to release the power-on reset signal;

[0086] In step S660, the first CPU core controls each of the second CPU cores to release the core reset signal;

[0087] Step S670: The first CPU core starts each of the second CPU cores.

[0088] As can be understood, the specific steps for the first CPU core to start each of the second CPU cores in this embodiment are as follows: the first CPU core sends a power-on reset signal (Assert poweron reset) to each of the second CPU cores; the first CPU core sends a core reset signal (Assert core reset) to each of the second CPU cores; the first CPU core sets the power switch registers of all the second CPU cores to put all the second CPU cores in the power-on state (Set powerswitch); the first CPU core performs a power-gating operation (Clear powergating) on ​​all the second CPU cores; the first CPU core controls each of the second CPU cores to release the power-on reset signal (De-assert poweron reset); the first CPU core controls each of the second CPU cores to release the core reset signal (De-assert core reset); and finally, the first CPU core starts each of the second CPU cores (DBGPWR up). This provides strong support for starting each of the second CPU cores for parallel testing.

[0089] Additionally, refer to Figure 8 This embodiment also provides a SOC chip testing device for performing the SOC chip testing method as described in any one of claims 1 to 6. The SOC chip testing device includes an ATE tester, a test motherboard, and an FT test board. The test motherboard is communicatively connected to the ATE tester and the FT test board, respectively. The FT test board is electrically connected to the SOC chip under test. The SOC chip under test includes at least a first CPU core and multiple second CPU cores. The first CPU core is communicatively connected to each of the second CPU cores.

[0090] like Figure 7 As shown, Figure 7 This is a structural diagram of a control device provided in one embodiment of this application. The present invention also provides a control device 700, comprising:

[0091] The processor 710 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0092] The memory 720 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 720 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 720 and called and executed by the processor 710 using the SOC chip testing method of the embodiments of this application.

[0093] The input / output interface 730 is used to implement information input and output;

[0094] The communication interface 740 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0095] Bus 750 transmits information between various components of the device (e.g., processor 710, memory 720, input / output interface 730, and communication interface 740);

[0096] The processor 710, memory 720, input / output interface 730 and communication interface 740 are connected to each other within the device via bus 750.

[0097] In addition, this application also provides an electronic device, including the control device 700 described in the above embodiments.

[0098] In addition, this application embodiment also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the above-described SOC chip testing method.

[0099] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0100] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0101] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A method for testing a System-on-a-Chip (SOC) chip, characterized in that, An application is made in a SOC chip testing apparatus, the SOC chip testing apparatus comprising an ATE tester, a test motherboard, and an FT test board, wherein the test motherboard is communicatively connected to the ATE tester and the FT test board respectively, and the FT test board is electrically connected to the SOC chip under test, the SOC chip under test comprising at least a first CPU core and multiple second CPU cores, wherein the first CPU core is communicatively connected to each of the second CPU cores, and the method comprises: After the SOC chip under test is powered on, the SOC chip under test sends a boot success command to the ATE test machine through the FT test board and the test motherboard. When the ATE test machine detects the boot success command, the ATE test machine sends test commands to the SOC chip under test through the test motherboard and the FT test board. When the first CPU core in the SOC chip under test receives the test command, the first CPU core allocates corresponding target resources to each of the second CPU cores. Each of the target resources is different and independent of each other. The target resources are chip test resources used for chip testing. The first CPU core starts each of the second CPU cores and controls each of the second CPU cores to perform chip testing based on the corresponding target resources, and obtains sub-test results; The first CPU core detects the test status information of each of the second CPU cores, obtains each of the sub-test results, and sends all the test status information and all the test results to the ATE test machine through the FT test board and the test motherboard. The ATE test machine generates target chip test results based on the results of each of the sub-tests.

2. The SOC chip testing method according to claim 1, characterized in that, The first CPU core allocates corresponding target resources to each of the second CPU cores, including: The first CPU core initializes the chip test resources of the SOC chip under test; The first CPU core divides the chip test resources based on the core capacity of each of the second CPU cores to obtain multiple target resources; The first CPU core allocates each of the target resources to the corresponding second CPU cores; The first CPU core uses the lock_mutex function to lock the target resources in each of the second CPU cores.

3. The SOC chip testing method according to claim 2, characterized in that, The first CPU core starts each of the second CPU cores and controls each of the second CPU cores to perform chip testing based on the corresponding target resources, obtaining sub-test results, including: After the first CPU core starts each of the second CPU cores, each of the second CPU cores determines the locking status of the corresponding target resource; When the locking state indicates that the target resource is not locked, the first CPU core controls the second CPU core corresponding to the unlocked target resource to perform chip testing based on the corresponding target resource and the test command, and obtain the sub-test result.

4. The SOC chip testing method according to claim 3, characterized in that, Before each of the second CPU cores determines the locking state of the corresponding target resource, the method includes: Each of the second CPU cores receives the test command; The target CPU core unlocks the corresponding target resources based on the test command, wherein the target CPU core belongs to the second CPU core.

5. The SOC chip testing method according to claim 1, characterized in that, Before the SOC chip under test sends a boot success command to the ATE test machine through the FT test board and the test motherboard, the method further includes: The ATE tester is powered on, thereby starting the SOC chip under test; The ATE tester performs power consumption performance tests on the SOC chip under test.

6. The SOC chip testing method according to claim 1, characterized in that, The first CPU core boots each of the second CPU cores, including: The first CPU core sends a power-on reset signal to each of the second CPU cores; The first CPU core sends a core reset signal to each of the second CPU cores; The first CPU core sets the power switch registers of all the second CPU cores so that all the second CPU cores are in the power-on state; The first CPU core performs a power gating state clearing operation on all second CPU cores; The first CPU core controls each of the second CPU cores to release the power-on reset signal; The first CPU core controls each of the second CPU cores to release the core reset signal; The first CPU core starts each of the second CPU cores.

7. A SOC chip testing device, characterized in that, The SOC chip testing device is used to perform the SOC chip testing method as described in any one of claims 1 to 6. The SOC chip testing device includes an ATE tester, a test motherboard, and an FT test board. The test motherboard is communicatively connected to the ATE tester and the FT test board, respectively. The FT test board is electrically connected to the SOC chip under test. The SOC chip under test includes at least a first CPU core and a plurality of second CPU cores. The first CPU core is communicatively connected to each of the second CPU cores.

8. A control device, characterized in that, It includes at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, which, when executed by the at least one control processor, enable the at least one control processor to perform the SOC chip testing method as described in any one of claims 1 to 6.

9. An electronic device, characterized in that, Includes the control device as described in claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the SOC chip testing method as described in any one of claims 1 to 6.

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