Device for multi-chip integrated packaging of high-density computing modules

Abstract

The present invention relates to the technical field of multi-chip integrated packaging, and in particular to a device for a multi-chip integrated packaging high-density computing power module, comprising: a plurality of modules, each module comprising a plurality of intelligent acceleration chips, a substrate, two connectors and an auxiliary controller, wherein the plurality of intelligent acceleration chips are arranged in rows and columns on the front of the substrate to be packaged into a matrix computing unit to perform a target computing task; an auxiliary controller, which is respectively connected to the plurality of intelligent acceleration chips and two connectors to obtain the working status of each chip, and judge whether the current module is faulty according to the working status of each chip; a system controller, which is connected to the auxiliary controller in each module to perform task migration of the faulty module; a connector cascade module, which is respectively connected to each module and the system controller to expand the number of modules according to the target computing task. Thus, the problems of limited computing power and delayed transmission caused by the traditional acceleration card integrating only a single chip are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-chip integrated packaging, and in particular to a device for multi-chip integrated packaging of a high-density computing power module. Background Art

[0002] With the rapid development of modern science and technology and artificial intelligence technology, various models and algorithms have increasingly higher requirements for computing power. Although the processing power of a single chip is constantly improving, it is difficult to meet the growing computing needs.

[0003] In existing traditional acceleration cards, one acceleration chip is usually integrated in one acceleration card, and the computing power scale is limited by the number of PCIE slots in the server, so it is impossible to integrate multiple acceleration cards. At the same time, the inter-chip communication of the chips needs to be executed through CPU forwarding, passing through multiple transit paths, resulting in large delays in the data transmission process, reducing execution efficiency, and may also cause data loss or errors. When collaborative computing is required, some acceleration cards will be idle or waiting, reducing utilization and execution efficiency. Summary of the invention

[0004] The present invention provides a device for packaging a high-density computing power module with multiple chips, so as to solve the problems of limited computing power and transmission delay caused by the traditional acceleration card integrating only a single acceleration chip.

[0005] A first aspect of an embodiment of the present invention provides a device for a multi-chip integrated packaging high-density computing power module, comprising:

[0006] A plurality of modules, each of which comprises a plurality of smart acceleration chips, a substrate, a first connector, a second connector and an auxiliary controller, wherein:

[0007] The multiple intelligent acceleration chips are arranged in rows and columns on the front side of the substrate, the sending channel and the receiving channel above the first row of intelligent acceleration chips on the substrate are connected to the second connector, the sending channel and the receiving channel to the left of the first column of intelligent acceleration chips on the substrate are connected to the second connector, the sending channel and the receiving channel below the last row of intelligent acceleration chips on the substrate are connected to the first connector, the sending channel and the receiving channel to the right of the last column of intelligent acceleration chips on the substrate are connected to the first connector, and the sending channels and the receiving channels in four directions of the intelligent acceleration chips at other positions are respectively connected to their adjacent intelligent acceleration chips, so as to be packaged into a matrix computing unit to perform the target computing task;

[0008] The auxiliary controller is respectively connected to the multiple smart acceleration chips, the first connector, and the second connector to obtain the working status of each smart acceleration chip, and judge whether the current module fails according to the working status of each smart acceleration chip, and reset the failed chip;

[0009] A system controller, the system controller is connected to the auxiliary controller in each module to obtain the working status of each module, and judge whether the current module fails according to the working status of each module, and perform task migration for the failed module;

[0010] A connector cascading module, wherein the connector cascading module is respectively connected to the system controller and each module to expand the number of modules according to the target computing task.

[0011] Optionally, the multiple intelligent acceleration chips include at least one of NPU, TPU, DPU, and APU.

[0012] Optionally, the sending channel and receiving channel with a high-speed serial communication interface above the first row of smart acceleration chips on the substrate are connected to the second connector, the sending channel and receiving channel with a high-speed serial communication interface on the left side of the first column of smart acceleration chips on the substrate are connected to the second connector, the sending channel and receiving channel with a high-speed serial communication interface below the last row of smart acceleration chips on the substrate are connected to the first connector, the sending channel and receiving channel with a high-speed serial communication interface on the right side of the last column of smart acceleration chips on the substrate are connected to the first connector, and the sending channels and receiving channels with a high-speed serial communication interface in four directions of the smart acceleration chips at the remaining positions are respectively connected to their adjacent smart acceleration chips.

[0013] Optionally, the auxiliary controller includes any one of a CPLD circuit, an MCU circuit, a SOC circuit, and an FPGA circuit.

[0014] Optionally, each module is provided with an independent ID code and SN code, wherein the ID code is obtained by the auxiliary controller by reading the pull-up and pull-down resistors of the resistor, and the SN code is written in the EEPROM of the module during production.

[0015] Optionally, the substrate adopts an even-numbered multilayer design, and its inner layer adopts a symmetrical design. At the same time, a whole layer of complete copper foil is retained after every N layers, so that different materials in the substrate maintain the same shrinkage coefficient in all directions under the support of the copper foil.

[0016] Optionally, each module further includes:

[0017] A temperature detection chip, which is arranged on the front side of the substrate and connected to the auxiliary controller to detect the temperatures of the multiple intelligent acceleration chips;

[0018] A metal bracket, wherein the metal bracket is arranged on the back side of the substrate;

[0019] A heat sink, the heat sink is fixed on the metal bracket in close contact with the multiple smart acceleration chips and is connected to the system controller, and controls its own fan speed according to the system controller to dynamically dissipate heat for the multiple smart acceleration chips;

[0020] A power supply is arranged on the front side of the substrate and is respectively connected to the auxiliary controller and the power supply to supply power to the current module.

[0021] Optionally, the auxiliary controller communicates with the plurality of intelligent acceleration chips through an SPI bus to obtain a working status of each chip, and uploads the working status of each intelligent acceleration chip to the system controller;

[0022] The auxiliary controller communicates with the temperature detection chip via the IIC bus to obtain the real-time temperature of the current module and uploads it to the system controller;

[0023] The auxiliary controller detects the state of the power supply through the GPIO port, uploads the state to the system controller, and controls the power supply.

[0024] Optionally, after each module is powered on, the auxiliary controller performs a self-test on all the smart acceleration chips and the power supply, and uploads the self-test result to the system controller, wherein the self-test result includes at least one of the smart acceleration chip working, the smart acceleration chip not working, the power supply is normal, the power supply is abnormal, the module temperature exceeds a threshold, and the module temperature is normal.

[0025] Optionally, when the self-test result obtained by the auxiliary controller is that the intelligent acceleration chip is not working, the system controller will perform task migration on the faulty intelligent acceleration chip and module, and after the task migration, the auxiliary controller restarts the current module.

[0026] Optionally, if the fault is not eliminated after the auxiliary controller restarts the current module, the system controller cuts off power to the current module and replaces the module.

[0027] Optionally, when the self-test result obtained by the auxiliary controller is that the power supply is abnormal, the system controller cuts off the power supply to the current module and replaces the current module.

[0028] Optionally, when the self-test result obtained by the auxiliary controller is that the module temperature exceeds a preset maximum threshold, the system controller cuts off power to the current module.

[0029] A second aspect of an embodiment of the present invention provides a computer, comprising a computer motherboard and a memory device, wherein the computer motherboard is provided with a device for a multi-chip integrated packaging high-density computing power module as described above.

[0030] The device of a multi-chip integrated packaging high-density computing power module proposed in an embodiment of the present invention effectively solves the problems of limited computing power, communication transmission delay, and substrate bending and deformation of traditional acceleration cards by increasing the packaging density of the chips and adopting a direct connection method; the device will bring revolutionary breakthroughs to the field of high-performance computing and promote the rapid development of related fields; it also has broad application prospects, and the significant improvement in computing power is more suitable for supporting complex computing systems composed of multiple network models.

[0031] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0033] Figure 1 A schematic diagram of the structure of a device for a multi-chip integrated packaging high-density computing power module provided by an embodiment of the present invention;

[0034] Figure 2 A schematic diagram of the structure of each module provided in an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of the data transmission direction of each chip provided by an embodiment of the present invention;

[0036] Figure 4 A schematic diagram of the structure of a substrate provided in an embodiment of the present invention, wherein (a) is the shape of the substrate, and (b) is a schematic diagram of the substrate stacking;

[0037] Figure 5 A schematic diagram of the structure of a metal bracket provided in an embodiment of the present invention;

[0038] Figure 6 It is a block diagram of a computer proposed in an embodiment of the present invention.

[0039] Description of reference numerals:

[0040] 10-device for multi-chip integrated packaging of high-density computing power modules, 101-multiple modules, 102-system controller, 60-computer, 601-computer motherboard and 602-memory device. DETAILED DESCRIPTION

[0041] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0042] The following describes the device of a multi-chip integrated packaging high-density computing power module of an embodiment of the present invention with reference to the accompanying drawings. In view of the problems mentioned in the above background technology center that the traditional acceleration card only integrates a single acceleration chip, resulting in limited computing power and transmission delay, the present invention provides a multi-chip integrated packaging technology, which integrates multiple intelligent acceleration chips in a package in a specific way to form a high-density computing power module. The high-density computing power module can break through the limitation of the processing capacity of a single acceleration chip, achieve an exponential increase in computing power per unit area, and solve the communication problems between acceleration chips, heat dissipation problems, and the selection of packaging materials. Problems to meet more complex and diverse computing needs in the future.

[0043] Specifically, Figure 1 A schematic diagram of the structure of a device for a multi-chip integrated packaging high-density computing power module provided in an embodiment of the present invention.

[0044] like Figure 1 As shown, the device 10 of the multi-chip integrated packaging high-density computing power module includes: multiple modules 101, a system controller 102 and a connector cascade module.

[0045] Each module 101 includes a plurality of intelligent acceleration chips, a substrate, a first connector, a second connector and an auxiliary controller. The plurality of intelligent acceleration chips are arranged in rows and columns on the front of the substrate. The plurality of intelligent acceleration chips are respectively connected to the first connector and the second connector to be packaged into a matrix computing unit to perform a target computing task. The auxiliary controller is respectively connected to the plurality of intelligent acceleration chips, the first connector and the second connector to obtain the working status of each chip of the plurality of intelligent acceleration chips, and judge whether the current module 101 is faulty according to the working status of each chip, and reset the faulty chip. The system controller 102 is connected to the auxiliary controller in each module 101 to obtain the working status of each module, and judge whether the current module is faulty according to the working status of each module, and perform task migration on the faulty module. The connector cascade module is respectively connected to the system controller 102 and each module 101 to expand the number of modules according to the target computing task. The device of the multi-chip integrated packaging high-density computing power module integrates multiple chips into a package to form a multi-chip packaged high-density module, so that the computing module power is no longer limited by the computing power of a single chip, and the computing power will increase exponentially according to the number of packaged chips.

[0046] It should be noted that the multiple intelligent acceleration chips can be at least one of NPU, TPU, DPU, APU, etc., but are not limited to this. Those skilled in the art can choose the chip type according to actual conditions.

[0047] In some embodiments, the sending channel and receiving channel with a high-speed serial communication interface above the first row of smart acceleration chips on the substrate are connected to the second connector set on the back side of the substrate, the sending channel and receiving channel with a high-speed serial communication interface to the left of the first column of smart acceleration chips on the substrate are connected to the second connector set on the back side of the substrate, the sending channel and receiving channel with a high-speed serial communication interface below the last row of smart acceleration chips on the substrate are connected to the first connector set on the back side of the substrate, the sending channel and receiving channel with a high-speed serial communication interface to the right of the last column of smart acceleration chips on the substrate are connected to the first connector set on the back side of the substrate, and the sending channels and receiving channels with a high-speed serial communication interface in four directions of the smart acceleration chips at the remaining positions are respectively connected to their adjacent smart acceleration chips, so that data can be transmitted inside multiple smart acceleration chips.

[0048] Specifically, among the multiple smart acceleration chips to be packaged, each smart acceleration chip has a sending channel and a receiving channel of a high-speed serial communication interface in the upper, lower, left and right directions respectively. The sending channel and the receiving channel of the high-speed serial communication interface at the top of the first row of the substrate are directly connected to the second connector, the sending channel and the receiving channel of the high-speed serial communication interface at the left of the smart acceleration chip in the first column of the substrate are connected to the second connector, the sending channel and the receiving channel of the high-speed serial communication interface at the bottom of the smart acceleration chip in the last row of the substrate are connected to the first connector, the sending channel and the receiving channel of the high-speed serial communication interface at the right of the smart acceleration chip in the last column of the substrate are connected to the first connector, and the sending channels and the receiving channels of the four directions of the smart acceleration chips at the remaining positions are respectively connected to their adjacent smart acceleration chips.

[0049] In the actual implementation process, Figure 2 As shown, the smart acceleration chips are evenly packaged on the substrate in the form of X rows and Y columns to form a matrix computing unit, where X and Y are both positive integers greater than or equal to 1. Taking the arrangement of 4 rows and 4 columns as an example, the high-speed serial communication interface sending channels and receiving channels below the smart acceleration chips A1, B1, C1, and D1 at the edge of the substrate are directly connected to the first connector F1; the high-speed serial communication interface sending channels and receiving channels above the smart acceleration chips A4, B4, C4, and D4 are directly connected to the second connector F2; the high-speed serial communication interface sending channels and receiving channels above the smart acceleration chips D1, D2, D3, and D4 are directly connected to the second connector F3; the high-speed serial communication interface sending channels and receiving channels above the smart acceleration chips A4, B4, C4, and D4 are directly connected to the second connector F2; the high-speed serial communication interface sending channels and receiving channels above the smart acceleration chips D1, D2, D3, and D4 are directly connected to the second connector F3. 4 is directly connected to the first connector F1; the high-speed serial communication interface sending channel and receiving channel on the left of the smart acceleration chip A1, the smart acceleration chip A2, the smart acceleration chip A3, and the smart acceleration chip A4 are directly connected to the second connector F2, and the smart acceleration chip B2, the smart acceleration chip B3, the smart acceleration chip C2, and the smart acceleration chip C3 are located at the center of the package. The high-speed serial communication interface sending channels and receiving channels of the four directions of these four smart acceleration chips are directly connected to the adjacent smart acceleration chips as shown in the figure, and data signals, control signals, and power can be simultaneously input and output through the first connector F1 and the second connector F2.

[0050] Taking the arrangement of 7 rows and 8 columns as an example, the high-speed serial communication interface sending channel and receiving channel below the smart acceleration chip A1, smart acceleration chip B1, smart acceleration chip C1, smart acceleration chip D1, smart acceleration chip E1, smart acceleration chip F1, smart acceleration chip G1, and smart acceleration chip H1 at the edge of the substrate are directly connected to the first connector F1; the high-speed serial communication interface sending channel and receiving channel above the smart acceleration chip A7, smart acceleration chip B7, smart acceleration chip C7, smart acceleration chip D7, smart acceleration chip E7, smart acceleration chip F7, smart acceleration chip G7, and smart acceleration chip H7 are directly connected to the first connector F1. The high-speed serial communication interface sending channel and receiving channel are directly connected to the second connector F2; the high-speed serial communication interface sending channel and receiving channel on the right of the smart acceleration chip H1, smart acceleration chip H2, smart acceleration chip H3, smart acceleration chip H4, smart acceleration chip H5, smart acceleration chip H6, and smart acceleration chip H7 are directly connected to the first connector F1; the smart acceleration chip A1, smart acceleration chip A2, smart acceleration chip A3, smart acceleration chip A4, smart acceleration chip A5, smart acceleration chip A6, and smart acceleration chip A7 are directly connected to the first connector F1; the ... The sending channel and receiving channel of the high-speed serial communication interface are directly connected to the second connector F2, the smart acceleration chip B2, the smart acceleration chip B3, the smart acceleration chip B4, the smart acceleration chip B5, the smart acceleration chip B6, the smart acceleration chip C2, the smart acceleration chip C3, the smart acceleration chip C4, the smart acceleration chip C5, the smart acceleration chip C6, the smart acceleration chip D2, the smart acceleration chip D3, the smart acceleration chip D4, the smart acceleration chip D5, the smart acceleration chip D6, the smart acceleration chip E2, the smart acceleration chip E3, the smart acceleration chip E4, the smart acceleration chip E5 , smart acceleration chip E6, smart acceleration chip F2, smart acceleration chip F3, smart acceleration chip F4, smart acceleration chip F5, smart acceleration chip F6, smart acceleration chip G2, smart acceleration chip G3, smart acceleration chip G4, smart acceleration chip G5, and smart acceleration chip G6 are located in the center of the package. The high-speed serial communication interface sending channels and receiving channels in four directions of these 30 smart acceleration chips are directly connected to the adjacent smart acceleration chips, and data signals, control signals and power can be input and output simultaneously through the first connector F1 and the second connector F2.

[0051] like Figure 3 As shown, taking the arrangement of 4 rows and 4 columns as an example, data transmission in the smart acceleration chip can be transmitted through the high-speed serial communication interface in the order of A1 to A4, or in the order of A1 to D1. Taking the arrangement of 7 rows and 8 columns as an example, data transmission in the smart acceleration chip can be transmitted through the high-speed serial communication interface in the order of A1 to A7, or in the order of A1 to H1.

[0052] In some embodiments, the data transmission process through the first connector and the second connector can be simplex, that is, sending or receiving separately, or duplex, that is, sending and receiving at the same time. The intelligent acceleration chip can be automatically selected according to the actual data volume and the computing task volume. The intelligent acceleration chips can also directly exchange data in four different situations: one-to-one, one-to-many, many-to-one, and many-to-many, without being transferred through the CPU, thereby reducing transmission delays. Technical personnel in this field can automatically select the data exchange method according to the actual data volume and the computing task volume.

[0053] That is to say, the smart acceleration chip can receive data according to the simplex and one-to-one or many-to-one data exchange mode in the aforementioned transmission mode, and synchronously calculate a large computing task, or it can receive data according to the duplex and one-to-many or many-to-many data exchange mode in the aforementioned transmission mode, and assign different tasks for asynchronous calculations.

[0054] It should be noted that by optimizing the communication and synchronization mechanisms between intelligent acceleration chips through data transmission protocols, signal processing algorithms, clock synchronization and other methods, efficient collaboration between intelligent acceleration chips can be ensured, thereby improving the performance and efficiency of the overall system.

[0055] In some embodiments, multiple smart acceleration chips in the embodiments of the present invention can also transmit data packets along a specified path, and verify the cyclic redundancy check code CRC of the data during the transmission process of each smart acceleration chip to ensure data validity.

[0056] During the actual execution process, the system controller 102 will select the intelligent acceleration chip of the specified path from the multiple modules 101 according to the specified path of the data packet, and then transmit the data on these paths in turn. Every time the data packet passes through an intelligent acceleration chip, the data bit sequence to be sent by the data packet will be divided by the preset generating polynomial agreed upon by the two communication parties, and a check code will be obtained according to the remainder polynomial. This check code is then attached to the data and sent to the current intelligent acceleration chip. After receiving the data, the current intelligent acceleration chip will divide the data with the same generating polynomial again. If the remainder obtained is not 0, it means that an error has been detected and the data is transmitted to the auxiliary controller. The auxiliary controller performs a working status detection and sends the detection result to the system controller 102. The system controller 102 re-determines the specified path and sends it to the auxiliary controller to continue the calculation. If the remainder is 0, it means that the data transmission is correct, and the calculation continues until all the intelligent acceleration chips on the path have completed the calculation.

[0057] In some embodiments, each module 101 is provided with an independent ID code and SN code, wherein the ID code is obtained by the auxiliary controller by reading the pull-up and pull-down resistors, that is, each multi-chip module has an independent ID code, the ID data length is 8 bits, and the SN code is written in the EEPROM (Electrically Erasable Programmable Read-Only Memory) of the module during production, indicating the serial number of the module, and the length of the SN code is not limited. Each smart acceleration chip is also provided with a serial number, which is solidified in the chip when it leaves the factory.

[0058] Specifically, each multi-chip module obtains a fixed and unique ID code of the multi-chip module by reading the pre-configured pull-up and pull-down resistors through the auxiliary controller when it is powered on, so that when a fault occurs in a subsequent module, the system controller 102 can find the corresponding multi-chip module in time. The SN code is written into the EEPROM of the module during production. Since the EEPROM is a non-volatile memory, the data therein can remain unchanged even if the module is powered off, thereby ensuring that when a fault occurs in a subsequent module, the system controller 102 can still find the corresponding SN code in time.

[0059] In some embodiments, Figure 4 As shown, the substrate adopts an even-numbered multilayer design, and its inner layer uses a symmetrical design. At the same time, a whole layer of complete copper foil is retained after every N layers, so that different materials in the substrate maintain the same shrinkage coefficient in all directions under the support of the copper foil. Among them, to ensure the flatness of the substrate, N is a positive integer and is greater than or equal to 1.

[0060] Specifically, designing the number of layers to be an even number can ensure the symmetry and balance of the structure, thereby reducing the uneven stress distribution and shrinkage coefficient differences caused by structural asymmetry. The symmetrical design of the inner layer can make the structure and layout of each layer mirror-symmetrical, thereby reducing the shrinkage coefficient changes caused by material differences and deviations in the manufacturing process, ensuring the electrical performance of the substrate, and reducing signal distortion and noise. Retaining a complete layer of copper foil every N layers can ensure electrical conductivity, reduce resistance and inductance, and enhance the overall strength of the substrate to avoid module deformation, cracking, and damage when integrating multiple smart acceleration chips.

[0061] In some embodiments, each module 101 may further include:

[0062] Metal bracket, such as 304 stainless steel metal bracket, such as Figure 5 As shown, the metal bracket is arranged on the back side of the substrate;

[0063] A heat sink is fixed to a metal bracket with screws in close contact with multiple smart acceleration chips and is connected to the system controller 102. The metal bracket disperses the force of the heat sink on the bracket to support the substrate, ensuring that all smart acceleration chips on the substrate are in flat contact with the contact surface of the heat sink, and all smart acceleration chips are cooled. The structure is easy to replace, supports hot plugging, and controls its own fan speed according to the system controller 102 to dynamically cool multiple smart acceleration chips;

[0064] A temperature detection chip is arranged on the front side of the substrate and connected to the auxiliary controller to detect the temperature of each module;

[0065] The power supply is arranged on the front side of the substrate and is respectively connected to the auxiliary controller and the power supply to supply power to the current module 101 .

[0066] In some embodiments, the auxiliary controller includes any one of a CPLD circuit, an MCU circuit, a SOC circuit, and an FPGA circuit, but is not limited thereto. Those skilled in the art may select a corresponding control chip according to actual conditions.

[0067] Furthermore, the auxiliary controller communicates with multiple intelligent acceleration chips through the SPI bus to obtain the working status of each intelligent acceleration chip, and uploads the working status of each intelligent acceleration chip to the system controller 102; the auxiliary controller communicates with the temperature detection chip through the IIC bus to obtain the real-time temperature of the current module 101, and uploads it to the system controller 102; the auxiliary controller detects the status of the power supply through the GPIO port, uploads it to the system controller 102, and controls the power supply.

[0068] In the actual implementation process, after each module 101 is powered on, the auxiliary controller in the module will perform self-test on all chips and power supplies. If the self-test passes, the self-test information will be uploaded to the system controller 102. If the self-test fails, the fault information will be uploaded to the system controller 102. The self-test results include whether the smart acceleration chip is working, the smart acceleration chip is not working, the power supply is normal, the power supply is abnormal, the module temperature exceeds the threshold, and the module temperature is normal.

[0069] When the self-test result shows that the intelligent acceleration chip is not working, the power supply is normal, and the module temperature is normal, the auxiliary controller will send the ID code and SN code of the module 101 where the non-working intelligent acceleration chip is located to the system controller 102, and then the system controller 102 can determine the specific module where the faulty intelligent acceleration chip is located according to the SN code and ID code, and perform task migration on the module and the intelligent acceleration chip in the module. After the migration is completed, the auxiliary controller resets the module. If the problem cannot be eliminated after the reset, the module is powered off and the power indicator light goes out. The module can be replaced (hot plugging is supported).

[0070] When the self-test result shows that the intelligent acceleration chip is working, the power supply is abnormal, and the module temperature is normal, the auxiliary controller reports the ID code and power supply ID of the abnormal module to the system controller 102, and then the system controller 102 cuts off the power to the current module 101 according to the power supply ID and replaces it.

[0071] When the self-test result shows that the intelligent acceleration chip is working, the power supply is normal, and the module temperature exceeds the threshold, the auxiliary controller reports the ID code, SN code and specific temperature value of the module with abnormal temperature to the system controller 102. Then the system controller 102 finds the corresponding module and the heat sink of the module according to the ID code and SN code of the abnormal module, controls the fan acceleration speed of the heat sink according to the specific temperature value, and dynamically adjusts the heat dissipation of the module substrate.

[0072] If the module temperature value exceeds the preset maximum threshold, the system controller 102 finds the corresponding module according to the ID code and SN code of the abnormal module and cuts off the power to it. If the module has been dissipating heat for a period of time, but the module temperature has not decreased and / or continues to rise, the corresponding module is found according to the ID code and SN code of the abnormal module and cuts off the power to it.

[0073] When the self-test results show that the intelligent acceleration chip is working, the power supply is normal, and the module temperature is normal, the auxiliary controller will obtain the working status data in the module at fixed time intervals and upload the working status of the module to the system controller 102, where the working status data includes the module's ID code, SN code, temperature, power status, and the working status of the intelligent acceleration chip.

[0074] If the auxiliary controller detects a module failure during operation, the auxiliary controller will automatically report the failure to the system controller 102 in real time, and the system controller 102 will control and correct the module and restart it. The module failure includes the intelligent acceleration chip not working, power supply abnormality, and module temperature exceeding the preset threshold.

[0075] When the module failure is that the intelligent acceleration chip does not work, the auxiliary controller will report the ID code and SN code of the module where the inoperative intelligent acceleration chip is located to the system controller 102. The system controller 102 performs task migration and other operations according to the module ID code and SN code, and then the auxiliary controller will restart the module. If the fault cannot be eliminated after restarting, the module will be powered off, and the power indicator light will go out. The module can be replaced (hot plugging is supported); when the module failure is a power failure, the auxiliary controller reports the ID code, SN code and power ID of the abnormal module to the system controller 102, and the system controller 102 powers off the current module 101 according to the power ID; if the module temperature exceeds the threshold, the auxiliary controller reports the ID code, SN code and specific temperature value of the abnormal temperature module to the system controller 102, and the system controller 102 will control the radiator to dynamically adjust the heat dissipation of the current module 101 according to the specific temperature value.

[0076] In some embodiments, the number of modules can be expanded through a connector cascade module between modules. After the modules are expanded, the data transmission is still transmitted according to the above transmission method. Since the ID code of the module is 8 bits, it can support the cascading of up to 0-255 modules. This cascading can be in any direction. For example, taking module one with 4 rows and 4 columns and module two with 7 rows and 8 columns as examples, module one with 4 rows and 4 columns can be connected to any side of module two with 7 rows and 8 columns through a connector cascade module, and module two with 7 rows and 8 columns can also be connected to any side of module one with 4 rows and 4 columns through a connector cascade module. In addition, those skilled in the art can also use a connector cascade module with redundant design and fault detection function to improve the fault tolerance and stability of the system. This modular and scalable design enables the device to be flexibly configured according to different application requirements, and by replacing or adding or subtracting chip modules, the functional expansion or customization of different computing power modules can be achieved, which is practical and flexible.

[0077] The device for multi-chip integrated packaging of high-density computing power modules according to the embodiment of the present invention has the following beneficial effects:

[0078] (1) By tightly packaging multiple high-performance intelligent acceleration chips in the same module, the overall performance of the acceleration card is improved by increasing the computing power by the number of intelligent acceleration chips per unit area, achieving a doubling of the computing power. This not only improves the overall processing speed, but also meets the needs of complex and high-load computing tasks.

[0079] (2) The computing power of multiple intelligent acceleration chips can be used simultaneously through parallel processing, thereby improving computing efficiency. Since multiple intelligent acceleration chips share computing tasks, the workload of each intelligent acceleration chip is dispersed, reducing the working pressure of a single intelligent acceleration chip, thereby extending the service life of the system;

[0080] (3) Direct connection is used to reduce the signal transfer path, which not only reduces the delay of data transmission, but also improves the accuracy and reliability of data. At the same time, the data CRC is verified during transmission to ensure the validity of data. This is especially important for application scenarios that require high-performance computers, servers, data centers, and other applications that require a lot of computing, such as real-time data analysis, high-performance simulation, and autonomous driving.

[0081] (4) Using full copper foil and back-mounted stainless steel brackets in the stack to keep the substrate flat, solving the problem of deformation as the substrate size increases;

[0082] (5) It has brought revolutionary breakthroughs to the field of high-performance computing, promoted the rapid development of related fields, and has broad application prospects. The significant improvement in computing power is more suitable for supporting complex computing systems composed of multiple network models.

[0083] Next, the computer proposed according to the embodiment of the present application is described with reference to the accompanying drawings.

[0084] Figure 6 It is a block diagram of a computer proposed in an embodiment of the present invention.

[0085] like Figure 6 As shown, the computer 60 includes a computer motherboard 601 and a memory device 602 .

[0086] Among them, the computer motherboard is provided with a device of the multi-chip integrated package high-density computing power module as mentioned above, and the memory device is loaded with data that needs to be calculated. When there is a complex calculation, the technicians in this field can input the relevant data into the memory device in advance, and the computer motherboard inputs the corresponding data into the device of the multi-chip integrated package high-density computing power module. Before the calculation, the device of the multi-chip integrated package high-density computing power module first performs a self-test and adjusts its internal components accordingly according to the self-test results to ensure that the device of the multi-chip integrated package high-density computing power module can perform normal complex calculations.

[0087] Furthermore, during the calculation process, the auxiliary controller in the device of the multi-chip integrated packaged high-density computing power module will obtain the working status data in the module at fixed time intervals, and adaptively adjust the device of the multi-chip integrated packaged high-density computing power module again according to the working status data to ensure that the device of the multi-chip integrated packaged high-density computing power module can successfully complete the calculation process.

[0088] It should be noted that if the amount of data is too large and the current number of modules cannot meet the computing requirements, the system controller can control the connector cascade module to connect new modules to expand the number of modules to complete the target computing task.

[0089] It should be noted that the aforementioned explanation of the device embodiment of the multi-chip integrated packaging high-density computing power module is also applicable to the computer of this embodiment and will not be repeated here.

[0090] The computer provided according to the embodiment of the present invention has the following beneficial effects:

[0091] (1) By tightly packaging multiple high-performance intelligent acceleration chips in the same module, the overall performance of the acceleration card is improved by increasing the computing power by the number of intelligent acceleration chips per unit area, achieving a doubling of the computing power. This not only improves the overall processing speed, but also meets the needs of complex and high-load computing tasks.

[0092] (2) The computing power of multiple intelligent acceleration chips can be used simultaneously through parallel processing, thereby improving computing efficiency. Since multiple intelligent acceleration chips share computing tasks, the workload of each intelligent acceleration chip is dispersed, reducing the working pressure of a single intelligent acceleration chip, thereby extending the service life of the system;

[0093] (3) Direct connection is used to reduce the signal transfer path, which not only reduces the delay of data transmission, but also improves the accuracy and reliability of data. At the same time, the data CRC is verified during transmission to ensure the validity of data. This is especially important for application scenarios that require high-performance computers, servers, data centers, and other applications that require a lot of computing, such as real-time data analysis, high-performance simulation, and autonomous driving.

[0094] (4) Using full copper foil and back-mounted stainless steel brackets in the stack to keep the substrate flat, solving the problem of deformation as the substrate size increases;

[0095] (5) It has brought revolutionary breakthroughs to the field of high-performance computing, promoted the rapid development of related fields, and has broad application prospects. The significant improvement in computing power is more suitable for supporting complex computing systems composed of multiple network models.

[0096] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0097] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A device for packaging a multi-chip high-density computing module, characterized in that: include: A plurality of modules, each of which comprises a plurality of smart acceleration chips, a substrate, a first connector, a second connector and an auxiliary controller, wherein: The multiple intelligent acceleration chips are arranged in rows and columns on the front side of the substrate, the sending channel and the receiving channel with a high-speed serial communication interface above the first row of intelligent acceleration chips on the substrate are connected to the second connector, the sending channel and the receiving channel with a high-speed serial communication interface to the left of the first column of intelligent acceleration chips on the substrate are connected to the second connector, the sending channel and the receiving channel with a high-speed serial communication interface below the last row of intelligent acceleration chips on the substrate are connected to the first connector, the sending channel and the receiving channel with a high-speed serial communication interface to the right of the last column of intelligent acceleration chips on the substrate are connected to the first connector, and the sending channels and the receiving channels with a high-speed serial communication interface in four directions of the intelligent acceleration chips at other positions are respectively connected to their adjacent intelligent acceleration chips, so as to be packaged into a matrix computing unit to perform target computing tasks; The auxiliary controller is respectively connected to the multiple smart acceleration chips, the first connector, and the second connector to obtain the working status of each smart acceleration chip, determine whether the current module fails according to the working status of each smart acceleration chip, and reset the failed chip; A system controller, the system controller is connected to the auxiliary controller in each module to obtain the working status of each module, and judge whether the current module fails according to the working status of each module, and perform task migration for the failed module; A connector cascading module, wherein the connector cascading module is respectively connected to the system controller and each module to expand the number of modules according to the target computing task.

2. The device of multi-chip integrated packaging high-density computing power module according to claim 1, characterized in that: The multiple intelligent acceleration chips include at least one of NPU, TPU, DPU, and APU.

3. The device of multi-chip integrated packaging high-density computing power module according to claim 1, characterized in that: The auxiliary controller includes any one of a CPLD circuit, an MCU circuit, a SOC circuit, and an FPGA circuit.

4. The device of multi-chip integrated packaging high-density computing power module according to claim 1, characterized in that: Each module is provided with an independent ID code and SN code, wherein the ID code is obtained by the auxiliary controller through reading the pull-up and pull-down resistors of the resistor, and the SN code is written in the EEPROM of the module during production.

5. The device of multi-chip integrated packaging high-density computing power module according to claim 1, characterized in that: The substrate adopts an even-numbered multilayer design, and its inner layer adopts a symmetrical design. At the same time, a whole layer of complete copper foil is retained after every N layers, so that different materials in the substrate maintain the same shrinkage coefficient in all directions under the support of the copper foil.

6. The device of multi-chip integrated packaging high-density computing power module according to claim 1, characterized in that: Each module further comprises: A temperature detection chip, which is arranged on the front side of the substrate and connected to the auxiliary controller to detect the temperature of each module; A metal bracket, wherein the metal bracket is arranged on the back side of the substrate; A heat sink, the heat sink is fixed on the metal bracket in close contact with the multiple smart acceleration chips and is connected to the system controller to control its own fan speed according to the system controller to dynamically dissipate heat for the multiple smart acceleration chips; A power supply is arranged on the front side of the substrate and is respectively connected to the auxiliary controller and the power supply to supply power to the current module.

7. The device of multi-chip integrated packaging high-density computing power module according to claim 6, characterized in that: The auxiliary controller communicates with the plurality of intelligent acceleration chips through the SPI bus to obtain the working status of each chip, and uploads the working status of each chip to the system controller; The auxiliary controller communicates with the temperature detection chip via the IIC bus to obtain the real-time temperature of the current module and uploads it to the system controller; The auxiliary controller detects the state of the power supply through the GPIO port, uploads the state to the system controller, and controls the power supply.

8. The device of multi-chip integrated packaging high-density computing power module according to claim 7, characterized in that: After each module is powered on, the auxiliary controller performs a self-test on all the smart acceleration chips and the power supply, and uploads the self-test result to the system controller, wherein the self-test result includes at least one of the smart acceleration chip working, the smart acceleration chip not working, the power supply is normal, the power supply is abnormal, the module temperature exceeds a threshold, and the module temperature is normal.

9. The device of multi-chip integrated packaging high-density computing power module according to claim 8, characterized in that: When the self-test result obtained by the auxiliary controller is that the intelligent acceleration chip is not working, the system controller will perform task migration on the faulty intelligent acceleration chip and module, and after the task migration, the auxiliary controller restarts the current module.

10. The device of multi-chip integrated packaging high-density computing power module according to claim 9, characterized in that: If the fault is not eliminated after the auxiliary controller restarts the current module, the system controller cuts off the power supply to the current module and replaces the module.

11. The device of multi-chip integrated packaging high-density computing power module according to claim 8, characterized in that: When the self-test result obtained by the auxiliary controller is that the power supply is abnormal, the system controller cuts off the power supply to the current module and replaces the current module.

12. The device of multi-chip integrated packaging high-density computing power module according to claim 8, characterized in that: When the self-test result obtained by the auxiliary controller is that the module temperature exceeds a preset maximum threshold, the system controller cuts off power to the current module.

13. A computer, comprising a computer motherboard and a memory, wherein the computer motherboard cooperates with the computer memory, characterized in that: The computer mainboard is provided with a device of a multi-chip integrated packaging high-density computing power module as described in any one of claims 1-12.

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