A planar gate β-type gallium oxide VDMOS device and its preparation method

Abstract

The present invention discloses a planar gate β-type gallium oxide VDMOS device and a preparation method thereof, which relates to the field of semiconductor technology, and comprises a drain metal, wherein the drain metal is located at the bottom of the device, an n-type SiC substrate is arranged above the drain metal, an n-type β-type gallium oxide is arranged above the n-type SiC substrate, and pure β-gallium oxide is arranged above the n-type β-gallium oxide; n+β-gallium oxide and p-type NiO are arranged above the pure β-gallium oxide. x , the n+β gallium oxide and p-type NiO x A source metal is arranged above the pure β-gallium oxide, a gate dielectric is also arranged above the pure β-gallium oxide, and a gate metal is arranged above the gate dielectric. By using pure β-gallium oxide as the shutdown blocking current region, the problem of difficult implementation of p-type doping is avoided, and the conduction characteristics of the device will not be affected by the heterojunction; a parasitic body diode is built through the heterostructure to help the device to continue current when it is not turned on.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a planar gate beta-type gallium oxide VDMOS device and a preparation method thereof. Background Art

[0002] As one of the representatives of ultra-wide bandgap semiconductor devices, gallium oxide has a bandgap width of about 48eV, a critical breakdown field strength of up to 8MV / cm, and an electron mobility of 300cm2 / V·s. However, due to the difficulty in achieving p-type doping and the low activation rate, the types of gallium oxide devices are severely limited. At the same time, the thermal conductivity of gallium oxide materials is low, making it difficult to widely promote in high-power-density RF and power applications.

[0003] The present invention adopts pure β-gallium oxide as the shutdown blocking current region, thereby avoiding the problems of difficult to implement p-type doping and low activation rate, and will not affect the conduction characteristics of the device due to the heterojunction; and a parasitic body diode is built through the heterostructure to help the device to continue current when it is not turned on. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a planar gate β-type gallium oxide VDMOS device and a method for preparing the same to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: a planar gate β-type gallium oxide VDMOS device, comprising a drain metal, the drain metal being located at the bottom of the device, an n-type SiC substrate being disposed above the drain metal, an n-type β-type gallium oxide being disposed above the n-type SiC substrate, and pure β-gallium oxide being disposed above the n-type β-type gallium oxide;

[0006] n+β-gallium oxide and p-type NiO are arranged above the pure β-gallium oxide. x , the n+β gallium oxide and p-type NiO x A source metal is arranged above the pure β-gallium oxide, a gate dielectric is arranged above the pure β-gallium oxide, a gate metal is arranged above the gate dielectric, and the gate metal is located at the top of the device.

[0007] Further optimizing the technical solution, the thickness of the n-type SiC substrate is 2 μm, the thickness of the n-type β-gallium oxide is 5-8 μm, the maximum thickness of the pure β-gallium oxide is 1 μm, the thickness of the n+β-gallium oxide is 500 nm, and the p-type NiO x The thickness of the gate dielectric is 200 nm, the thickness of the source metal is 200 nm, and the thickness of the gate metal is 100 nm.

[0008] Further optimizing the technical solution, the doping concentration of the n-type SiC substrate is 5e18cm -3 The doping concentration of the n-type β-gallium oxide is 6e17cm -3 The doping concentration of n+β gallium oxide is 2e19cm -3 , the p-type NiO x The doping concentration is 5e19cm -3 .

[0009] To further optimize the technical solution, the gate dielectric is a high-K dielectric, which includes one of silicon nitride, aluminum oxide and hafnium oxide; the source metal, drain metal and gate metal include one or more alloys of aluminum, copper, chromium, titanium and tungsten.

[0010] To further optimize the technical solution, the pure β-gallium oxide is the current blocking region when the device is turned off. When a positive voltage is applied to the gate metal of the device, electrons from the n+ β-gallium oxide region move to the bottom of the gate metal, forming a conductive path from the source metal to the n-type β-gallium oxide, and the device is turned on.

[0011] Further optimization of this technical solution, the device is not turned on, but when the source metal is positively voltageed, the source metal and the p-type NiO x Forming ohmic contact, p-type NiO x A heterojunction is formed with n-type β-type gallium oxide for short-time freewheeling. After the short-time freewheeling, the device is turned on and works normally.

[0012] A method for preparing a planar gate β-type gallium oxide VDMOS device is prepared based on the above-mentioned planar gate β-type gallium oxide VDMOS device, comprising the following specific steps:

[0013] S1. epitaxially growing a layer of n-type β-gallium oxide on an n-type SiC substrate with a drain metal;

[0014] S2, epitaxially growing a layer of pure β-gallium oxide on the n-type β-gallium oxide;

[0015] S3, depositing a barrier layer on pure β-gallium oxide, etching through holes of n-type β-gallium oxide, and performing Si ion implantation;

[0016] S4, removing the barrier layer in step S3, re-forming a new barrier layer, and etching p-type NiO x Through hole, etching p-type NiO x grooves;

[0017] S5, removing the barrier layer in step S4, re-forming a new barrier layer, and etching p-type NiO x Via, etch source metal via, physical vapor deposition source metal;

[0018] S6, removing the barrier layer in step S5, re-forming a new barrier layer, etching a gate dielectric through hole, and physically vapor depositing a gate dielectric;

[0019] S7, removing the barrier layer in step S6, re-forming a new barrier layer, etching a gate through hole, and physically vapor depositing a gate metal.

[0020] To further optimize the technical solution, in step S1, the epitaxial growth of n-type β-gallium oxide adopts HVPE technology, and the growth temperature is 1050°C.

[0021] To further optimize the technical solution, in step S2, the epitaxial growth of pure β-gallium oxide adopts MBE technology, the growth temperature is 1200° C., and the vacuum degree is 10 mbar.

[0022] Further optimizing the technical solution, in step S4, etching p-type NiO x After the trench is formed, p-type NiO is deposited by chemical vapor deposition x The deposition conditions are 1050℃, 1.2MPa.

[0023] Compared with the prior art, the present invention provides a planar gate β-type gallium oxide VDMOS device and a preparation method thereof, which has the following beneficial effects:

[0024] 1. The planar gate β-type gallium oxide VDMOS device and its preparation method are based on β-type gallium oxide material and adopt VDMOS device structure. The critical breakdown field strength is as high as about 8 MV / cm. The device has high voltage resistance. The device substrate adopts n+ doped silicon carbide substrate. The process is mature, the thermal conductivity is strong, and the cost is low. It can effectively improve the power density of the device while improving the economic benefits.

[0025] 2. The planar-gate β-gallium oxide VDMOS device and its preparation method use pure β-gallium oxide as the off-current blocking region to avoid the problems of difficult p-type doping and low activation rate, and will not affect the conduction characteristics of the device due to the heterojunction; a parasitic body diode is built through the heterostructure to help the device to continue current when it is not turned on. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic cross-sectional view of a planar-gate β-type gallium oxide VDMOS device proposed in the present invention;

[0027] Figure 2 A schematic cross-sectional view of a device in step S1 of a method for preparing a planar gate β-type gallium oxide VDMOS device proposed in the present invention;

[0028] Figure 3A schematic cross-sectional view of a device in step S2 of a method for preparing a planar-gate β-type gallium oxide VDMOS device proposed in the present invention;

[0029] Figure 4 A schematic cross-sectional view of a device in step S3 of a method for preparing a planar gate β-type gallium oxide VDMOS device proposed in the present invention;

[0030] Figure 5 A schematic cross-sectional view of a device in step S4 of a method for preparing a planar gate β-type gallium oxide VDMOS device proposed by the present invention;

[0031] Figure 6 A schematic cross-sectional view of a device in step S5 of a method for preparing a planar gate β-type gallium oxide VDMOS device proposed by the present invention;

[0032] Figure 7 A schematic cross-sectional view of a device in step S6 of a method for preparing a planar-gate β-type gallium oxide VDMOS device proposed in the present invention;

[0033] Figure 8 It is a schematic cross-sectional view of a device in step S7 of a method for preparing a planar-gate β-type gallium oxide VDMOS device proposed in the present invention.

[0034] Figure: 1. Drain metal; 2. n-type SiC substrate; 3. n-type β-gallium oxide; 4. Pure β-gallium oxide; 5. n+β-gallium oxide; 6. p-type NiO x ; 7. Source metal; 8. Gate dielectric; 9. Gate metal. DETAILED DESCRIPTION

[0035] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Embodiment 1:

[0036] See also Figure 1 A planar gate β-gallium oxide VDMOS device includes a drain metal 1, the drain metal 1 is located at the bottom of the device, an n-type SiC substrate 2 is arranged above the drain metal 1, the silicon carbide conductive substrate has a mature process, low cost, and high thermal conductivity, which can effectively improve the power density of the device while improving economic benefits, an n-type β-gallium oxide 3 is arranged above the n-type SiC substrate 2, and a pure β-gallium oxide 4 is arranged above the n-type β-gallium oxide 3. n+β-gallium oxide 5 and p-type NiO are arranged above the pure β-gallium oxide 4. x6. The n+β-gallium oxide 5 and p-type NiO x A source metal 7 is arranged above the device 6, a gate dielectric 8 is also arranged above the pure β-gallium oxide 4, a gate metal 9 is arranged above the gate dielectric 8, and the gate metal 9 is located at the top of the device. The gate dielectric 8 is a high-K dielectric, and the high-K dielectric includes one of silicon nitride, aluminum oxide and hafnium oxide; the source metal 7, the drain metal 1 and the gate metal 9 include one or more alloys of aluminum, copper, chromium, titanium and tungsten.

[0037] The device adopts a VDMOS device structure, with a bandgap width of approximately 48eV, a critical breakdown field strength of up to 8MV / cm, and a high voltage withstand capability.

[0038] The thickness of the n-type SiC substrate 2 is 2 μm, the thickness of the n-type β-gallium oxide 3 is 5-8 μm, the maximum thickness of the pure β-gallium oxide 4 is 1 μm, the thickness of the n+β-gallium oxide 5 is 500 nm, and the thickness of the p-type NiO x The thickness of the dielectric 6 is 1 μm, the thickness of the gate dielectric 8 is 200 nm, the thickness of the source metal 7 is 200 nm, and the thickness of the gate metal 9 is 100 nm.

[0039] The doping concentration of the n-type SiC substrate is 5e18cm -3 The doping concentration of the n-type β-type gallium oxide 3 is 6e17cm -3 The doping concentration of the n+β-gallium oxide 5 is 2e19cm -3 , the p-type NiO x The doping concentration of 6 is 5e19cm -3 .

[0040] Furthermore, the doping concentration of the n-type SiC substrate 2 is to form an ohmic contact with the drain metal 1 and reduce the on-resistance of the device, the doping concentration of the n-type β-gallium oxide 3 is to ensure a compromise between the device withstand voltage and the on-resistance of the device, the doping concentration of the n+β-gallium oxide 5 is to form an ohmic contact with the source metal 7 and provide electrons from the n+β-gallium oxide 5 source region to the gate when the device is turned on after a positive voltage is applied, thereby reducing the on-resistance of the device, and the p-type NiO x The doping concentration of 6 is due to the relatively low activation rate of the device. High doping can ensure the hole concentration, form an ohmic contact with the source metal 7, and contact with the p-type NiO x 6 Form a heterojunction.

[0041] In this embodiment, since p-type doping of gallium oxide is difficult and the activation rate is low, it cannot form a pn junction similar to traditional Si-based devices. Pure β-gallium oxide 4 is constructed as the current blocking region when the device is turned off. When a positive voltage is applied to the gate metal 9 of the device, electrons from the n+β-gallium oxide 5 region move to the bottom of the gate metal 9, forming a conductive path from the source metal 7 to the n-type β-gallium oxide 3, and the device is turned on. The device is not turned on, but when a positive voltage is applied to the source metal 7, the source metal 7 and the p-type NiO x 6 Forming ohmic contact, p-type NiO x 6 forms a heterojunction with the n-type β-type gallium oxide 3 for short-time freewheeling. After the short-time freewheeling, the device is turned on and works normally. Embodiment 2:

[0042] A method for preparing a planar gate β-type gallium oxide VDMOS device is prepared based on the planar gate β-type gallium oxide VDMOS device described in Example 1, and comprises the following specific steps:

[0043] S1, such as Figure 2 As shown, a layer of n-type β-gallium oxide 3 is epitaxially grown on an n-type SiC substrate 2 with a drain metal 1; the epitaxial growth of n-type β-gallium oxide 3 adopts HVPE technology at a growth temperature of 1050° C. The growth speed is fast using this technology, and the quality is slightly worse than that of MBE, but it has no effect on the withstand voltage part.

[0044] S2, such as Figure 3 As shown, a layer of pure β-gallium oxide 4 is epitaxially grown on n-type β-gallium oxide 3; the epitaxial growth of pure β-gallium oxide 4 adopts MBE technology, the growth temperature is 1200°C, and the vacuum degree is 10mbar. The growth speed is slow, but the quality is high.

[0045] S3, such as Figure 4 As shown, a barrier layer is deposited on the pure β-gallium oxide 4, a through hole of the n-type β-gallium oxide 3 is etched, and Si ion implantation is performed;

[0046] S4, such as Figure 5 As shown, the barrier layer in step S3 is removed, a new barrier layer is re-formed, p-type NiOx6 through holes are etched, and p-type NiO is etched. x 6 trench, etch p-type NiO x After the trench of 6, p-type NiO was deposited by chemical vapor deposition x 6. Deposition conditions are 1050℃, 1.2MPa.

[0047] S5, such as Figure 6 As shown, the barrier layer in step S4 is removed, a new barrier layer is formed, and the p-type NiO is etched. x 6 through hole, etching source metal 7 through hole, physical vapor deposition source metal 7;

[0048] S6, such as Figure 7 As shown, the barrier layer in step S5 is removed, a new barrier layer is re-formed, a through hole of the gate dielectric 8 is etched, and the gate dielectric 8 is physically deposited;

[0049] S7, such as Figure 8 As shown, the barrier layer in step S6 is removed, a new barrier layer is re-formed, a gate through hole is etched, and a gate metal 9 is physically vapor deposited.

[0050] The beneficial effects of the present invention are:

[0051] 1. The planar gate β-type gallium oxide VDMOS device and its preparation method are based on β-type gallium oxide material and adopt VDMOS device structure. The critical breakdown field strength is as high as about 8 MV / cm. The device has high voltage resistance. The device substrate adopts n+ doped silicon carbide substrate. The process is mature, the thermal conductivity is strong, and the cost is low. It can effectively improve the power density of the device while improving the economic benefits.

[0052] 2. The planar-gate β-gallium oxide VDMOS device and its preparation method use pure β-gallium oxide as the off-current blocking region to avoid the problems of difficult p-type doping and low activation rate, and will not affect the conduction characteristics of the device due to the heterojunction; a parasitic body diode is built through the heterostructure to help the device to continue current when it is not turned on.

[0053] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0054] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A planar gate β-type gallium oxide VDMOS device, characterized in that: It includes a drain metal, the drain metal is located at the bottom of the device, an n-type SiC substrate is arranged above the drain metal, an n-type β-type gallium oxide is arranged above the n-type SiC substrate, and pure β-gallium oxide is arranged above the n-type β-type gallium oxide; n+β-gallium oxide and p-type NiOx are arranged above the pure β-gallium oxide, a source metal is arranged above the n+β-gallium oxide and the p-type NiOx, the p-type NiOx is located on a side of the n+β-gallium oxide away from the pure β-gallium oxide, and both the p-type NiOx and the n+β-gallium oxide are in contact with the source metal, a gate dielectric is also arranged above the pure β-gallium oxide, a gate metal is arranged above the gate dielectric, and the gate metal is located at the top of the device; The thickness of the n-type SiC substrate is 2 μm, the thickness of the n-type β-gallium oxide is 5-8 μm, the maximum thickness of the pure β-gallium oxide is 1 μm, the thickness of the n+β-gallium oxide is 500 nm, and the p-type NiO x The thickness of the gate dielectric is 200 nm, the thickness of the source metal is 200 nm, and the thickness of the gate metal is 100 nm; The doping concentration of the n-type SiC substrate is 5e18cm -3 The doping concentration of the n-type β-gallium oxide is 6e17cm -3 The doping concentration of n+β gallium oxide is 2e19cm -3 , the p-type NiO x The doping concentration is 5e19cm -3 .

2. A planar gate β-type gallium oxide VDMOS device according to claim 1, characterized in that: The gate dielectric is a high-K dielectric, which includes one of silicon nitride, aluminum oxide and hafnium oxide; the source metal, drain metal and gate metal include one of aluminum, copper, chromium, titanium and tungsten or an alloy composed of several of them.

3. A method for preparing a planar gate β-type gallium oxide VDMOS device, based on the planar gate β-type gallium oxide VDMOS device according to any one of claims 1 to 2, characterized in that: The specific steps include: S1. epitaxially growing a layer of n-type β-gallium oxide on an n-type SiC substrate with a drain metal; S2, epitaxially growing a layer of pure β-gallium oxide on the n-type β-gallium oxide; S3, depositing a barrier layer on pure β-gallium oxide, etching through holes of n-type β-gallium oxide, and performing Si ion implantation; S4, removing the barrier layer in step S3, re-forming a new barrier layer, and etching p-type NiO x Through hole, etching p-type NiO x grooves; S5, removing the barrier layer in step S4, re-forming a new barrier layer, and etching p-type NiO x Via holes, etching source metal via holes, physical vapor deposition of source metal; S6, removing the barrier layer in step S5, re-forming a new barrier layer, etching a gate dielectric through hole, and physically vapor depositing a gate dielectric; S7, removing the barrier layer in step S6, re-forming a new barrier layer, etching a gate through hole, and physically vapor depositing a gate metal.

4. The method for preparing a planar gate β-type gallium oxide VDMOS device according to claim 3, characterized in that: In the step S1, the epitaxial growth of n-type β-gallium oxide adopts HVPE technology, and the growth temperature is 1050°C.

5. The method for preparing a planar gate β-type gallium oxide VDMOS device according to claim 3, characterized in that: In step S2, the epitaxial growth of pure β-gallium oxide adopts MBE technology, the growth temperature is 1200° C., and the vacuum degree is 10 mbar.

6. The method for preparing a planar gate β-type gallium oxide VDMOS device according to claim 3, characterized in that: In step S4, the p-type NiO is etched x After the trench is formed, p-type NiO is deposited by chemical vapor deposition x The deposition conditions are 1050℃, 1.2MPa.

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