Display substrate and display device

Abstract

The application discloses a display substrate and a display device, and belongs to the technical field of display. The display substrate comprises a substrate, a plurality of conductive pads, a first organic insulating layer and a first inorganic insulating layer. The first organic insulating layer has a first opening corresponding to at least one conductive pad, the second organic insulating layer has a second opening corresponding to the conductive pad, and the orthographic projection of the at least one conductive pad on the substrate is located in the orthographic projection of the corresponding first opening on the substrate, and the orthographic projection of the second opening on the substrate is located in the orthographic projection of the corresponding conductive pad on the substrate, so as to increase the distance between the first organic insulating layer and the pad area exposed by the second opening.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Currently, micro light-emitting diodes (LEDs) and mini light-emitting diodes (MLEDs) are smaller in size than traditional LEDs and can be widely used in display devices.

[0003] A display substrate includes a substrate and a plurality of conductive pads located on the substrate, wherein a portion of the conductive pads are used to bond to a light-emitting device (micro light-emitting diode or mini light-emitting diode), and another portion of the conductive pads are used to bond to a driver chip.

[0004] However, the aforementioned display substrate cannot achieve a good electrical connection with the light-emitting device or driver chip, resulting in a low yield rate for the display substrate. Summary of the Invention

[0005] This application provides a display substrate and a display device. The technical solution is as follows:

[0006] According to a first aspect of this application, a display substrate is provided, the display substrate comprising:

[0007] Substrate;

[0008] Multiple conductive pads are located on the substrate.

[0009] A first organic insulating layer is located on a substrate on which the conductive pad is disposed. The first organic insulating layer has a plurality of first openings, each of which corresponds to at least one of the conductive pads, and the orthographic projection of the at least one conductive pad on the substrate is located within the orthographic projection of the corresponding first opening on the substrate.

[0010] A first inorganic insulating layer is located on the side of the first organic insulating layer away from the substrate. The first inorganic insulating layer has a plurality of second openings, each of which corresponds to a conductive pad. The orthographic projection of the second opening onto the substrate is located within the orthographic projection of the corresponding conductive pad onto the substrate.

[0011] Optionally, the display substrate further includes a conductive anti-oxidation layer, which is located on a substrate on which the first inorganic insulating layer is disposed. The orthographic projection of the conductive anti-oxidation layer on the substrate is located in the orthographic projection of the second opening on the substrate, and the conductive anti-oxidation layer covers the pad area in the conductive pad away from the surface of the substrate. The pad area is the area of ​​the conductive pad exposed at the second opening.

[0012] Optionally, the shortest distance between two adjacent conductive pads is greater than or equal to a first preset value, and the first opening corresponds to one of the conductive pads.

[0013] Optionally, the shortest distance between two adjacent conductive pads is less than a first preset value, and the first opening corresponds to a plurality of conductive pads.

[0014] Optionally, the range of the first preset value is 30 micrometers to 60 micrometers.

[0015] Optionally, the plurality of conductive pads includes a plurality of first conductive pads and a plurality of second conductive pads;

[0016] Every two first conductive pads constitute a first conductive pad group, and one first conductive pad group is used to connect to a light-emitting device.

[0017] Every N second conductive pads constitute a second conductive pad group, and one second conductive pad group is used to connect to a driver chip.

[0018] The first opening includes a first sub-opening and a second sub-opening, the first sub-opening corresponding to one of the first conductive pad groups, and the second sub-opening corresponding to one of the second conductive pad groups.

[0019] Optionally, the plurality of conductive pads includes a plurality of first conductive pads and a plurality of second conductive pads;

[0020] Every two first conductive pads constitute a first conductive pad group, and one first conductive pad group is used to connect to a light-emitting device.

[0021] Every N second conductive pads constitute a second conductive pad group, and each second conductive pad group is used to connect to a driver chip.

[0022] The first opening includes a first sub-opening and a second sub-opening, the first sub-opening corresponding to at least three adjacent first conductive pad groups, and the second sub-opening corresponding to one second conductive pad group.

[0023] Optionally, the distance between adjacent first sub-openings and second sub-openings ranges from 20 micrometers to 100 micrometers.

[0024] Optionally, the first opening corresponds to at least one second opening, and the orthographic projection of the at least one second opening on the substrate is located in the orthographic projection of the corresponding first opening on the substrate.

[0025] The shortest distance between the edge of the orthographic projection of the first opening on the substrate and the edge of the orthographic projection of at least one second opening on the substrate ranges from 20 micrometers to 80 micrometers.

[0026] Optionally, the display substrate is rectangular, and the display substrate has two opposing first edges and two opposing second edges;

[0027] The display substrate also includes a connection terminal and a side trace located at the second edge, and the connection terminal and the side trace are electrically connected.

[0028] The plurality of first openings includes a target first opening, which is adjacent to the first edge, and the edge of the target first opening coincides with the edge of the first organic insulating layer located at the first edge.

[0029] Optionally, the first organic insulating layer further has a third opening adjacent to the second edge, the third opening corresponding to at least one of the conductive pads, and the edge of the orthographic projection of the third opening on the substrate is at least partially located outside the orthographic projection of the corresponding at least one conductive pad on the substrate.

[0030] There is a second predetermined distance between the edge of the third opening and the edge of the first organic insulating layer located at the second edge.

[0031] Optionally, the range of the second preset distance is 20 micrometers to 50 micrometers.

[0032] Optionally, the display substrate also has an alignment mark, and the first organic insulating layer also has a fourth opening, which is adjacent to the alignment mark;

[0033] The fourth opening corresponds to one of the conductive pads, and the fourth opening on the substrate is located in the orthographic projection of the corresponding conductive pad on the substrate.

[0034] Optionally, the display substrate further includes a first wiring pattern and a second insulating layer located between the plurality of conductive pads and the substrate. The first wiring pattern and the second insulating layer are stacked in a direction away from the substrate. The second insulating layer has a via. The orthographic projection of the via on the substrate and the orthographic projection of the first wiring pattern on the substrate at least partially overlap.

[0035] The display substrate further includes a second trace pattern that is located on the same layer as the plurality of conductive pads and electrically connected to them. The second trace pattern is electrically connected to the first trace pattern through the via.

[0036] The edge of the orthographic projection of the first opening on the substrate is offset from the edge of the orthographic projection of the via on the substrate.

[0037] According to another aspect of this application, a display device is provided, the display device including the display substrate described above.

[0038] The beneficial effects of the technical solutions provided in this application include at least the following:

[0039] A display substrate is provided, comprising a substrate, a plurality of conductive pads, a first organic insulating layer, and a first inorganic insulating layer. The first organic insulating layer has a first opening corresponding to at least one conductive pad, and a second organic insulating layer has a second opening corresponding to a conductive pad. The orthographic projection of at least one conductive pad onto the substrate lies within the orthographic projection of the corresponding first opening onto the substrate, and the orthographic projection of the second opening onto the substrate lies within the orthographic projection of the corresponding conductive pad onto the substrate. Thus, compared to related technologies where the orthographic projection of the first opening onto the substrate lies within the orthographic projection of the corresponding conductive pad onto the substrate, the distance between the edges of the first and second openings in this embodiment is larger. This increases the distance between the pad areas of the first organic insulating layer and the exposed conductive pads of the second opening, preventing the first organic insulating layer from affecting the metal plating on the pad areas of the exposed conductive pads of the second opening. This solves the problem of low yield in related technologies and improves the yield of the display substrate. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a display substrate.

[0042] Figure 2 yes Figure 1 A schematic diagram showing the coverage area of ​​the first organic insulating layer in the display substrate;

[0043] Figure 3 yes Figure 1The diagram shows a cross-sectional view of the display substrate along the A1-A2 position.

[0044] Figure 4 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this application;

[0045] Figure 5 yes Figure 4 The diagram shows the positional relationship between the first organic insulating layer and multiple conductive pads in the display substrate.

[0046] Figure 6 yes Figure 4 The diagram shows a cross-sectional view of the display substrate along the B1-B2 position.

[0047] Figure 7 This is a schematic diagram of another display substrate structure provided in an embodiment of this application;

[0048] Figure 8 yes Figure 7 The diagram shows a cross-sectional view of the display substrate along the C1-C2 position.

[0049] Figure 9 This is a schematic diagram of another display substrate structure provided in an embodiment of this application;

[0050] Figure 10 This is a schematic diagram of another display substrate structure provided in an embodiment of this application;

[0051] Figure 11 This is another display substrate provided in the embodiments of this application;

[0052] Figure 12 This is another display substrate provided in the embodiments of this application;

[0053] Figure 13 This is another display substrate provided in the embodiments of this application;

[0054] Figure 14 yes Figure 13 The diagram shows a cross-sectional view of the display substrate along the D1-D2 position;

[0055] Figure 15 This is a flowchart of a method for manufacturing a display substrate provided in an embodiment of this application.

[0056] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0058] Figure 1 This is a schematic diagram of the structure of a display substrate 10. Figure 2 yes Figure 1 A schematic diagram showing the coverage area of ​​the first organic insulating layer 13 in the display substrate 10. Figure 3 yes Figure 1 The cross-sectional structural diagram of the display substrate 10 along position A1-A2 shown is for reference only. Figure 1 , Figure 2 and Figure 3 The display substrate 10 includes a substrate 11, a plurality of conductive pads 12, a first organic insulating layer 13, and a first inorganic insulating layer 14. The plurality of conductive pads 12, the first organic insulating layer 13, and the first inorganic insulating layer 14 are stacked on the substrate 11 in a direction away from the substrate 11. The plurality of conductive pads 12 include a plurality of first conductive pads for connecting light-emitting devices and a plurality of second conductive pads for connecting driver chips.

[0059] in, Figure 2 Only the positional relationship between the first organic insulating layer 13 and the plurality of conductive pads 12 is shown, by Figure 1 and Figure 2 It can be seen that multiple second openings 141 can correspond one-to-one with multiple conductive pads 12, and multiple first openings 131 can also correspond one-to-one with multiple conductive pads 12.

[0060] It should be noted that after the first inorganic insulating layer 14 is formed on the display substrate, a subsequent gold plating process may be included. During the gold plating process, the first organic insulating layer 13 exposed by the first inorganic insulating layer 14 can absorb the gold plating solution in the gold plating process and generate tiny bubbles in the gold plating solution. These tiny bubbles will cause the metal plating layer deposited by the gold plating solution on the pad area of ​​the conductive pad 12 to be incomplete, that is, the metal plating layer cannot cover the pad area exposed by the first inorganic insulating layer 14.

[0061] This results in poor integrity of the metal plating layer, leading to a low yield of multiple pads in the display substrate 10. The light-emitting device or driving chip cannot achieve a good electrical connection with the display substrate 10, resulting in a low yield of the display substrate 10.

[0062] Figure 4 This is a schematic diagram of the structure of a display substrate 20 provided in an embodiment of this application. Figure 5 yes Figure 4 The diagram shows the positional relationship between the first organic insulating layer 203 and the plurality of conductive pads 202 in the display substrate 20. Figure 6 yes Figure 4The diagram shows a cross-sectional view of the display substrate 20 along the B1-B2 position. The display substrate 20 may include: a substrate 201, a plurality of conductive pads 202, a first organic insulating layer 203, and a first inorganic insulating layer 204.

[0063] Multiple conductive pads 202 can be located on a substrate 201, and a first organic insulating layer 203 can be located on the substrate 201 on which the conductive pads 202 are disposed. The first organic insulating layer 203 can have multiple first openings 2031, and the first openings 2031 can penetrate the first organic insulating layer 203. Each first opening 2031 can correspond to at least one conductive pad 202, and the orthographic projection of at least one conductive pad 202 on the substrate 201 can lie within the orthographic projection of the corresponding first opening 2031 on the substrate 201. Figure 2 As shown, a first opening 2031 may have one or more conductive pads 202 projected onto the substrate 201 within its orthogonal projection onto the substrate 201, and one or more conductive pads 202 may be exposed in a first opening 2031 on the first organic insulating layer 203.

[0064] The first inorganic insulating layer 204 can be located on the side of the first organic insulating layer 203 facing away from the substrate 201. The first inorganic insulating layer 204 can have multiple second openings 2041, which can correspond to conductive pads 202. The orthographic projection of the second opening 2041 on the substrate 201 can be located within the orthographic projection of the corresponding conductive pad 202 on the substrate 201. The multiple second openings 2041 can correspond one-to-one with multiple conductive pads 202. A portion of a conductive pad 202 can be exposed in one of the second openings 2041 on the first inorganic insulating layer 204. This portion of the pad can be referred to as the pad region 202a.

[0065] It should be noted that during the manufacturing process of the display substrate 20, a conductive anti-oxidation layer can be formed on the substrate 201 on which the first inorganic insulating layer 204 is formed by a metal plating process. This conductive anti-oxidation layer can be a metal plating layer on the conductive pad 202. Compared with the related art where the orthographic projection of the first opening 2031 on the substrate 201 is located within the orthographic projection of the corresponding conductive pad 202 on the substrate 201, the embodiment of this application can increase the distance between the first opening 2031 and the second opening 2041. In this way, the distance between the first organic insulating layer 203 and the pad area 202a of the conductive pad 202 exposed by the second opening 2041 can also be increased, which can improve the coverage effect of the first organic insulating layer 203 on the first inorganic insulating layer 204. This can avoid the problem of missing metal plating on the pad area 202a of the conductive pad 202 caused by the first organic insulating layer 203 exposed by the first inorganic insulating layer 204 coming into contact with the gold plating solution during the manufacturing process of the display substrate 20. This can improve the yield of multiple pads in the display substrate 20. The pad can refer to the pad area 202a covered by the conductive anti-oxidation layer. The pad can be used to bond light-emitting devices or driver chips.

[0066] In summary, this application provides a display substrate comprising a substrate, a plurality of conductive pads, a first organic insulating layer, and a first inorganic insulating layer. The first organic insulating layer has a first opening corresponding to at least one conductive pad, and the second organic insulating layer has a second opening corresponding to a conductive pad. Furthermore, the orthographic projection of at least one conductive pad onto the substrate lies within the orthographic projection of the corresponding first opening onto the substrate, and the orthographic projection of the second opening onto the substrate lies within the orthographic projection of the corresponding conductive pad onto the substrate. Thus, compared to related technologies where the orthographic projection of the first opening onto the substrate lies within the orthographic projection of the corresponding conductive pad onto the substrate, the distance between the edges of the first and second openings in this application is larger. This increases the distance between the pad areas of the first organic insulating layer and the exposed conductive pads of the second opening, preventing the first organic insulating layer from affecting the metal plating on the pad areas of the exposed conductive pads of the second opening. This addresses the low yield problem of display substrates in related technologies and improves the overall yield of the display substrate.

[0067] Optionally, such as Figure 5As shown, the display substrate 20 may further include a second wiring pattern 213 that is located on the same layer as and electrically connected to the plurality of conductive pads 202. The plurality of conductive pads 202 and the second wiring pattern 213 are located on the side of the first organic insulating layer 203 near the substrate 201. The second wiring pattern 213 may include a plurality of second signal lines 2131. It is understood that the conductive pads 202 and the second signal lines 2131 that are in direct contact with them may be an integral structure, or the conductive pads 202 and the second wiring pattern 213 may be made of the same material. In some embodiments, the conductive pads 202 may also be an integral structure with the first wiring pattern 209, or the conductive pads 202 and the first wiring pattern 209 may be made of the same material.

[0068] It should be noted that, due to the second opening ( Figure 5 The orthographic projection of the conductive pad 202 on the substrate 201 (not shown) is located in the orthographic projection of the conductive pad 202 on the substrate 201. Therefore, the second opening will not expose the second signal line 2131, so that the second signal line 2131 is protected by the first inorganic insulating layer.

[0069] Optionally, Figure 7 This is a schematic diagram of another display substrate 20 provided in an embodiment of this application. Figure 8 yes Figure 7 Please refer to the cross-sectional structural diagram of the display substrate 20 along the C1-C2 position shown. Figure 7 and Figure 8 The conductive pad 202 can be exposed from the first organic insulating layer 203 through the corresponding first opening 2031, and the conductive pad 202 has a top surface and a bottom surface, with the top surface located on the side of the bottom surface away from the substrate 201. The top surface of the conductive pad 202 can be exposed from the first inorganic insulating layer 204 through the corresponding second opening 2041. The area of ​​the conductive pad 202 exposed through the second opening 2041 can be the pad area 202a.

[0070] The display substrate 20 may further include a conductive anti-oxidation layer 205. The conductive anti-oxidation layer 205 may be located on the substrate 201 on which the first inorganic insulating layer 204 is disposed. The orthographic projection of the conductive anti-oxidation layer 205 on the substrate 201 may be located in the orthographic projection of the second opening 2041 on the substrate 201. The conductive anti-oxidation layer 205 covers the pad area 202a in the conductive pad 202 away from the surface of the substrate 201. The pad area 202a is the area of ​​the conductive pad 202 exposed at the second opening 2041, that is, the area of ​​the conductive pad 202 exposed at the second opening 2041 covered by the conductive anti-oxidation layer 205. The conductive anti-oxidation layer 205 may include a metal plating layer on the top surface of the conductive pad 202 exposed at the second opening 2041. The material of the conductive anti-oxidation layer 205 may include at least one of nickel (Ni), gold (Au), and titanium (Ti). The material of the conductive pad 202 may include at least one of copper (Cu) and molybdenum-niobium alloy (MoNb).

[0071] The conductive anti-oxidation layer 205 formed by the electroless gold process can have a crystalline structure. This crystalline structure is easier to solder than the surface of the conductive pad 202, allowing for a more stable electrical connection between the conductive pad 202 and the pins of the light-emitting device or the driver chip. Furthermore, the material of the conductive anti-oxidation layer 205 is chemically more stable than the material of the conductive pad 202, protecting the conductive pad 202 and preventing oxidation.

[0072] In one exemplary embodiment, a larger display device can be assembled by splicing together multiple smaller display devices to improve product reliability and reduce transportation and maintenance costs. Because the front side (the side containing the display surface) of the display device has a bonding area, the bezel of the display device is relatively wide, and the resulting splicing gaps can affect the optical uniformity of the large-size display device. Therefore, side traces can be used to connect the traces located on the display surface side of the display device to a circuit board (e.g., a flexible circuit board) located on the non-display surface side of the display substrate, thereby reducing the bezel size of the smaller display devices and decreasing the spacing between adjacent smaller display devices.

[0073] In related technologies, during the manufacturing process of the display substrate 10, there are process steps involving flipping or moving the display substrate 10. For example, the display substrate 10 has a front and a back side. First, conductive pads 12, a first organic insulating layer 13, and a first inorganic insulating layer 14 are processed on the front side of the display substrate 10. Then, the display substrate 10 is flipped to perform the routing process on the back side. Next, a metallization process is performed on the conductive pads 12 on the display substrate 10 to form a metal plating layer on the surface of the pad area 202a of the conductive pads 12, thereby ensuring good solderability and electrical performance of the formed pads. However, during the back side routing process, the film layer on the front side of the display substrate 10 will directly contact the production equipment, potentially causing scratches on a portion of the first inorganic insulating layer 14 on the front side. This prevents the first inorganic insulating layer 14 in that portion from completely covering the underlying first organic insulating layer 13.

[0074] It should be noted that after forming the first inorganic insulating layer 14 on the display substrate, a subsequent electroless gold plating process may be included. This process forms a conductive anti-oxidation layer on the substrate 11 where the first inorganic insulating layer 14 is formed. This conductive anti-oxidation layer can be a metal plating layer on the pad area of ​​the conductive pad 12. Electroless gold plating, also known as immersion gold plating, is a gold plating process that uses a chemical reaction in a solution to deposit metal onto the surface of the pad area of ​​the conductive pad 12. The solution used in this process can be called an electroless gold plating solution.

[0075] During the electroless gold process, the first organic insulating layer 13 exposed by the first inorganic insulating layer 14 can absorb the electroless gold solution in the electroless gold process and generate tiny bubbles in the electroless gold solution. These tiny bubbles will cause the metal plating layer deposited by the electroless gold solution on the pad area of ​​the conductive pad 12 to be incomplete, that is, the metal plating layer cannot cover the pad area on the conductive pad 12 exposed by the first inorganic insulating layer 14.

[0076] Alternatively, due to process fluctuations during the manufacturing of the display substrate 10, the expected coverage effect between the layers cannot be achieved. For example, the first inorganic insulating layer 14 may not completely cover the first organic insulating layer 13, causing the first organic insulating layer 13 to affect the metal plating.

[0077] Therefore, the integrity of the metal plating layer in the related technology is poor. In the manufacturing process, the conductive anti-oxidation layer 205 in this embodiment is not easily affected by the first organic insulating layer 203. Therefore, the conductive anti-oxidation layer 205 can completely cover the pad area 202a exposed at the second opening 2041 of the conductive pad 202, which can improve the yield of the display substrate 20.

[0078] Optionally, such as Figure 4 As shown, the first opening 2031 corresponds to at least one second opening 2041. The orthographic projection of the at least one second opening 2041 on the substrate 201 lies within the orthographic projection of the corresponding first opening 2031 on the substrate 201. The shortest distance L1 between the edge of the orthographic projection of the first opening 2031 on the substrate 201 and the edge of the orthographic projection of the at least one second opening 2041 on the substrate 201 ranges from 20 micrometers to 80 micrometers. Further, the shortest distance L1 between the edge of the orthographic projection of the first opening 2031 on the substrate 201 and the edge of the orthographic projection of the corresponding at least one second opening 2041 on the substrate 201 ranges from 20 micrometers to 80 micrometers. For example, the shortest distance L1 between the edge of the orthographic projection of the first opening 2031 on the substrate 201 and the edge of the orthographic projection of the corresponding at least one second opening 2041 on the substrate 201 is 50 micrometers.

[0079] Compared to related technologies where the shortest distance between the edge of the orthographic projection of the first opening 2031 onto the substrate 201 and the edge of the orthographic projection of the corresponding second opening 2041 onto the substrate 201 ranges from 2 micrometers to 5 micrometers, the distance between the first opening 2031 and the second opening 2041 in this embodiment is larger. This means the distance between the pad areas 202a of the conductive pad 202 exposed by the first organic insulating layer 203 and the second opening 2041 is larger, which improves the coverage effect of the first organic insulating layer 203 on the first inorganic insulating layer 204. This avoids the problem of the first organic insulating layer 203 exposed by the first inorganic insulating layer 204 coming into contact with the gold plating solution during the manufacturing process of the display substrate 20, causing missing metal plating on the pad areas 202a of the conductive pad 202, and thus improves the yield of multiple pads in the display substrate 20.

[0080] Even if the first inorganic insulating layer 204 in this embodiment of the application has scratches during the manufacturing process of the display substrate 20, exposing part of the first organic insulating layer 203, the distance between the edge of the first organic insulating layer 203 (i.e., the edge of the first opening 2031) and the exposed pad area 202a of the conductive pad 202 at the second opening 2041 is relatively large. This results in a smaller impact of the first organic insulating layer 203 on the gold plating solution on the exposed pad area 202a of the conductive pad 202 at the second opening 2041. This can further avoid the problem of the first organic insulating layer 203 exposed by the first inorganic insulating layer 204 coming into contact with the gold plating solution during the manufacturing process of the display substrate 20, causing the metal plating layer on the pad area 202a of the conductive pad 202 to be missing. This can improve the yield of multiple pads in the display substrate 20.

[0081] Optionally, Figure 9This is a schematic diagram of another display substrate 20 provided in an embodiment of this application. Please refer to it. Figure 9 The shortest distance L2 between two adjacent conductive pads 202 is greater than or equal to a first preset value, and the first opening 2031 corresponds to a conductive pad 202. That is, when the arrangement of multiple conductive pads 202 on the display substrate 20 is relatively sparse, the first organic insulating layer 203 can expose a conductive pad 202 through a first opening 2031, so that adjacent conductive pads 202 do not interfere with each other.

[0082] Optionally, the range of the first preset value can be 30 micrometers to 60 micrometers. Within this range, the plurality of first openings 2031 on the first organic insulating layer 203 can correspond one-to-one with the plurality of conductive pads 202.

[0083] In one exemplary embodiment, when the shortest distance L3 between two adjacent second openings is greater than 70 micrometers, the first opening 2031 corresponds to a conductive pad 202.

[0084] The distance L4 between the edge of the orthographic projection of the first opening 2031 on the substrate 201 and at least a portion of the edge of the orthographic projection of the corresponding conductive pad 202 on the substrate 201 can be greater than 7 micrometers.

[0085] Optionally, such as Figure 4 As shown, the shortest distance L2 between two adjacent conductive pads 202 is less than a first preset value, and the first opening 2031 corresponds to multiple conductive pads 202. That is, when the multiple conductive pads 202 on the display substrate 20 are arranged relatively densely, the first organic insulating layer 203 can expose multiple conductive pads 202 through a first opening 2031, thereby reducing the difficulty of the manufacturing process of the display substrate 20.

[0086] It should be noted that there are process fluctuations in the manufacturing process of the display substrate 20. When designing multiple film layers on the display substrate 20, the encapsulation relationship between the film layers needs to be considered. That is, the distance between the edges of adjacent film layers is greater than a preset value to avoid poor uniformity at the edges of adjacent film layers.

[0087] For example, such as Figure 3 As shown, Figure 3 The film layer at the conductive pad 12 includes a conductive pad 12, a first organic insulating layer 13 and a first inorganic insulating layer 14 stacked in a direction away from the substrate 11. The wrapping relationship of each film layer is as follows: the edge of the first opening 131 on the first organic insulating layer 13 covers the conductive pad 12, and the edge of the second opening 141 on the first inorganic insulating layer 14 is located in the first opening 131. That is, the edge of the first opening 131 can wrap the edge of the second opening 141.

[0088] When the process fluctuation range during the manufacturing of the display substrate is 5 micrometers, the design value of the distance between the edges of multiple film layers on the display substrate 10 can satisfy the following relationship: the distance L5 between the edge of the first opening 131 of the first organic insulating layer 13 projected onto the substrate 11 and the edge of the corresponding conductive pad 12 projected onto the substrate 11 can be greater than 7 micrometers. In this way, the situation where part of the edge of the first opening 131 is located outside the conductive pad 12 and another part of the edge is located on the conductive pad 12 can be avoided, which can make the uniformity of the organic insulating layer on the display substrate better.

[0089] The distance L6 between the edge of the orthographic projection of the second opening 141 of the first inorganic insulating layer 14 onto the substrate 11 and the edge of the orthographic projection of the first opening 131 of the first organic insulating layer 13 onto the substrate 11 can be greater than 9 micrometers. This avoids the situation where the first inorganic insulating layer 14 covers the first organic insulating layer 13 at some edges but not at others, resulting in better uniformity of the film layers on the display substrate. Therefore, with good uniformity of the film layers at the conductive pad 12, the distance between the edge of the orthographic projection of the second opening 141 onto the substrate 11 and the edge of the orthographic projection of the conductive pad 12 onto the substrate 11 can be greater than 16 micrometers.

[0090] However, by Figure 1 It is known that in the related technology, the distance L7 between the edges of two adjacent conductive pads 12 in the first direction f1 is 10.5 micrometers, and the distance (L5+L6) between the edge of the orthographic projection of the second opening 141 on the substrate 11 and the edge of the orthographic projection of the conductive pad 12 on the substrate 11 is 11 micrometers. Therefore, the distance between the edges of two adjacent second openings 141 in the first direction is 32.5 micrometers (11×2+10.5=32.5).

[0091] If the size of the conductive pad 12 is adjusted so that the distance between the edge of the conductive pad 12 and the edge of the second opening 141 is 16 micrometers, the distance between the edges of two adjacent conductive pads 12 in the first direction is 0.5 micrometers. This makes the distance between the two conductive pads 12 relatively close, which makes it easier for short circuits to occur between adjacent conductive pads 12.

[0092] Alternatively, in an optional embodiment, the distance between two adjacent conductive pads 12 is greater than 14 micrometers, such as 18 micrometers. If the first opening 131 is enlarged so that its orthographic projection on the substrate 11 is outside the orthographic projection of the corresponding conductive pad 12 on the substrate 11, and the distance between the edge of the orthographic projection of the first opening 131 on the substrate 11 and the edge of the orthographic projection of the corresponding conductive pad 12 on the substrate 11 is greater than 7 micrometers, then the shortest distance between the edge of the orthographic projection of the first opening 131 on the substrate 11 and the edge of the orthographic projection of the second opening 141 on the substrate 11 can be greater than 9 micrometers. Because the distance between the first openings 131 corresponding to two adjacent conductive pads 12 is small, the manufacturing of the first organic insulating layer 13 is more difficult, resulting in a lower yield of the display substrate.

[0093] Therefore, in this embodiment of the application, by having a first opening 2031 corresponding to multiple conductive pads 202, it is possible to improve the uniformity of multiple film layers on the display substrate, and at the same time, increase the distance between the pad area 202a of the conductive pad 202 exposed by the first organic insulating layer 203 and the second opening 2041, thereby improving the coverage effect of the first organic insulating layer 203 on the first inorganic insulating layer 204.

[0094] Optionally, Figure 10 This is a schematic diagram of another display substrate provided in an embodiment of this application. Please refer to it. Figure 10 The multiple conductive pads 202 may include multiple first conductive pads 2021 and multiple second conductive pads 2022. Every two first conductive pads 2021 constitute a first conductive pad group 2021a, and one first conductive pad group is used to connect to a light-emitting device. Every N second conductive pads 2022 constitute a second conductive pad group 2022a, and one second conductive pad group 2022a is used to connect to a driver chip. Here, N is a positive integer greater than or equal to 2; for example, N is 6.

[0095] The first opening 2031 may include a first sub-opening 20311 and a second sub-opening 20312. The first sub-opening 20311 corresponds to a first conductive pad group 2021a, and the second sub-opening 20312 corresponds to a second conductive pad group 2022a.

[0096] Since the distance between two adjacent conductive pads 202 of the plurality of first conductive pads 2021 in the second direction f2 is greater than the distance between two adjacent conductive pads 202 of the plurality of first conductive pads 2021 in the first direction f1, for example, the distance between two adjacent second openings 2041 of the plurality of second openings 2041 in the second direction f2 can be 86 micrometers, and the distance L2 between two adjacent conductive pads 202 of the plurality of conductive pads 202 in the second direction f2 can be 58 micrometers, therefore, the first organic insulating layer 203 can be located in the region between two adjacent second openings 2041 in the second direction f2, and in the second direction f2, the distance between the edge of the orthographic projection of the first opening 2031 on the substrate 201 and the orthographic projection of the corresponding two conductive pads 202 on the substrate 201 can be greater than 7 micrometers. For example, the distance between two adjacent second openings 2041 in the first direction f1 can be 46 micrometers, and the distance L8 between two adjacent first conductive pads 2021 in the first direction f1 can be 18 micrometers. Therefore, the first organic insulating layer 203 may not be located in the region between two adjacent conductive pads 202 in the first direction f1 to avoid poor uniformity of the first organic insulating layer 203.

[0097] Similarly, compared to multiple first conductive pads 2021, in a more closely arranged set of multiple second conductive pads 2022, six second conductive pads 2022 can correspond to one first opening 2031, which can increase the distance between the first opening 2031 and the second opening 2041, thereby increasing the distance between the first organic insulating layer 203 and the conductive pads 202 exposed by the second opening 2041. This can also reduce the manufacturing difficulty of the display substrate 20, improve the uniformity of the first organic insulating layer 203, and thus improve the yield of the display substrate 20.

[0098] For example, each light-emitting device may include two pins, each driving chip may include six pins, and the two pins of each light-emitting device may be electrically connected to two first conductive pads 2021 through two second openings 2041 through the first inorganic insulating layer 204 and a first sub-opening 20311 through the first organic insulating layer 203.

[0099] The six pins of each driver chip can be connected to the six second conductive pads 2022 through the six second openings 2041 penetrating the first inorganic insulating layer 204 and the second sub-opening 20312 penetrating the first organic insulating layer 203, thereby controlling the light-emitting device to emit light through the driver chip.

[0100] Optionally, such as Figure 4As shown, the multiple conductive pads 202 may include multiple first conductive pads 2021 and multiple second conductive pads 2022. Every two first conductive pads 2021 constitute a first conductive pad group (not shown in the figure), and one first conductive pad group is used to connect to a light-emitting device. Every N second conductive pads 2022 constitute a second conductive pad group (not shown in the figure), and one second conductive pad group is used to connect to a driver chip. Here, N is a positive integer greater than or equal to 2; for example, N is 6.

[0101] The first opening 2031 may include a first sub-opening 20311 and a second sub-opening 20312. The first sub-opening 20311 may correspond to at least three adjacent first conductive pad groups, and the second sub-opening 20312 may correspond to one second conductive pad group. It should be noted that... Figure 4 The division of the first conductive pad group and the second conductive pad group in the middle and Figure 10 The division of the first conductive pad group and the second conductive pad group is the same.

[0102] For example, the plurality of light-emitting devices may include a blue light-emitting device for emitting blue light, a green light-emitting device for emitting green light, and a red light-emitting device for emitting red light. Each light-emitting device may include two pins, and the two pins of each light-emitting device may be electrically connected to the first conductive pad 2021 through two second openings 2041 through the first inorganic insulating layer 204. The six pins of the three light-emitting devices may be electrically connected to the first conductive pad 2021 through a first sub-opening 20311 through the first organic insulating layer 203.

[0103] Each driver chip may include six pins, and the six pins of each driver chip may be connected to six second conductive pads 2022 through six second openings 2041 through the first inorganic insulating layer 204 and one second sub-opening 20312 through the first organic insulating layer 203, thereby controlling the light-emitting device to emit light through the driver chip.

[0104] Optionally, such as Figure 4 As shown, the distance between adjacent first sub-openings 20311 and second sub-openings 20312 ranges from 20 micrometers to 100 micrometers. That is, the distance L9 between the first sub-opening 20311 corresponding to the first conductive pad group and the second sub-opening 20312 corresponding to the second conductive pad group can be greater than 20 micrometers to reduce the influence between multiple first conductive pads 2021 and multiple second conductive pads 2022.

[0105] Optionally, Figure 11 This is another display substrate 20 provided in the embodiments of this application; please refer to [link / reference]. Figure 11The display substrate 20 may be rectangular, and has two opposing first edges s1 and two opposing second edges s2. The display substrate 20 may also include a connection terminal 206 and side traces (not shown) located at the second edge s2, and the connection terminal 206 and the side traces are electrically connected. The connection terminal 206 may be located at the second edge s2 of the display substrate 20 and in the area exposed by the first organic insulating layer 203 and the first inorganic insulating layer 204.

[0106] The plurality of first openings 2031 may include a target first opening 2032, which is adjacent to a first edge s1, and the edge of the target first opening 2032 coincides with the edge of the first organic insulating layer 203 located at the first edge s1. The display substrate 20 can be obtained by cutting a display substrate mother plate, which may include multiple connected display substrates 20. After cutting the display substrate mother plate, individual display substrates 20 can be obtained. During the manufacturing process of the display substrate 20, a high-energy laser can be used to cut the display substrate mother plate into multiple display substrates 20.

[0107] The display substrate motherboard has a cutting area, also known as a cutting channel, and the edge of this cutting area is the edge of the first organic insulating layer 203 on each display substrate 20. When the display substrate motherboard is cut along the cutting area using a laser, the first organic insulating layer 203 at the edge of the display substrate 20 may be affected by the high energy of the laser, causing fusion and generating carbonized foreign matter, resulting in a low yield of the display substrate. Therefore, the first organic insulating layer 203 is not covered in the cutting area of ​​the display substrate motherboard. This avoids the generation of carbonized foreign matter during the cutting of the display substrate motherboard. The edge of the target first opening 2032 coincides with the edge of the first organic insulating layer 203 located at the first edge s1, meaning the target first opening 2032 and the cutting channel can be connected, simplifying the manufacturing process of the display substrate 20.

[0108] Optionally, such as Figure 11 As shown, the first organic insulating layer 203 also has a third opening 2033, which can be adjacent to the second edge s2. The side of the display substrate 20 at the second edge s2 can be used to provide side traces. These side traces can be used to connect the front traces and back traces of the display substrate 20. The side traces can connect the traces on the display surface side of the display device to the circuit board (e.g., a flexible circuit board) on the non-display surface side of the display substrate, thereby reducing the bezel size of smaller display devices and reducing the spacing between adjacent smaller display devices.

[0109] The third opening 2033 corresponds to at least one conductive pad 202, and the edge of the orthographic projection of the third opening 2033 on the substrate 201 is at least partially located outside the orthographic projection of the corresponding at least one conductive pad 202 on the substrate 201. There is a second preset distance L10 between the edge of the third opening 2033 and the edge of the first organic insulating layer 203 located at the second edge s2. Since the front and back traces can be manufactured using exposure processes during the manufacturing process of the display substrate 20, and the side traces can be manufactured using laser etching processes, a large amount of heat can be generated during laser etching of the side traces. In this embodiment, by having a second preset distance between the edge of the third opening 2033 and the edge of the first organic insulating layer 203 located at the second edge s2, a partial structure on the first organic insulating layer 203 is formed between the edge of the third opening 2033 and the edge of the first organic insulating layer 203. This partial structure can be called a barrier 207. The barrier 207 can be used to isolate the heat generated during laser etching of the side traces to avoid the heat affecting the conductive pad 202 in the third opening 2033.

[0110] Optionally, the second preset distance can be in the range of 20 micrometers to 50 micrometers. Within this range, the heat insulation effect of the baffle 207 is better. Furthermore, the third opening 2033 corresponds to at least one second opening, and the orthographic projection of the at least one second opening on the substrate 201 lies within the orthographic projection of the corresponding third opening 2033 on the substrate 201. Within this range, the impact on the distance between the edge of the orthographic projection of the third opening 2033 on the substrate 201 and the edge of the orthographic projection of the second opening on the substrate 201 is small, thus preventing the first inorganic insulating layer 204 from exposing the first organic insulating layer 203. For example, the shortest distance between the edge of the orthographic projection of the third opening 2033 on the substrate 201 and the edge of the orthographic projection of the corresponding at least one second opening on the substrate 201 can be greater than 10 micrometers.

[0111] Optionally, Figure 12 This is another display substrate 20 provided in the embodiments of this application; please refer to [link / reference]. Figure 12 The display substrate 20 also has alignment marks 208, which are used for alignment of the exposure equipment during the exposure of the pattern formed on the film layer on the display substrate 20. The first organic insulating layer 203 may also have a fourth opening 2034, which is adjacent to the alignment marks 208. The fourth opening 2034 corresponds to a conductive pad 202, and the fourth opening 2034 is located in the orthographic projection of the corresponding conductive pad 202 onto the substrate 201. The second opening ( Figure 12(Not shown in the image) and the fourth opening 2034 can also correspond one-to-one, and the orthographic projection of the second opening on the substrate 201 can be located in the orthographic projection of the fourth opening 2034 on the substrate 201. In this way, the size of the fourth opening 2034 can be made smaller, and the fourth opening 2034 can be avoided from affecting the alignment mark 208.

[0112] For example, the conductive pad 202 corresponding to the fourth opening 2034 can be the second conductive pad 2022, that is, the conductive pad 202 connected to the driver chip.

[0113] Optionally, Figure 13 This is another display substrate 20 provided in the embodiments of this application. Figure 14 yes Figure 13 Please refer to the cross-sectional structural diagram of the display substrate 20 along the C1-C2 position shown. Figure 13 and Figure 14 The display substrate 20 also includes a first wiring pattern 209 and a second insulating layer 210 located between a plurality of conductive pads 202 and a substrate 201. The first wiring pattern 209 and the second insulating layer 210 are stacked in a direction away from the substrate 201. The second insulating layer 210 has a via 2101. The orthographic projection of the via 2101 on the substrate 201 and the orthographic projection of the first wiring pattern 209 on the substrate 201 at least partially overlap.

[0114] The display substrate 20 may further include a second wiring pattern 213 located on the same layer as and electrically connected to the plurality of conductive pads 202. The second wiring pattern 213 is electrically connected to the first wiring pattern 209 through a via 2101. The display substrate may further include a buffer layer located between the first wiring pattern 209 and the display substrate 20. The first wiring pattern 209 includes a plurality of first signal lines. A second organic insulating layer is located on the side of the first wiring pattern 209 away from the substrate 201. The plurality of conductive pads 202 and the second wiring pattern 213 are located on the side of the second organic insulating layer away from the substrate 201. The second wiring pattern 213 includes a plurality of second signal lines. It is understood that the conductive pads 202 and the second wiring pattern 213 in direct contact with them may be an integral structure. In some embodiments, the conductive pads 202 may also be an integral structure with the first wiring pattern 209.

[0115] The multiple second signal lines may include multiple data signal lines Dm, multiple first positive signal lines Hm1, multiple second positive signal lines Hm2, multiple reference signal lines Vm, and multiple scan signal adapter lines extending along the second direction f2. The second wiring pattern 213 includes multiple scan signal lines Sn, which are electrically connected to the scan signal adapter lines and extend along the first direction f1. For example, in a plurality of pixels arranged in an array (e.g., each pixel includes three light-emitting devices arranged along the second direction f2, and a driver chip for providing signals to the three light-emitting devices), each row of pixels is electrically connected to the same scan signal line Sn, and each column of pixels is electrically connected to a data signal line Dm, a reference signal line Vm, a first positive signal line Hm1, and a second positive signal line Hm2, so as to achieve reasonable wiring and transmit corresponding signals to the pixels through multiple signal lines.

[0116] The edge of the orthographic projection of the first opening 2031 on the substrate 201 is offset from the edge of the orthographic projection of the via 2101 on the substrate 201. This has two advantages: firstly, the via 2101 can be protected by the first organic insulating layer 203; secondly, it can prevent the first inorganic insulating layer 204 from having excessive undulations at the via 2101, which could lead to breakage of the first inorganic insulating layer 204.

[0117] For example, the shortest distance between the edge of the orthographic projection of the via 2101 on the substrate 201 and the edge of the orthographic projection of the first opening 2031 on the substrate is greater than or equal to 10 micrometers.

[0118] Optionally, such as Figure 14 As shown, the second insulating layer 210 may include a fourth inorganic insulating layer 2103, a second organic insulating layer 2102 and a third inorganic insulating layer 2101 stacked together. The display substrate may also include a second inorganic insulating layer 211 located on the side of the first organic insulating layer 203 facing the substrate 201. The second inorganic insulating layer 211 may have an opening that overlaps with the second opening position on the first inorganic insulating layer 204. The second inorganic insulating layer 211 and the first inorganic insulating layer 204 can be formed by a single patterning process.

[0119] The display substrate may further include a buffer layer 212 located on the side of the first trace pattern 209 facing the substrate 201, and a third trace pattern 214, a trace protection layer 215, and a fifth inorganic insulating layer 216 stacked on the side of the substrate 201 away from the buffer layer 212 and in a direction away from the substrate 201. The third trace pattern 214 may be a line connecting the side traces and the drive control device on the back of the display substrate. The trace protection layer 215 may be made of indium tin oxide to prevent the third trace pattern 214 from being corroded by moisture. A back mark 217 may also be included between the substrate 210 and the fifth inorganic insulating layer 216, which can be used as an alignment mark.

[0120] In summary, this application provides a display substrate comprising a substrate, a plurality of conductive pads, a first organic insulating layer, and a first inorganic insulating layer. The first organic insulating layer has a first opening corresponding to at least one conductive pad, and the second organic insulating layer has a second opening corresponding to a conductive pad. Furthermore, the orthographic projection of at least one conductive pad onto the substrate lies within the orthographic projection of the corresponding first opening onto the substrate, and the orthographic projection of the second opening onto the substrate lies within the orthographic projection of the corresponding conductive pad onto the substrate. Thus, compared to related technologies where the orthographic projection of the first opening onto the substrate lies within the orthographic projection of the corresponding conductive pad onto the substrate, the distance between the edges of the first and second openings in this application is larger. This increases the distance between the pad areas of the first organic insulating layer and the exposed conductive pads of the second opening, preventing the first organic insulating layer from affecting the metal plating on the pad areas of the exposed conductive pads of the second opening. This addresses the low yield problem of display substrates in related technologies and improves the overall yield of the display substrate.

[0121] Figure 15 This is a flowchart illustrating a method for manufacturing a display substrate according to an embodiment of this application. This method can manufacture the display substrate provided in the above embodiment. For example, it can be used to prepare the display substrate described in the above embodiment. Figure 14 The display substrate 20 shown is for reference. Figure 15 The method may include:

[0122] Step 301: Obtain the substrate.

[0123] Optionally, the substrate can be a flexible substrate, which can be made of a flexible material (e.g., polyimide, PI). Alternatively, the substrate can be a glass substrate. Or, the substrate can be an opaque substrate.

[0124] Step 302: Form a buffer layer on the first surface of the substrate.

[0125] After the substrate is cleaned using standard methods, a buffer layer can be formed on the substrate using a sputter deposition process. The thickness of the buffer layer can range from 1500 angstroms to 2600 angstroms, and its material can include at least one of silicon oxide (SiOx) or nitrogen oxide (SiNx).

[0126] Step 303: Form a first wiring pattern on the substrate on which the buffer layer is formed.

[0127] A first metal material thin film can be formed on the side of the buffer layer away from the substrate using sputtering deposition or atomic layer deposition (ALD) processes. This first metal material thin film is then patterned to obtain a first wiring pattern. The thickness of the first wiring pattern can range from 2000 angstroms to 3000 angstroms, and its material can include at least one metal such as copper (Cu) and molybdenum-niobium alloy (MoNb). Alternatively, the first wiring pattern can be a stacked structure of molybdenum-niobium alloy, copper, and molybdenum-niobium alloy (MoNb / Cu / MoNb).

[0128] The patterning process may include at least some of the steps in the process flow such as cleaning, coating, baking, exposure, development, hard baking, etching, and stripping.

[0129] Step 304: Form a fourth inorganic insulating layer on the substrate on which the first wiring pattern is formed.

[0130] A fourth inorganic insulating layer can be formed on a substrate using either sputtering or chemical vapor deposition (CVD) processes. The thickness of this fourth inorganic insulating layer can range from 2200 angstroms to 2600 angstroms, and its material can include at least one of silicon oxide (SiOx) or nitrous oxide (SiNx). The fourth inorganic insulating layer has a first via, and the orthographic projection of the first via onto the substrate overlaps with the orthographic projection of the first wiring pattern onto the substrate.

[0131] Step 305: Form a second organic insulating layer on the substrate on which the fourth inorganic insulating layer has been formed.

[0132] A second organic insulating layer can be formed on the side of the fourth inorganic insulating layer away from the substrate through processes such as coating, photo exposure, and development. The thickness of the second organic insulating layer can range from 3.5 micrometers to 7.5 micrometers. The second organic insulating layer has a second via, the orthographic projection of the second via on the substrate overlaps with the orthographic projection of the first wiring pattern on the substrate, and the second via can communicate with the first via.

[0133] Optionally, the material of the second organic insulating layer may include at least one of polyimide, optically transparent adhesive and polyamide.

[0134] Step 306: Form a third inorganic insulating layer on the substrate on which the second organic insulating layer has been formed.

[0135] A third inorganic insulating layer can be formed on the substrate using either sputtering or chemical vapor deposition (CVD) processes. The thickness of this third inorganic insulating layer can range from 1200 angstroms to 3300 angstroms, and its material can include at least one of silicon oxide (SiOx) or nitrogen oxide (SiNx). The third inorganic insulating layer has a third via, the orthographic projection of which overlaps with the orthographic projection of the first wiring pattern on the substrate, and the third via can communicate with both the first and second vias.

[0136] In one optional embodiment, the formation process of the above three vias may include: first forming a second via on a second organic insulating layer, and then etching away the third and fourth inorganic insulating layers at the second via using a dry etching process, so as to form the first and third vias in a single etching process.

[0137] Step 307: Form multiple conductive pads and multiple second wiring patterns on a substrate on which a third inorganic insulating layer has been formed.

[0138] A second metal material thin film can be formed on the side of the third inorganic insulating layer away from the substrate using sputtering deposition or atomic layer deposition (ALD) processes. This second metal material thin film is then patterned to obtain a second wiring pattern and multiple conductive pads. The thickness of the first wiring pattern and conductive pads can range from 0.8 micrometers to 1 micrometer; for example, the thickness can be 0.9 micrometers. The material can include at least one metal such as copper (Cu) and molybdenum-niobium alloy (MoNb). Alternatively, the first wiring pattern and conductive pads can be a stacked structure of molybdenum-niobium alloy, copper, and molybdenum-niobium alloy (MoNb / Cu / MoNb).

[0139] Step 308: Form a second inorganic insulating layer on a substrate having multiple conductive pads and multiple second wiring patterns.

[0140] A second inorganic insulating layer can be formed on a substrate using either sputtering or chemical vapor deposition (CVD) processes. The thickness of this second inorganic insulating layer can range from 1200 angstroms to 2600 angstroms, and its material can include at least one of silicon oxide (SiOx) or nitrogen oxide (SiNx). The second inorganic insulating layer has a fifth opening, the third opening of which penetrates the second inorganic insulating layer, and the orthographic projection of the fifth opening onto the substrate lies within the orthographic projection of the conductive pad onto the substrate.

[0141] Step 309: Form a first organic insulating layer on the substrate on which the second inorganic insulating layer is formed.

[0142] A first organic insulating layer can be formed on the side of the second inorganic insulating layer away from the substrate through processes such as coating, photo exposure, and development. The thickness of the first organic insulating layer can range from 1.5 micrometers to 2.5 micrometers. The first organic insulating layer has a first opening that penetrates the first organic insulating layer, and the first organic insulating layer can correspond to at least one conductive pad, meaning that the orthographic projection of at least one conductive pad on the substrate lies within the orthographic projection of the first opening on the substrate. Furthermore, the orthographic projection of at least one third opening on the substrate lies within the orthographic projection of the first opening on the substrate. Optionally, the material of the first organic insulating layer can include at least one of polyimide, optically transparent adhesive, and polyamide.

[0143] Step 310: Form a first inorganic insulating film on a substrate on which a first organic insulating layer has been formed.

[0144] A first inorganic insulating film can be formed on a substrate using either sputtering or chemical vapor deposition (CVD) processes. The thickness of the first inorganic insulating film can range from 1200 angstroms to 3300 angstroms, and its material can include at least one of silicon oxide (SiOx) or nitrogen oxide (SiNx). In this step, the first inorganic insulating film can completely cover the film structure located beneath it.

[0145] Optionally, after forming a first inorganic insulating film on the substrate, the substrate with the first inorganic insulating film can be cut to form multiple display substrates. Then, a gold plating process can be performed on multiple pad areas (i.e., areas where conductive pads are exposed) on the substrate to prevent the pad areas from being corroded and oxidized.

[0146] Step 311: Form a back mark on the second surface of the substrate on which the first inorganic insulating film is formed.

[0147] After forming a first inorganic insulating film on the first surface of the display substrate, the display substrate can be flipped over for the first time, and a back mark (OC Mark) can be formed on the second surface of the substrate through processes such as coating, exposure, and development.

[0148] Step 312: Form a third wiring pattern on the substrate with back markings.

[0149] The third trace pattern can be formed using processes such as sputtering deposition, cleaning, coating, baking, exposure, development, hard baking, etching, and stripping. The thickness of this third trace pattern can range from 8000 angstroms to 9500 angstroms, and its material can include at least one metal such as copper (Cu) and molybdenum-niobium alloy (MoNb). Alternatively, the third trace pattern can be a stacked structure of molybdenum-niobium alloy, copper, and molybdenum-niobium alloy (MoNb / Cu / MoNb).

[0150] A trace protection layer can also be formed on the side of the third trace pattern away from the substrate. This trace protection layer can cover the third trace pattern to protect it. The material of the trace protection layer may include indium tin oxide (ITO), and the thickness of the trace protection layer can be in the range of 500 angstroms to 600 angstroms. For example, the thickness of the trace protection layer can be 520 angstroms.

[0151] Step 313: Form a fifth inorganic insulating layer on the substrate on which the third wiring pattern is formed.

[0152] A fifth inorganic insulating layer can be formed on a substrate using either sputtering or chemical vapor deposition (CVD) processes. The thickness of this fifth inorganic insulating layer can range from 5000 angstroms to 6000 angstroms, and its material can include at least one of silicon oxide (SiOx) or nitrous oxide (SiNx). The fifth inorganic insulating layer has a sixth opening, the orthographic projection of which overlaps with the orthographic projection of the third wiring pattern on the substrate. The third wiring pattern can be electrically connected through this sixth opening to side traces and structures such as flexible circuit boards.

[0153] Step 314: Etch the first inorganic insulating film to form the first inorganic insulating layer.

[0154] After forming the fifth inorganic insulating layer on the second surface of the display substrate, the display substrate can be flipped over a second time, and the first inorganic insulating layer can be formed by dry etching process.

[0155] The first inorganic insulating layer has a second opening, the orthographic projection of which onto the substrate lies in the orthographic projection of the conductive pad onto the substrate, and the first opening and the fifth opening may be located within the second opening.

[0156] In one alternative embodiment, the process of forming the above three openings may include: first forming a first opening on a first organic insulating layer, and then etching away the first inorganic insulating layer and the second inorganic insulating layer at the second opening through a dry etching process, so as to form the second opening and the fifth opening through a single etching process.

[0157] In summary, this application provides a method for manufacturing a display substrate, which includes a substrate, a plurality of conductive pads, a first organic insulating layer, and a first inorganic insulating layer. The first organic insulating layer has a first opening corresponding to at least one conductive pad, and a second organic insulating layer has a second opening corresponding to a conductive pad. Furthermore, the orthographic projection of at least one conductive pad onto the substrate lies within the orthographic projection of the corresponding first opening onto the substrate, and the orthographic projection of the second opening onto the substrate lies within the orthographic projection of the corresponding conductive pad onto the substrate. Thus, compared to related technologies where the orthographic projection of the first opening onto the substrate lies within the orthographic projection of the corresponding conductive pad onto the substrate, the distance between the edges of the first and second openings in this application is larger. This increases the distance between the first organic insulating layer and the exposed pad areas of the conductive pads, preventing the first organic insulating layer from affecting the metal plating on the exposed pad areas of the conductive pads. This solves the problem of low yield in related technologies and improves the overall yield of the display substrate.

[0158] Furthermore, this application also provides a display device, which may include the display substrate in any of the above embodiments. The light-emitting devices on the display substrate include OLED (Organic Light-Emitting Diode), Mini LED (Mini Light-Emitting Diode), Micro LED (Micro Light-Emitting Diode), etc.

[0159] Using miniature or micro-LEDs as light-emitting devices results in smaller size and smaller particles compared to traditional LEDs. Within the same screen size, the light source density per unit area is higher and the unit size of the light source is smaller. Therefore, more precise local control of the light-emitting device can be achieved, and the problem of uneven brightness of the light-emitting device will not occur. This ensures the uniformity of display brightness and thus guarantees the display quality of the display device.

[0160] In some embodiments, the display device further includes an integrated circuit chip and a flexible circuit board.

[0161] For example, an integrated circuit chip is configured to be electrically connected to a flexible circuit board. The integrated circuit chip sends control signals, which are then transmitted via the flexible circuit board to side traces and connection terminals. The connection terminals are electrically connected to multiple first signal lines in a first trace pattern. These multiple first signal lines can be electrically connected via a second trace pattern and multiple conductive pads to transmit the drive signals to the conductive pads. The conductive pads then transmit the drive signals to a light-emitting device to control the light-emitting device to emit light, thereby enabling the display device to display an image.

[0162] The display device may also include a driver chip. It is understood that multiple first signal lines in the first wiring pattern may also be electrically connected to the driver chip, enabling the driver chip to control the brightness of the light-emitting devices. Specifically, three light-emitting devices may be driven and controlled by one driver chip, or four, five, or more light-emitting devices may be driven and controlled by one driver chip; this application does not limit the scope of the embodiments.

[0163] In one alternative embodiment, the display device may include a plurality of display substrates as described in any of the above embodiments, and the plurality of display substrates in the display device are arranged in an array.

[0164] In this application, the term "at least one of A and B" merely describes the relationship between related objects, indicating that three relationships can exist. For example, "at least one of A and B" can represent: A existing alone, A and B existing simultaneously, and B existing alone. Similarly, "at least one of A, B, and C" indicates that seven relationships can exist, representing: A existing alone, B existing alone, C existing alone, A and B existing simultaneously, A and C existing simultaneously, C and B existing simultaneously, and A, B, and C existing simultaneously. Likewise, "at least one of A, B, C, and D" indicates that fifteen relationships can exist, representing: A existing alone, B existing alone, C existing alone, D existing alone, A and B existing simultaneously, A and C existing simultaneously, A and D existing simultaneously, C and B existing simultaneously, D and B existing simultaneously, C and D existing simultaneously, A, B, and C existing simultaneously, A, B, and D existing simultaneously, A, C, and D existing simultaneously, and A, B, C, and D existing simultaneously.

[0165] It should be noted that the dimensions of layers and regions may be exaggerated in the accompanying drawings for clarity. Furthermore, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be intermediate layers. Additionally, it is understood that when an element or layer is referred to as being "below" another element or layer, it can be directly below the other element, or there may be more than one intermediate layer or element. Furthermore, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0166] In this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" means two or more, unless otherwise expressly defined.

[0167] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display substrate, characterized by, The display substrate includes: Substrate; Multiple conductive pads are located on the substrate. A first organic insulating layer is located on a substrate on which the conductive pad is disposed. The first organic insulating layer has a plurality of first openings, each of which corresponds to at least one of the conductive pads, and the orthographic projection of the at least one conductive pad on the substrate is located within the orthographic projection of the corresponding first opening on the substrate. A first inorganic insulating layer is located on the side of the first organic insulating layer away from the substrate and is in direct contact with the first organic insulating layer. In a direction parallel to the substrate, the first inorganic insulating layer is at least partially located between the first organic insulating layer and the conductive pad. The first inorganic insulating layer has a plurality of second openings, each corresponding to a conductive pad, and the orthographic projection of the second opening on the substrate lies within the orthographic projection of the corresponding conductive pad on the substrate. The shortest distance between the edge of the orthographic projection of the first opening on the substrate and the edge of the orthographic projection of an adjacent second opening on the substrate ranges from 20 micrometers to 80 micrometers. A first wiring pattern and a second insulating layer are located between the plurality of conductive pads and the substrate, the first wiring pattern and the second insulating layer being stacked in a direction away from the substrate; the second insulating layer includes a fourth inorganic insulating layer, a second organic insulating layer and a third inorganic insulating layer stacked together, and the second insulating layer has a via, the orthographic projection of the via on the substrate and the orthographic projection of the first wiring pattern on the substrate at least partially overlap; the orthographic projection of the conductive pad on the substrate is located within the orthographic projection of the second organic insulating layer on the substrate; A second trace pattern is located on the same layer as the plurality of conductive pads and electrically connected thereto. The second trace pattern and the conductive pads are located on the side of the first organic insulating layer near the substrate. The second trace pattern is electrically connected to the first trace pattern through the via. The edge of the orthographic projection of the first opening on the substrate is offset from the edge of the orthographic projection of the via on the substrate, and the first organic insulating layer covers the via.

2. The display substrate of claim 1, wherein, The display substrate further includes a conductive anti-oxidation layer, which is located on a substrate on which the first inorganic insulating layer is disposed. The orthographic projection of the conductive anti-oxidation layer on the substrate is located in the orthographic projection of the second opening on the substrate. The conductive anti-oxidation layer covers the pad area in the conductive pad away from the surface of the substrate. The pad area is the area of ​​the conductive pad exposed at the second opening.

3. The display substrate of claim 1, wherein, The shortest distance between two adjacent conductive pads is greater than or equal to a first preset value, and the first opening corresponds to one of the conductive pads.

4. The display substrate according to claim 1, characterized in that, The shortest distance between two adjacent conductive pads is less than a first preset value, and the first opening corresponds to a plurality of conductive pads.

5. The display substrate according to any one of claims 3 or 4, characterized in that, The first preset value ranges from 30 micrometers to 60 micrometers.

6. The display substrate according to claim 1, characterized in that, The plurality of conductive pads includes a plurality of first conductive pads and a plurality of second conductive pads; Every two first conductive pads constitute a first conductive pad group, and one first conductive pad group is used to connect to a light-emitting device. Every N second conductive pads constitute a second conductive pad group, and one second conductive pad group is used to connect to a driver chip. The first opening includes a first sub-opening and a second sub-opening, the first sub-opening corresponding to one of the first conductive pad groups, and the second sub-opening corresponding to one of the second conductive pad groups.

7. The display substrate according to claim 1, characterized in that, The plurality of conductive pads includes a plurality of first conductive pads and a plurality of second conductive pads; Every two first conductive pads constitute a first conductive pad group, and one first conductive pad group is used to connect to a light-emitting device. Every N second conductive pads constitute a second conductive pad group, and each second conductive pad group is used to connect to a driver chip. The first opening includes a first sub-opening and a second sub-opening, the first sub-opening corresponding to at least three adjacent first conductive pad groups, and the second sub-opening corresponding to one second conductive pad group.

8. The display substrate according to any one of claims 6 or 7, characterized in that, The distance between adjacent first and second sub-openings ranges from 20 micrometers to 100 micrometers.

9. The display substrate according to claim 1, characterized in that, The first opening corresponds to at least one second opening, and the orthographic projection of the at least one second opening on the substrate is located in the orthographic projection of the corresponding first opening on the substrate.

10. The display substrate according to claim 1, characterized in that, The display substrate is rectangular and has two opposing first edges and two opposing second edges; The display substrate also includes a connection terminal and a side trace located at the second edge, and the connection terminal and the side trace are electrically connected. The plurality of first openings includes a target first opening, which is adjacent to the first edge, and the edge of the target first opening coincides with the edge of the first organic insulating layer located at the first edge.

11. The display substrate according to claim 10, characterized in that, The first organic insulating layer also has a third opening, which is adjacent to the second edge and corresponds to at least one of the conductive pads. The edge of the orthographic projection of the third opening on the substrate is at least partially located outside the orthographic projection of the corresponding at least one conductive pad on the substrate. There is a second predetermined distance between the edge of the third opening and the edge of the first organic insulating layer located at the second edge.

12. The display substrate according to claim 11, characterized in that, The second preset distance ranges from 20 micrometers to 50 micrometers.

13. The display substrate according to claim 1, characterized in that, The display substrate also has an alignment mark, and the first organic insulating layer also has a fourth opening, which is adjacent to the alignment mark. The fourth opening corresponds to one of the conductive pads, and the fourth opening on the substrate is located in the orthographic projection of the corresponding conductive pad on the substrate.

14. A display device, characterized in that, include: The display substrate according to any one of claims 1 to 13.

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