A flexible thin film transistor and a method of manufacturing the same

Abstract

The present application relates to the technical field of semiconductor preparation, in particular to a flexible thin film transistor and a preparation method thereof, which comprises a substrate, a first metal film, a second metal film, a third metal film, a PdSe2 channel layer, an h-BN dielectric layer and a graphene film; the first metal film and the second metal film are respectively arranged at two adjacent top corner positions of the substrate; the third metal film is arranged at a center position of an edge of the substrate; the PdSe2 channel layer covers a partial region of the first metal film, a region of the substrate between the first metal film and the second metal film and a partial region of the second metal film; the h-BN dielectric layer covers a region of the PdSe2 channel layer between the first metal film and the second metal film; and the graphene film covers a partial region of the h-BN dielectric layer between the first metal film and the second metal film and a partial region of the third metal film, so that the transfer characteristic curve of the flexible thin film transistor still shows good stability after multiple foldings.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor preparation, in particular to a flexible thin film transistor and a preparation method thereof. BACKGROUND

[0002] With the development of science and technology, electronic products are integrated into every field of people's life and enter thousands of households. People's demand for electronic products has become diverse, and integrated circuits need to meet people's requirements in various application scenarios. Flexible electronics are applied in some special application scenarios due to their bendable and light quality characteristics, and the application range is becoming wider and wider. However, flexible electronics have put forward new requirements for materials in flexibility and flexibility, which makes the rigid and heavy Si material not suitable for the development of this field. In addition, the complex preparation process of Si-based transistors also limits the development of flexible electronics. Therefore, how to design a flexible thin film transistor structure with good stability of transfer characteristic curve after multiple folding will become a technical problem urgently to be solved in the field. SUMMARY

[0003] The purpose of the present application is to provide a flexible thin film transistor and a preparation method thereof, so as to improve the stability of the transfer characteristic curve after multiple folding.

[0004] To achieve the above-mentioned purpose, the present application provides a flexible thin film transistor, which comprises:

[0005] a substrate;

[0006] a first metal film arranged at a first top corner position in the substrate;

[0007] a second metal film arranged at a second top corner position in the substrate; the first top corner position and the second top corner position are adjacent top corner positions of the substrate; there is a gap between the first metal film and the second metal film;

[0008] a third metal film arranged at an edge center position of the substrate, the edge center position being an intermediate position between a third top corner position and a fourth top corner position; there is a gap between the third metal film and the first metal film and the second metal film respectively;

[0009] a PdSe2 channel layer covering a partial region of the first metal film, a substrate region between the first metal film and the second metal film, and a partial region of the second metal film;

[0010] an h-BN dielectric layer covering a region of the PdSe2 channel layer between the first metal film and the second metal film;

[0011] a graphene film covering part of the h-BN dielectric layer between the first metal film and the second metal film and part of the third metal film.

[0012] Optionally, the first metal film, the second metal film and the third metal film are all gold films; and the substrate is a PET substrate.

[0013] Optionally, the length of the graphene film covering the third metal film is 5-15 μm, the length of the PdSe2 channel layer covering the first metal film is 5-15 μm, and the length of the PdSe2 channel layer covering the second metal film is 5-15 μm.

[0014] Optionally, the total length of the graphene film is 50-200 μm, and the thickness of the graphene film is 5-10 nm; the total length of the PdSe2 channel layer is 30-50 μm, and the thickness of the PdSe2 channel layer is 5-15 nm; the total length of the h-BN dielectric layer is 15-40 μm, and the thickness of the h-BN dielectric layer is 5-10 nm.

[0015] Optionally, the thickness of the first metal film, the second metal film and the third metal film is all 50 nm, and the thickness of the PET substrate is 0.01 cm.

[0016] The application further provides a preparation method of the flexible thin film transistor.

[0017] Step S1: cleaning a substrate to obtain a target substrate;

[0018] Step S2: performing coating photoresist, electron beam lithography, development, evaporation and de-gluing treatment on the cleaned substrate to obtain a first metal film, a second metal film and a third metal film, respectively;

[0019] Step S3: selecting a PdSe2 crystal block, an h-BN crystal block and a graphene crystal block, respectively, and using England blue tape and an optical microscope in cooperation to obtain a PdSe2 channel layer, an h-BN dielectric layer and a graphene film, respectively;

[0020] Step S4: transferring the PdSe2 channel layer to a part of the first metal film, a substrate region between the first metal film and the second metal film and a part of the second metal film;

[0021] Step S5: transferring the h-BN dielectric layer to the PdSe2 channel layer region between the first metal film and the second metal film;

[0022] Step S6: transferring the graphene film to the part of the h-BN dielectric layer between the first metal film and the second metal film and the part of the third metal film.

[0023] Optionally, the cleaned substrate is subjected to coating photoresist, electron beam lithography, development, evaporation and photoresist removal to obtain the first metal film, the second metal film and the third metal film, specifically comprising:

[0024] Coating photoresist: the target substrate is placed in a spin coater, photoresist is dropped on the target substrate by a dropper, and the spin coater is used for spin coating twice, and after coating, the heater controls the temperature of the baking tray to be 180℃ for baking for 90s for standby;

[0025] Electron beam lithography: the baked target substrate is placed in an electron beam lithography system for multiple correction and exposure operations;

[0026] Development: two beakers are prepared, one is filled with developer and the other is filled with isopropyl alcohol, the exposed target substrate is soaked in the developer for a few seconds, then is placed in isopropyl alcohol to wash the residual developer, and is blown dry with a nitrogen gun for standby;

[0027] Evaporation: the target substrate after development is subjected to metal evaporation by vacuum thermal evaporation method for standby;

[0028] Photoresist removal: the target substrate after evaporation is subjected to multiple acetone rinsing, and the sample surface is blown dry with a nitrogen gun, and the first metal film, the second metal film and the third metal film obtained after electron beam lithography are prepared.

[0029] Optionally, the current for evaporating metal is 80-90A, and the rate is 0.1-0.12nm / s.

[0030] According to the specific embodiments of the present application, the following technical effects are disclosed:

[0031] The application discloses a flexible thin film transistor and a preparation method thereof, and belongs to the field of flexible thin film transistor. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0033] Figure 1 It is a front view of the flexible thin film transistor of the embodiment of the present application.

[0034] Figure 2 It is a top view of the flexible thin film transistor of the embodiment of the present application.

[0035] Figure 3 It is a side view of the flexible thin film transistor of the embodiment of the present application.

[0036] Figure 4 It is a schematic view of the change of the transfer characteristic curve with the number of bending.

[0037] In the drawings, 1 is a substrate, 2 is a first metal thin film, 3 is a second metal thin film, 4 is a third metal thin film, 5 is a PdSe2 channel layer, 6 is an h-BN dielectric layer, and 7 is a graphene thin film. DETAILED DESCRIPTION

[0038] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0039] The present application aims to provide a flexible thin film transistor and a preparation method thereof, so as to improve the transfer characteristic curve stability of the flexible thin film transistor after multiple foldings.

[0040] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] The present application mainly aims to solve the problem that the metal thin film of the flexible transistor is warped due to stress concentration when being bent, and then the overall foldable times of the device are affected, and even the device is cracked and fails. The specific embodiments are described in detail as follows:

[0042] Embodiment 1

[0043] As shown in Figures 1-3 , the present application discloses a flexible thin film transistor, comprising: a substrate 1, a first metal thin film 2, a second metal thin film 3, a third metal thin film 4, a PdSe2 channel layer 5, an h-BN dielectric layer 6 and a graphene thin film 7.

[0044] The first metal thin film 2 and the second metal thin film 3 are respectively arranged at two adjacent top corner positions in the substrate 1; there is a gap between the first metal thin film 2 and the second metal thin film 3. The third metal thin film 4 is arranged at the edge center position of the substrate 1, and the edge center position is the middle position between the third top corner position and the fourth top corner position; there is a gap between the third metal thin film 4 and the first metal thin film 2 and the second metal thin film 3 respectively.

[0045] The PdSe2 channel layer 5 covers a partial region of the first metal thin film 2, a region of the substrate 1 between the first metal thin film 2 and the second metal thin film 3, and a partial region of the second metal thin film 3; the h-BN dielectric layer 6 covers a region of the PdSe2 channel layer 5 between the first metal thin film 2 and the second metal thin film 3; and the graphene thin film 7 covers a partial region of the h-BN dielectric layer 6 between the first metal thin film 2 and the second metal thin film 3 and a partial region of the third metal thin film 4.

[0046] The application connects the first metal film 2 and the second metal film 3 as source / drain electrodes, connects the graphene film 7 as a top gate electrode to the third metal film 4 on the substrate 1 and the h-BN dielectric layer 6 on the PdSe2 channel layer 5, and forms a top gate bottom contact flexible transistor. In use, three voltages are applied to the first metal film 2, the second metal film 3 and the third metal film 4. Since the three metal films for applying voltage are prepared in the same photoetching, the application reduces the photoetching times in the process of making the transistor.

[0047] As an optional embodiment, the first metal film 2, the second metal film 3 and the third metal film 4 are all gold films (Au), the first metal film 2 and the second metal film 3 are respectively used as source / drain electrodes, and the third metal film 4 is used for graphene gate connection. The gate voltage is not directly applied to the graphene film 7, but is applied to the third metal film 4.

[0048] As an optional embodiment, the substrate 1 is preferably a PET (polyethylene terephthalate) substrate with a thickness of 0.01 cm. The PET substrate has the functions of moisture-proof, flexibility, firmness and shock resistance.

[0049] As shown in Figures 1-3 The length of the graphene film 7 covering the third metal film 4 is 5-15 μm, the total length of the graphene film 7 is 50-200 μm, and the thickness of the graphene film 7 is 5-10 nm. The length of the PdSe2 channel layer 5 covering the first metal film 2 is 5-15 μm, the length of the PdSe2 channel layer 5 covering the second metal film 3 is 5-15 μm, the total length of the PdSe2 channel layer 5 is 30-50 μm, and the thickness of the PdSe2 channel layer 5 is 5-15 nm. The total length of the h-BN dielectric layer 6 is 15-40 μm, and the thickness of the h-BN dielectric layer 6 is 5-10 nm. The thicknesses of the first metal film 2, the second metal film 3 and the third metal film 4 are all 50 nm.

[0050] In this embodiment, the specific sizes of the first metal film 2, the second metal film 3 and the third metal film 4 are set according to actual needs, and will not be discussed here.

[0051] Embodiment 2

[0052] The application discloses a preparation method of a flexible thin film transistor.

[0053] Step S1: cleaning the substrate 1.

[0054] Step S2: After cleaning the substrate 1, the photoresist is applied, electron beam lithography, development, evaporation and de-glue treatment are carried out to obtain the first metal film 2, the second metal film 3 and the third metal film 4 respectively.

[0055] Step S3: PdSe2 crystal block, h-BN crystal block and graphene crystal block are selected respectively, and England blue tape and optical microscope are used in cooperation to obtain PdSe2 channel layer 5, h-BN dielectric layer 6 and graphene film 7 respectively.

[0056] Step S4: The PdSe2 channel layer 5 is transferred to the partial area of the first metal film 2, the area between the first metal film 2 and the second metal film 3 of the substrate 1, and the partial area of the second metal film 3.

[0057] Step S5: The h-BN dielectric layer 6 is transferred to the PdSe2 channel layer 5 area between the first metal film 2 and the second metal film 3.

[0058] Step S6: The graphene film 7 is transferred to the partial area of the h-BN dielectric layer 6 between the first metal film 2 and the second metal film 3 and the partial area of the third metal film 4.

[0059] The following will be discussed in detail:

[0060] Step S1: The substrate 1 is cleaned to obtain the target substrate; specifically, polyethylene terephthalate (PET) is selected as the substrate 1, the thickness of the PET layer is 0.01 cm, the substrate 1 is sequentially placed in an ultrasonic cleaner, and is sequentially cleaned with acetone, isopropyl alcohol and deionized water for 5 minutes, and finally dried with a nitrogen gun as a target substrate for standby.

[0061] Step S2: After cleaning the substrate 1, the photoresist is applied, electron beam lithography, development, evaporation and de-glue treatment are carried out to obtain the first metal film 2, the second metal film 3 and the third metal film 4 respectively, which specifically includes:

[0062] Apply photoresist: place the target substrate in the spin coating machine, drop the photoresist on the target substrate with a dropper, spin twice with the spin coating machine, and after the coating is completed, the oven temperature is controlled by the heater to 180°C for 90s for standby. Specifically, the target substrate of step S1 is placed in the spin coating machine, the photoresist of type S1813 is dropped on the target substrate with a dropper, the first stage is rotated at 500 rpm for 5s with the spin coating machine, the second stage is rotated at an initial speed of 1000 rpm for 40s with the spin coating machine, and after the coating is completed, the oven temperature is controlled by the heater to 180°C for 90s for standby.

[0063] E-beam lithography: the baked target substrate is placed into the e-beam lithography system for multiple correction and exposure operations; specifically, the baked target substrate is placed into the e-beam lithography system, and current, image, and other correction actions are performed, then the exposure wavelength is set to 590-740 nm, after confirming two alignment points, the instrument automatically performs correction actions, and then the process of seeking alignment points is repeated three times. After three times of correction, the target substrate is usually within the allowable error range, and exposure is performed. After exposure, the sample is used as a target substrate.

[0064] Development: two beakers are prepared, one is filled with a developing solution, and the other is filled with isopropyl alcohol. After the exposed target substrate is soaked in the developing solution for a few seconds, it is washed in isopropyl alcohol to remove residual developing solution, and then dried with a nitrogen gun for standby. Specifically, two beakers are prepared, one is filled with a developing solution, and the other is filled with isopropyl alcohol. The developing solution used in this step is MIBK (4-methyl-2-pentanone), which is uniformly mixed with water in a ratio of 1:3 to form a dilute solution. After the exposed target substrate is soaked in the dilute solution for a few seconds, it is washed in isopropyl alcohol to remove residual developing solution, and then dried with a nitrogen gun for standby.

[0065] Evaporation: a metal is evaporated on the developed target substrate by vacuum thermal evaporation for standby; specifically, a 50 nm metal is evaporated on the developed target substrate by vacuum thermal evaporation for standby. The evaporation current of gold is 80-90 A, and the rate is 0.1-0.12 nm / s. The metal evaporated in this embodiment is preferably gold.

[0066] Debinding: the evaporated target substrate is washed multiple times with acetone, and then the sample surface is dried with a nitrogen gun. After e-beam lithography, a first metal thin film 2, a second metal thin film 3, and a third metal thin film 4 are prepared. Specifically, the evaporated target substrate is placed in a culture dish filled with acetone for about 8 hours to dissolve the photoresist and wash away the unexposed metal film. After 8 hours of standing, the sample surface is washed again with acetone to remove the remaining metal, and then dried with a nitrogen gun to complete the stripping process. After e-beam lithography, a source and a drain electrode, and a gold thin film connected to the graphene gate are prepared, which are labeled as a first metal thin film 2, a second metal thin film 3, and a third metal thin film 4, respectively. The third metal thin film 4 is located in the upper central position, while the first metal thin film 2 and the second metal thin film 3 are symmetrically distributed on the lower left and right. At this point, the preparation of the metal source and drain electrodes (first metal thin film 2 and second metal thin film 3) and the third metal thin film 4 connected to the graphene gate is completed. The third metal thin film 4 is used for graphene gate connection, and the gate voltage is not directly applied to the graphene, but to the third metal thin film 4.

[0067] Step S3: Select PdSe2 crystal block, h-BN crystal block and graphene crystal block respectively, and use England blue tape and optical microscope to obtain PdSe2 channel layer 5, h-BN dielectric layer 6 and graphene film 7 respectively, which specifically includes:

[0068] Step S31: Select PdSe2 crystal block, and use England blue tape and optical microscope to obtain PdSe2 channel layer 5, which specifically includes: use England blue tape to make a transfer on PdSe2 crystal block, and then tear the England blue tape with another piece of England blue tape, so that PdSe2 is divided into two parts. Repeat the above steps several times, and then attach the PdSe2 sheet to the Gelpak mechanical peeling special PF gel film on the glass slide. Then gently lift the PdSe2 sheet, and observe the PF gel film under the optical microscope. Select the PdSe2 film with a thickness of 5-15 nm, a uniform surface and a length of 30-50 μm as the PdSe2 channel layer 5.

[0069] Step S32: Select h-BN crystal block, and use England blue tape and optical microscope to obtain h-BN dielectric layer 6, which specifically includes: use England blue tape to make a transfer on h-BN crystal block, and then tear the England blue tape with another piece of England blue tape, so that h-BN is divided into two parts. Repeat the above steps several times, and then attach the h-BN sheet to the Gelpak mechanical peeling special PF gel film on the glass slide. Then gently lift the h-BN sheet, and observe the PF gel film under the optical microscope. Select the h-BN film with a thickness of 5-10 nm, a uniform surface and a length of 15-40 μm as the h-BN dielectric layer 6.

[0070] Step S33: Select graphene crystal block, and use England blue tape and optical microscope to obtain graphene film 7, which specifically includes: use England blue tape to make a transfer on graphene crystal block, and then tear the England blue tape with another piece of England blue tape, so that graphene is divided into two parts. Repeat the above steps several times, and then attach the graphene sheet to the Gelpak mechanical peeling special PF gel film on the glass slide. Then gently lift the graphene sheet, and observe the PF gel film under the optical microscope. Select the graphene film with a thickness of 5-10 nm, a uniform surface and a length of 50-200 μm as the graphene film 7.

[0071] Step S4: transfer the PdSe2 channel layer 5 to the first metal film 2 partial region, the substrate 1 region between the first metal film 2 and the second metal film 3, and the second metal film 3 partial region; specifically, the PdSe2 channel layer 5 on the PF gel film prepared in step S31 is transferred to the first metal film 2 partial region, the substrate 1 region between the first metal film 2 and the second metal film 3, and the second metal film 3 partial region by using a two-dimensional material transfer system and a matching microscope, and overlaps the source and drain electrodes (the first metal film 2 and the second metal film 3) by 5-15 μm, and the PdSe2 channel layer 5 serves as a conductive channel of the transistor.

[0072] Step S5: transfer the h-BN dielectric layer 6 to the PdSe2 channel layer 5 region between the first metal film 2 and the second metal film 3; specifically, the h-BN dielectric layer 6 on the PF gel film prepared in step S32 is transferred to the PdSe2 channel layer 5 directly above by using a two-dimensional material transfer system and a matching microscope; in this embodiment, the h-BN film material serves as a dielectric layer of the transistor.

[0073] Step S6: transfer the graphene film 7 to the h-BN dielectric layer 6 partial region between the first metal film 2 and the second metal film 3 and the third metal film 4 partial region; specifically, the graphene film 7 on the PF gel film prepared in step S33 is transferred to the h-BN dielectric layer 6 directly above, and overlaps the third metal film 4 by 5-15 μm, and the graphene film 7 serves as a gate electrode, and the voltage applied to the third metal film 4 acts on the entire transistor, and thus a flexible thin film transistor is prepared.

[0074] Figure 4 The characteristic curve graphs of the flexible thin film transistor of the present application after being folded 0 times, 5 times, 10 times and 15 times are given, and it can be seen that Figure 4 the source and drain current and the gate voltage change little, and thus it can be deduced that the transfer characteristic curve still shows good stability after being folded multiple times.

[0075] The present application focuses on the application of two-dimensional materials with high specific area, high optical transparency and excellent mechanical flexibility in flexible electronics, and the two-dimensional materials as the channel (PdSe2) and the gate (graphene) bring higher mechanical flexibility and thinner thickness to the device. In particular, the strong interaction force (covalent bond) in the graphene layer enables the gate to better adapt to the use environment of flexible electronics bending and folding. At the same time, the two-dimensional transistor has a simple preparation method compared with the silicon-based transistor, which greatly reduces the cost and difficulty of large-scale preparation of flexible electronics in the future, making it possible for smart wear, foldable / rollable displays and electronic skin applications in the future.

[0076] The biggest advantage of the present application compared with the prior art is that, in the manufacturing process, since the three metal films are in the same layer, the gate only needs to connect the channel and the external electrode through graphene, so only one electron beam lithography is included in the device manufacturing process, compared with the manufacturing process of other flexible transistors, the number of lithography in the transistor manufacturing process is reduced, and therefore the process is simpler. At the same time, the gate and the channel material of the transistor respectively adopt graphene and PdSe2, compared with the traditional silicon-based MOS structure, since the introduction of two-dimensional material, the structure has a thinner thickness, can better adapt to bending, twisting and stretching and other deformations, and is more in line with the future application scenarios of intelligent wearable; in addition, the strong interaction force (covalent bond) in the graphene layer makes it easy to deform in the direction perpendicular to the surface, showing good mechanical flexibility, thereby ensuring the stability of the gate during bending. In summary, the present application makes full use of the advantages of two-dimensional materials in thickness and flexibility, and realizes the preparation of a flexible device with good stability and wide application range through single lithography.

[0077] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between various embodiments can be referred to each other.

[0078] The principles and implementation modes of the present application are described by applying specific examples herein, and the above description of the embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A flexible thin film transistor, characterized by, The flexible thin film transistor comprises: a substrate; a first metal thin film arranged at a first top corner position in the substrate; a second metal thin film arranged at a second top corner position in the substrate; the first top corner position and the second top corner position are adjacent top corner positions of the substrate; there is a gap between the first metal thin film and the second metal thin film; a third metal thin film arranged at an edge center position of the substrate, the edge center position being a middle position between a third top corner position and a fourth top corner position; there is a gap between the third metal thin film and the first metal thin film and the second metal thin film respectively; a PdSe2 channel layer covering a partial region of the first metal thin film, a substrate region between the first metal thin film and the second metal thin film, and a partial region of the second metal thin film; an h-BN dielectric layer covering a region of the PdSe2 channel layer between the first metal thin film and the second metal thin film; a graphene thin film covering a partial region of the h-BN dielectric layer between the first metal thin film and the second metal thin film and a partial region of the third metal thin film.

2. The flexible thin film transistor of claim 1, wherein, The first metal thin film, the second metal thin film and the third metal thin film are all gold thin films; and the substrate is a PET substrate.

3. The flexible thin film transistor of claim 1, wherein, The length of the graphene thin film covering the third metal thin film is 5-15 μm, the length of the PdSe2 channel layer covering the first metal thin film is 5-15 μm, and the length of the PdSe2 channel layer covering the second metal thin film is 5-15 μm.

4. The flexible thin film transistor of claim 1, wherein, The total length of the graphene thin film is 50-200 μm, and the thickness of the graphene thin film is 5-10 nm; the total length of the PdSe2 channel layer is 30-50 μm, and the thickness of the PdSe2 channel layer is 5-15 nm; the total length of the h-BN dielectric layer is 15-40 μm, and the thickness of the h-BN dielectric layer is 5-10 nm.

5. The flexible thin film transistor of claim 2, wherein, The thickness of the first metal thin film, the second metal thin film and the third metal thin film is all 50 nm, and the thickness of the PET substrate is 0.01 cm.

6. A method of fabricating a flexible thin film transistor, comprising: The preparation method comprises: Step S1: cleaning the substrate to obtain a target substrate; Step S2: performing coating photoresist, electron beam lithography, development, evaporation and de-gluing treatment on the cleaned substrate to obtain a first metal thin film, a second metal thin film and a third metal thin film respectively; Step S3: selecting PdSe2 crystal blocks, h-BN crystal blocks and graphene crystal blocks respectively, and using England blue tape and an optical microscope in cooperation to obtain a PdSe2 channel layer, an h-BN dielectric layer and a graphene thin film respectively; Step S4: transferring the PdSe2 channel layer to a partial region of the first metal thin film, a substrate region between the first metal thin film and the second metal thin film, and a partial region of the second metal thin film; Step S5: transferring the h-BN dielectric layer to a region of the PdSe2 channel layer between the first metal thin film and the second metal thin film; and Step S6: transferring the graphene thin film to a partial region of the h-BN dielectric layer between the first metal thin film and the second metal thin film and a partial region of the third metal thin film. Step S6: transferring the graphene film to the part of the h-BN dielectric layer between the first metal film and the second metal film and the part of the third metal film.

7. The method for fabricating a flexible thin-film transistor according to claim 6, characterized in that, The cleaned substrate is subjected to photoresist coating, electron beam lithography, development, evaporation and photoresist stripping to obtain the first metal film, the second metal film and the third metal film, specifically including: Photoresist coating: the target substrate is placed in a spin coater, photoresist is dropped on the target substrate by a dropper, and the target substrate is spin-coated twice by the spin coater. After the coating is completed, the heater controls the temperature of the baking tray to be 180°C for baking for 90s for standby; Electron beam lithography: the baked target substrate is placed in an electron beam lithography system for multiple correction and exposure operations; Development: prepare two beakers, one of which is filled with developer and the other is filled with isopropyl alcohol. After the exposed target substrate is soaked in the developer for a few seconds, it is washed with isopropyl alcohol to remove the residual developer, and then it is blown dry with a nitrogen gun for standby; Evaporation: the target substrate after development is subjected to metal evaporation by vacuum thermal evaporation method for standby; Photoresist stripping: the target substrate after evaporation is subjected to multiple acetone rinsing, and then the surface of the sample is blown dry with a nitrogen gun to obtain the first metal film, the second metal film and the third metal film after electron beam lithography.

8. The method for fabricating a flexible thin-film transistor according to claim 7, characterized in that, The current for metal evaporation is 80-90A, and the rate is 0.1-0.12nm / s.

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