Light Emitting Diodes and Light Emitting Devices

Abstract

This invention relates to a light-emitting diode (LED) and a light-emitting device. The LED includes a semiconductor epitaxial stack having opposing first and second surfaces. From the first surface to the second surface, it comprises sequentially stacked N-type semiconductor layers, an active layer, and a P-type semiconductor layer. The N-type semiconductor layer includes a first ohmic contact layer, a first capping layer, and a first window layer. The P-type semiconductor layer includes a second capping layer and a second window layer. The invention is characterized in that the thickness of the N-type semiconductor layer is less than 1.2 μm. By adjusting the doping method and thickness of the first window layer, the ESD performance of the LED chip can be ensured to remain unaffected. Simultaneously, by thinning the first window layer 102, the height from the first mesa to the first ohmic contact layer can be reduced, thereby reducing the chip manufacturing process difficulty and improving the chip's yield.

Description

Technical Field

[0001] This invention relates to a light-emitting diode and a light-emitting device, belonging to the field of semiconductor optoelectronic devices and technology. Background Technology

[0002] As display technology develops towards higher brightness, higher contrast, wider color gamut, HDR, flexible / curved surfaces, low power consumption, borderless design, and ultra-thinness, Mini-LED, with its unique advantages, has begun to enter the TV-level consumer product market.

[0003] As the name suggests, Mini-LED chips are much smaller in size than traditional LED chips. One problem brought about by the reduction in chip size is the decrease in the chip's electrostatic discharge (ESD) resistance. This directly affects whether Mini-LED chips can enter the high-end market. Therefore, improving the ESD resistance of Mini-LEDs to meet the needs of end-user applications is the primary problem that chip technology needs to solve.

[0004] Secondly, Mini-LED chip manufacturers face the challenge of improving yield and reducing costs. Currently, the first window layer of a red mini-LED accounts for about 25% of the epitaxial cost; reducing its thickness significantly lowers costs. Simultaneously, thinning this layer reduces chip manufacturing difficulty and improves yield. However, the first window layer plays a crucial role in the chip structure by spreading the N-terminal current, significantly impacting the chip's ESD resistance. Theoretically, a thicker first window layer with higher doping concentration results in better current spreading and improved ESD resistance. Simply thinning the first window layer directly significantly reduces the chip's ESD resistance. Improving ESD resistance by increasing the doping concentration of the first window layer leads to reduced LED brightness. This is because higher doping concentrations cause more light absorption, resulting in significantly lower brightness. Furthermore, excessively high doping concentrations reduce the crystal quality of the semiconductor epitaxial stack, thus affecting the LED's reliability. Summary of the Invention

[0005] To address the aforementioned problems, the present invention provides a light-emitting diode (LED), comprising: a semiconductor epitaxial stack having opposing first and second surfaces, and sequentially including an N-type semiconductor layer, an active layer, and a P-type semiconductor layer along a direction from the first surface to the second surface; the N-type semiconductor layer comprising a first ohmic contact layer, a first capping layer, and a first window layer; and the P-type semiconductor layer comprising a second capping layer and a second window layer.

[0006] Its characteristic is that the thickness of the N-type semiconductor layer is less than 1.2 μm.

[0007] In some alternative embodiments, the thickness of the semiconductor epitaxial stack is less than or equal to 10 μm.

[0008] In some alternative embodiments, the material of the first window layer is Al. (1-x) Ga x InP, where 0≤x<1.

[0009] In some alternative embodiments, the thickness of the first window layer is ≤1μm.

[0010] In some optional embodiments, the first window layer comprises a first sublayer and a second sublayer, wherein the doping concentration of the first sublayer is >2E19cm⁻¹. -3 The doping concentration of the second sublayer decreases from the first window layer to the first capping layer.

[0011] In some alternative embodiments, the doping concentration of the second portion of the first window layer decreases linearly or stepwise from the first window layer to the first capping layer.

[0012] In some optional embodiments, the ratio of the thickness of the first portion of the first window layer to the thickness of the first window layer ranges from 50% to 75%.

[0013] In some alternative embodiments, the doping concentration of the first capping layer is less than 3E18cm. -3 .

[0014] In some alternative embodiments, the thickness of the second window layer is less than 8 μm.

[0015] In some alternative embodiments, the light-emitting diode further includes a first mesa that exposes a second window layer.

[0016] In some alternative embodiments, the height from the first platform to the first ohmic contact layer is set to h, where h is less than or equal to 2 μm.

[0017] In some optional embodiments, the light-emitting diode further includes a first contact electrode and a second contact electrode, the first contact electrode being located above a first ohmic contact layer and electrically connected to an N-type semiconductor layer, and the second contact electrode being located above a first mesa and electrically connected to a P-type semiconductor layer.

[0018] In some optional embodiments, the light-emitting diode further includes a first pad electrode and a second pad electrode, the first pad electrode and the second pad electrode forming an electrical connection with the first contact electrode and the second contact electrode.

[0019] In some alternative embodiments, the light-emitting diode further includes an insulating layer having a first opening and a second opening, through which the first pad electrode and the second pad electrode are electrically connected to the first contact electrode and the second contact electrode.

[0020] In some alternative embodiments, the first pad electrode and the second pad electrode comprise an alloy or a stack of any combination of Ti, Al, Pt, Au, Ni, Sn, In, or any combination thereof.

[0021] In some optional embodiments, the light-emitting diode radiates light with a wavelength of 550~950 nm.

[0022] In some alternative embodiments, the surface of the second window layer is a rough surface.

[0023] In some alternative embodiments, the light-emitting diode further includes a substrate, which is a transparent substrate.

[0024] In some alternative embodiments, the light-emitting diode is a flip-chip light-emitting diode.

[0025] The present invention also proposes a light-emitting device comprising a light-emitting diode as described in any of the preceding claims.

[0026] In this invention, by adjusting the doping method of the first window layer—with a high doping concentration design for the first sub-layer and a gradually decreasing doping concentration for the second sub-layer—the total thickness of the first window layer can be reduced, ensuring that the ESD performance of the LED chip remains unaffected. Simultaneously, reducing the thickness of the first window layer 102 reduces the height from the first mesa S1 to the first ohmic contact layer 101, thereby reducing the chip manufacturing process difficulty and improving the chip's yield. Other features and advantages of this invention will be set forth in the following description and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings.

[0027] While the invention will be described below in conjunction with some exemplary embodiments and methods of use, those skilled in the art will understand that it is not intended to limit the invention to these embodiments. Rather, it is intended to cover all alternatives, modifications, and equivalents that fall within the spirit and scope of the invention as defined in the appended claims. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Unless otherwise specified, the positional relationships shown in the drawings in the following description are based on the direction in which the components are drawn in the figure.

[0029] Figure 1 This is a schematic cross-sectional view of the light-emitting diode mentioned in Embodiment 1 of the present invention.

[0030] Figures 2-6 This is a schematic diagram of the structure during the fabrication process of the light-emitting diode mentioned in Embodiment 2 of the present invention.

[0031] Figure 7 This is a schematic cross-sectional view of the light-emitting diode mentioned in Embodiment 3 of the present invention.

[0032] Component labeling in the diagram: 10: Growth substrate; 101: First ohmic contact layer; 102: First window layer; 102a: First sub-layer of the first window layer; 102b: Second sub-layer of the first window layer; 103: First capping layer; 104: Active layer; 105: Second capping layer; 106: Second window layer; 100: Substrate; 107: Bonding layer; 108: First contact electrode; S1: First mesa; 109: Second contact electrode; 110: Insulating layer; 111: First pad electrode; 112: Second pad electrode; 201: Metal interconnect layer; 200: Die-bonding substrate; h: Height from the first mesa to the first ohmic contact layer. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples, so that the process of how the present invention uses technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. Example 1

[0036] Figure 1 This is a cross-sectional structural diagram of a light-emitting diode chip according to an embodiment of the present invention.

[0037] Please refer to Figure 1To achieve at least one or more of the advantages desired by the present invention, one embodiment of the present invention provides a light-emitting diode chip comprising the following stacked layers: 100: substrate; 107: bonding layer; 101: first ohmic contact layer; 102: first window layer; 102a: first sub-layer of the first window layer; 102b: second sub-layer of the first window layer; 103: first cover layer; 104: active layer; 105: second cover layer; 106: second window layer; 108: first contact electrode; S1: first mesa; 109: second contact electrode; 110: insulating layer; 111: first pad electrode; 112: second pad electrode.

[0038] The LED chip can be a standard-sized LED chip. The LED chip can have a diameter of approximately 90,000 μm. 2 Above and approximately 2,000,000 μm 2 The following are the horizontal cross-sectional areas.

[0039] LED chips can also be small or micro-sized. LED chips can have a size of approximately 90,000 μm. 2 The following horizontal cross-sectional area. For example, a light-emitting diode chip may have a length and / or width of more than 100 μm to less than 300 μm, and further may have a thickness of more than 40 μm to less than 100 μm.

[0040] The light-emitting diode (LED) chip can also be a smaller, miniature LED chip. The LED chip can have a horizontal cross-sectional area of ​​approximately 10,000 μm² or less. For example, the LED chip can have a length and / or width of 2 μm or more to 100 μm or less, and further, a thickness of 2 μm or more to 100 μm or less. The LED chip of this embodiment can have the aforementioned horizontal cross-sectional area and thickness, therefore, the LED chip can be easily applied to various electronic devices requiring small and / or miniature light-emitting devices. In this embodiment, a small or micro-sized LED chip, i.e., a mini-LED, or an even smaller, miniature LED chip, is preferred.

[0041] The semiconductor epitaxial stack has a first surface and a second surface opposite to the first surface. The semiconductor epitaxial stack is obtained through MOCVD or other growth methods and is a semiconductor material capable of providing conventional radiation such as ultraviolet, blue, green, yellow, red, and infrared light. Specifically, it can be a material in the 200-950 nm range, such as common nitrides, specifically gallium nitride-based semiconductor epitaxial stacks. Gallium nitride-based epitaxial stacks are commonly doped with elements such as aluminum and indium, primarily providing radiation in the 200-550 nm wavelength range; or common aluminum gallium indium phosphide-based or aluminum gallium arsenide-based semiconductor epitaxial stacks, primarily providing radiation in the 550-950 nm wavelength range. In this embodiment, the semiconductor epitaxial stack is preferably composed of aluminum gallium indium phosphide-based or aluminum gallium arsenide-based materials, and the semiconductor epitaxial stack primarily provides radiation in the 550-950 nm wavelength range.

[0042] The semiconductor epitaxial stack has opposing first and second surfaces, and includes sequentially stacked N-type semiconductor layers, an active layer, and a P-type semiconductor layer from the first surface to the second surface. The N-type semiconductor layer includes a first ohmic contact layer 101, a first window layer 102, and a first capping layer 103. The P-type semiconductor layer includes a second capping layer 105 and a second window layer 106. The semiconductor epitaxial stack has a first mesa S1 that exposes the second window layer 107. Electrons from the N-type semiconductor layer and holes from the P-type semiconductor layer, driven by an applied current, convert electrical energy into light energy and emit light in the active layer 104.

[0043] The first ohmic contact layer 101 forms an ohmic contact with the first contact electrode 108, and the material of the ohmic contact layer 101 is Al. y Ga (1-y) As, where 0 ≤ y < 1 or Al (1-z) Ga z InP, where 0 ≤ z < 1. The doping concentration of the ohmic contact layer 101 is preferably 2 × 10⁻⁶. 18 cm -3 The above is preferred, with 5×10 being more ideal. 18 cm -3 Above, 1×10 20 cm -3 The following measures are taken to achieve better ohmic contact. The thickness of the ohmic contact layer 102 is preferably 40 nm or more and 150 nm or less. In this embodiment, the thickness of the ohmic contact layer 102 is preferably 60 nm.

[0044] Currently, Mini-LED chip manufacturers face the challenge of improving yield and reducing costs. The first window layer of existing red mini-LEDs accounts for approximately 25% of the epitaxial cost. Reducing its thickness significantly lowers costs and simplifies the chip manufacturing process, improving yield. However, the first window layer 102 plays a crucial role in N-terminal current expansion, significantly impacting the chip's ESD resistance. Theoretically, a thicker first window layer 102 with higher doping concentration results in better current expansion and improved ESD resistance. Directly thinning the first window layer 102 to reduce costs significantly decreases the chip's ESD resistance. Increasing the doping concentration of the first window layer 102 to improve ESD resistance leads to reduced LED brightness. This is because higher doping concentrations result in greater light absorption, significantly reducing brightness. Furthermore, excessively high doping concentrations reduce the crystal quality of the semiconductor epitaxial stack, affecting LED reliability. Therefore, this embodiment adjusts the doping method and thickness of the first window layer 103 to improve LED yield and reduce costs.

[0045] In this embodiment, the thickness of the first window layer 102 is less than 1 μm, and the material of the first window layer 102 is...

[0046] Al 1-x Ga x InP, where 0 ≤ x < 1. In this embodiment, the preferred material for the first window layer is AlInP. The first window layer 102 is divided into two sub-layers, and the doping concentration of the first sub-layer 102a is > 2E19cm⁻¹. -3 The doping concentration of the first sublayer remains constant, while the doping concentration of the second sublayer 102b decreases from the first window layer 102 to the first capping layer 103. In some optional embodiments, the doping concentration of the second sublayer 102b of the first window layer decreases linearly or stepwise from the first window layer 102 to the first capping layer 103. In this embodiment, it is preferable that the doping concentration of the second sublayer 102b of the first window layer decreases linearly from the first window layer 102 to the first capping layer 103.

[0047] The thickness of the first sublayer 102a of the first window layer is 50% to 75% of the thickness of the first window layer, preferably greater than 55% of the thickness of the first window layer. By setting the first sublayer of the first window layer to have a high doping concentration and ensuring it is within a certain thickness range, the antistatic capability of the light-emitting diode can be guaranteed not to be affected by the reduction in thickness. In this embodiment, the first window layer 102 is doped with n-type doping. N-type doping is commonly silicon doping, but equivalent substitutions of other elements are also possible.

[0048] In this embodiment, the height from the first platform S1 to the first ohmic contact layer is h, where h is less than or equal to 2 μm.

[0049] In this embodiment, by adjusting the doping method of the first window layer 102, the first sub-layer is designed with a high doping concentration, and the second sub-layer adopts a doping concentration gradient method, thereby reducing the total thickness of the first window layer 102 while ensuring that the ESD performance of the light-emitting diode chip is not affected. At the same time, in this embodiment, the thickness of the first window layer is reduced to less than 1 μm, which reduces the height from the first mesa S1 to the first ohmic contact layer 101 from the original 4~7 μm to less than 2 μm, reducing the chip manufacturing process difficulty and improving the process yield.

[0050] The first capping layer 103 provides electrons to the active layer 105. The preferred material is AlInP, and the thickness is 100-300 nm. The preferred n-type doping concentration is 8E17cm. -3 Above, 3E18cm -3 Below. The most common n-type doping is Si doping, but equivalent substitution by other elements cannot be ruled out.

[0051] The active layer 104 provides a light radiation region for electron-hole recombination. Different materials can be selected depending on the emission wavelength. The active layer 104 can be a periodic structure of a single quantum well or multiple quantum wells. In this embodiment, the active layer 104 is a quantum well structure with n periods. Each quantum well structure includes a well layer and a barrier layer deposited sequentially, wherein the barrier layer has a larger band gap than the well layer. By adjusting the composition ratio of the semiconductor material in the active layer 104, the desired wavelength of light is emitted. The active layer 104 is a material layer that provides electroluminescent radiation, such as aluminum gallium indium phosphide (AlGaInP) or aluminum gallium arsenide (AlGaAs), more preferably AlGaInP, which can be a single quantum well or multiple quantum wells. In this embodiment, the semiconductor epitaxial stack is preferably composed of AlGaInP-based or GaAs-based materials, and the active layer radiates light with a wavelength of 550~950nm.

[0052] In this embodiment, the period number n of the quantum well structure is 2 to 100. The well layer is made of Al. a Ga 1-a The barrier layer is composed of InP material; the barrier layer is made of Al b Ga 1-b The material composition is InP, where 0 ≤ a < b ≤ 1. The thickness of the well layer is 25~50 nm; the thickness of the barrier layer is 50~80 nm; and the Al content b of the barrier layer ranges from 0.5 to 0.90.

[0053] The second capping layer 105 provides holes for the active layer 104. The preferred material is AlInP, and the thickness is 150~400nm. The most common p-type doping is Mg doping, but other equivalent element doping is also possible.

[0054] The second window layer 106 serves to spread the current, and its spreading capability is related to its thickness. Therefore, in this embodiment, its thickness can be selected according to the specific device size, preferably controlled between 2000 nm and 8000 nm. In this embodiment, the thickness of the second current spreading layer 106 is preferably 4000~8000 nm to achieve sufficient current spreading capability. In this embodiment, the preferred material is GaP, with a p-type doping concentration of 6E17~2E18 cm⁻¹. 3 Magnesium doping is the most common type of p-type doping, but other equivalent substitutions by other elements cannot be ruled out.

[0055] Please refer to this again. Figure 1 The semiconductor epitaxial stack is bonded to the substrate 100 via a bonding layer 107. Preferably, the side of the semiconductor epitaxial stack facing the substrate 100 is formed with a rough surface, i.e., the surface of the second window layer 106 is a rough surface, to reduce the number of reflections during light output and improve the brightness of the light-emitting diode. In this embodiment, the substrate 100 is a sapphire substrate. The substrate 100 can be a transparent substrate, and the material of the transparent substrate includes inorganic materials or III-V semiconductor materials. Inorganic materials include silicon carbide (SiC), germanium (Ge), sapphire, lithium aluminate (LiAlO2), zinc oxide (ZnO), glass, or quartz. III-V semiconductor materials include indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), and aluminum nitride (AlN). The substrate 100 has sufficient strength to mechanically support the semiconductor epitaxial stack and can transmit light emitted from the semiconductor epitaxial stack. The thickness of the substrate 100 is preferably 50 μm or more. In addition, in order to facilitate the machining of the substrate 100 after bonding the semiconductor epitaxial layers, a thickness of no more than 300 μm is preferred.

[0056] It should be noted that the light-emitting diode chip of the present invention is not limited to containing only one semiconductor epitaxial stack, but may also contain multiple semiconductor epitaxial stacks located on the substrate 100, wherein the multiple semiconductor epitaxial stacks may have a wire structure to electrically connect the multiple semiconductor epitaxial stacks to each other on the substrate 100 in a series, parallel, series-parallel or other manner.

[0057] The bonding layer 107 may be made of insulating and / or conductive materials. Insulating materials include, but are not limited to, polyimide (PI), benzocyclobutene (BCB), perfluorocyclobutane (PFCB), magnesium oxide (MgO), Su8, epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, glass, alumina (Al2O3), and silicon dioxide (SiO2). x Titanium oxide (TiO2), tantalum oxide (Ta2O5), silicon nitride (SiN) x Alternatively, spin-coated glass (SOG) can be used. Conductive materials include, but are not limited to, indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), zinc oxide (ZnO), indium zinc oxide (IZO), diamond-like carbon thin films (DLC), or gallium zinc oxide (GZO). When the bonding layer 107 uses a conductive material to contact the P-type semiconductor layer, it can act as a current spreading layer, improving the current spreading effect and enhancing the uniformity of current distribution.

[0058] In some embodiments, the refractive index of the bonding layer 107 is preferably between the refractive index of the second window layer 106 and the refractive index of the substrate 100. For example, the second window layer 106 has a refractive index n1, the bonding layer 107 has a refractive index n2, and the substrate 100 has a refractive index n3, wherein refractive index n1 > refractive index n2 > refractive index n3. In some embodiments, the refractive index of the bonding layer 107 is in the range of 1.2 to 3. The bonding layer 107 may be a single-layer structure or a multi-layer structure.

[0059] In order to arrange the first contact electrode 108 and the second contact electrode 109 (described later) on the same side of the N-type semiconductor layer and the P-type semiconductor layer, the P-type semiconductor layer can be deposited on the N-type semiconductor layer with a portion of the N-type semiconductor layer exposed, or the N-type semiconductor layer can be deposited on the P-type semiconductor layer with a portion of the P-type semiconductor layer exposed. For example, please refer to... Figure 1 In this embodiment, the semiconductor epitaxial stack includes a first mesa S1 that at least partially penetrates the first ohmic contact layer 101, the first window layer 102, the first cover layer 103, the active layer 104, and the second cover layer 105 to expose the second window layer.

[0060] The light-emitting diode includes one or more first contact electrodes 108 located on an N-type semiconductor layer and directly or indirectly electrically connected to the N-type semiconductor layer, and one or more second contact electrodes 109 located on a P-type semiconductor layer and directly or indirectly electrically connected to the P-type semiconductor layer. In this embodiment, the first contact electrode 108 is an n-side contact electrode.

[0061] The first contact electrode 108 and the second contact electrode 109 can be metal electrodes. The first contact electrode 108 is composed of at least three elements, Au, Ge, and Ni, and their alloys. In some embodiments, the first contact electrode 108 further comprises Ti and Pt. Specifically, the second contact electrode 109 is preferably a stack of an alloy composed of Au, Zn, or Be, or any combination thereof, and the first contact electrode 108 is preferably a stack of an alloy composed of Au, Ge, or Ni, or any combination thereof. The thickness of the first contact electrode 108 and the second contact electrode 109 is 0.5~3μm, preferably 1μm or more, to ensure that the first contact electrode 108 and the second contact electrode 109 form good ohmic contact with the semiconductor epitaxial stack.

[0062] An insulating layer 110 covers the upper surface and sides of the semiconductor epitaxial stack, and also covers the first contact electrode 108 and the second contact electrode 109. The insulating layer 110 can be formed to extend and cover the upper surface of the substrate 100 partially exposed around the semiconductor epitaxial stack. Therefore, the insulating layer 110 can be in contact with the upper surface of the substrate 100, thus providing a more stable cover over the sides of the semiconductor epitaxial stack. The insulating layer 110 protects the semiconductor epitaxial stack from damage by moisture or contaminants, ensuring the optical and electrical properties of the semiconductor epitaxial stack. The insulating layer can be a single layer or multiple layers, and can be SiO2 or SiN. x It is composed of materials such as Al2O3.

[0063] The insulating layer has a first opening and a second opening, and a first pad electrode 111 and a second pad electrode 111 are arranged on the upper part of the insulating layer 110. The first pad electrode 111 can be electrically connected to the first contact electrode 108 through the first opening of the insulating layer 110. The second pad electrode 112 can be electrically connected to the second contact electrode 109 through the second opening. The first opening and the second opening can be circular in shape. In some other embodiments, the first opening and the second opening can also be square, etc. The shape and number of each opening are not particularly limited. There can be only one opening. If multiple openings are provided, the current can be distributed more evenly. In addition, in some other embodiments, when multiple openings are provided, the openings can be distributed in an equidistant or non-equidistant manner according to actual needs, and are not limited to the embodiments disclosed in this invention. In some embodiments, the first pad electrode 111 includes an alloy or a stack of any combination of Ti, Al, Pt, Au, Ni, Sn or any combination thereof. In some embodiments, the second pad electrode 112 comprises an alloy or a stack of any combination thereof made of Ti, Al, Pt, Au, Ni, Sn, or a combination thereof. The thickness of the first pad electrode 108 and the second pad electrode 109 is 1 to 5 μm, preferably 3 to 4 μm.

[0064] In this invention, by adjusting the doping method of the first window layer 102, the first sub-layer is designed with a high doping concentration, and the second sub-layer adopts a doping concentration gradient method, thereby reducing the total thickness of the first window layer 102. This ensures that the anti-static ESD performance of the light-emitting diode chip is not affected. At the same time, by reducing the thickness of the first window layer 102, the height from the first mesa S1 to the first ohmic contact layer 101 can be reduced, thereby reducing the chip manufacturing process difficulty and improving the chip process yield. Example 2

[0065] The manufacturing process of the light-emitting diode in Embodiment 1 described below will be explained in detail.

[0066] Please refer to Figure 2A semiconductor epitaxial stack is formed on the growth substrate 10, which can typically be grown using various known methods, such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). The growth substrate 10 is a gallium arsenide substrate. The semiconductor epitaxial stack is a gallium arsenide (GaAs) series material, comprising an N-type semiconductor layer, a P-type semiconductor layer, and an active layer 104 located between the N-type and P-type semiconductor layers. The N-type semiconductor layer includes a first ohmic contact layer 101, a first window layer 102, and a first capping layer 103; the P-type semiconductor layer includes a second capping layer 105 and a second window layer 106.

[0067] Please refer to Figure 3 The second window layer 106 is formed by a roughening process, wherein a roughened surface is formed on the surface of the second window layer 106. There are no particular limitations on the method of forming the roughened surface; for example, etching or mechanical polishing can be used. A bonding layer 107 is deposited on the roughened surface of the second window layer 106, and the surface of the bonding layer 107 is polished. The bonding layer 107 is preferably silicon dioxide.

[0068] Please refer to Figure 4 First, the semiconductor epitaxial stack is bonded to the substrate 100 through the bonding layer 107, wherein the substrate 100 is a sapphire substrate; then the growth substrate 10 is removed.

[0069] Please refer to Figure 5 A photoresist pattern is formed on the surface of the semiconductor epitaxial stack. The first ohmic contact layer 101, the first window layer 102, the first capping layer 103, the active layer 104 and the second capping layer 105 are removed from a portion of the surface of the semiconductor epitaxial stack until a portion of the second window layer 106 is exposed, forming a first mesa S1. Then, a first contact electrode 108 and a second contact electrode 109 are formed on the first mesa S1 and the first ohmic contact layer 101.

[0070] Please refer to Figure 6 An insulating layer 110 is deposited, which completely covers the surface of the semiconductor epitaxial stack, the sidewalls of the semiconductor epitaxial stack, and the surface of the exposed bonding layer 107.

[0071] Then, a first opening and a second opening are formed on the insulating layer 110 located on the first ohmic contact layer 101 and the first mesa S1, respectively. A first pad electrode 111 and a second pad electrode 112 are fabricated and electrically connected to the N-type semiconductor layer and the P-type semiconductor layer through the corresponding first and second openings, respectively, to obtain the following... Figure 1 The light-emitting diode shown.

[0072] In this invention, by adjusting the doping method of the first window layer 102, the first sub-layer is designed with a high doping concentration, and the second sub-layer adopts a doping concentration gradient method, thereby reducing the total thickness of the first window layer 102. This ensures that the anti-static ESD performance of the light-emitting diode chip is not affected. At the same time, by reducing the thickness of the first window layer 102, the height from the first mesa S1 to the first ohmic contact layer 101 can be reduced, thereby reducing the chip manufacturing process difficulty and improving the chip process yield. Example 3

[0073] This embodiment provides a light-emitting device, such as... Figure 7 As shown, the light-emitting device includes a die-bonding substrate 200 and a light-emitting diode (LED) located on the die-bonding substrate 200. The LED can be the light-emitting element provided in Embodiment 1 of this application. The die-bonding substrate 200 can be a ceramic substrate, a printed circuit board, etc. A die-bonding region is located on the die-bonding substrate 200, and the die-bonding region is arranged according to a specific logical design sequence. The LED is located on the die-bonding region of the die-bonding substrate 200, and a metal interconnect layer 201, such as a tin interconnect layer, is located between them. The light-emitting device can be, but is not limited to, lamps, displays, etc.

[0074] In this invention, by adjusting the doping method of the first window layer 102, the first sub-layer is designed with a high doping concentration, and the second sub-layer adopts a doping concentration gradient method, thereby reducing the total thickness of the first window layer 102. This ensures that the anti-static ESD performance of the light-emitting diode chip is not affected. At the same time, by reducing the thickness of the first window layer 102, the height from the first mesa S1 to the first ohmic contact layer 101 can be reduced, thereby reducing the chip manufacturing process difficulty and improving the chip process yield.

[0075] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.

[0076] Although this document frequently uses terms such as substrate, growth substrate, semiconductor epitaxial stack, N-type semiconductor layer, active layer, P-type semiconductor layer, first contact electrode, first pad electrode, second contact electrode, second pad electrode, insulating layer, and bonding layer, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention. The terms "first," "second," etc. (if present) in the specification, claims, and accompanying drawings of the embodiments of the invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A light emitting diode, comprising: a semiconductor epitaxial stack having opposite first and second surfaces, comprising in order along a direction from the first surface to the second surface, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer; the N-type semiconductor layer comprises a first ohmic contact layer, a first window layer, and a first cap layer; the P-type semiconductor layer comprises a second cap layer and a second window layer; Characterized in that: the first window layer contains first sub-layer and second sub-layer which are stacked in turn along the direction from the first surface to the second surface, the doping concentration of the first sub-layer is >2E19cm -3 , the doping concentration of the second sub-layer decreases from the first window layer to the first cover layer; the thickness of the N-type semiconductor layer is less than 1.2μm.

2. The light emitting diode of claim 1, wherein: a thickness of the semiconductor epitaxial stack is less than or equal to 10 μm.

3. The light emitting diode of claim 1, wherein: a material of the first window layer is Al (1-x) Ga x InP, where 0≤x<1.

4. The light emitting diode of claim 1, wherein: a thickness of the first window layer is less than or equal to 1 μm.

5. The light emitting diode of claim 1, wherein: a doping concentration of the second sub-layer of the first window layer decreases linearly or stepwise from the first window layer to the first cap layer.

6. The light emitting diode of claim 1, wherein: a ratio of a thickness of the first sub-layer of the first window layer to a thickness of the first window layer is 50% to 75%.

7. The light emitting diode of claim 1, wherein: The first cladding layer has a doping concentration less than 3E18 cm -3 .

8. The light emitting diode of claim 1, wherein: a thickness of the second window layer is less than 8 μm.

9. The light emitting diode of claim 1, wherein: the light emitting diode further comprises a first mesa, the first mesa exposes the second window layer.

10. The light emitting diode of claim 9, wherein: a height of the first mesa to the first ohmic contact layer is h, h is less than or equal to 2 μm.

11. The light emitting diode of claim 9, wherein: the light emitting diode further comprises a first contact electrode and a second contact electrode, the first contact electrode is on the first ohmic contact layer and forms an electrical connection with the N-type semiconductor layer, the second contact electrode is on the first mesa and forms an electrical connection with the P-type semiconductor layer.

12. The light emitting diode of claim 11, wherein: the light emitting diode further comprises a first pad electrode and a second pad electrode, the first pad electrode and the second pad electrode form an electrical connection with the first contact electrode and the second contact electrode.

13. The light emitting diode of claim 12, wherein: the light emitting diode further comprises an insulating layer, the insulating layer has a first opening and a second opening, the first pad electrode and the second pad electrode are electrically connected with the first contact electrode and the second contact electrode through the first opening and the second opening.

14. The light emitting diode of claim 12, wherein: the first pad electrode and the second pad electrode comprise Ti, Al, Pt, Au, Ni, Sn, In, or an alloy or a stack of any combination thereof.

15. The light emitting diode of claim 1, wherein: the light emitting diode radiates light with a wavelength of 550 nm to 950 nm.

16. The light emitting diode of claim 1, wherein: a surface of the second window layer away from the active layer has a rough surface.

17. The light emitting diode of claim 1, wherein: the light emitting diode further comprises a substrate, the substrate is a transparent substrate.

18. The light emitting diode of claim 1, wherein: the light emitting diode is a flip chip light emitting diode.

19. A light-emitting device, characterized in that: the light emitting device comprises the light emitting diode of any one of claims 1 to 18.

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