Operational amplifier device, electronic equipment

Abstract

The present disclosure relates to an operational amplifier device and an electronic device, wherein the device comprises an operational amplifier circuit, a first calibration module, and a second calibration module, wherein the operational amplifier circuit comprises a first input stage amplifier circuit, a second input stage amplifier circuit, an intermediate stage amplifier circuit, and an output stage amplifier circuit, all of which are used for performing an amplification operation, wherein the first calibration module and the second calibration module both comprise a chopping circuit unit and a self-zeroing circuit unit, wherein the first calibration module is arranged at the input end of the first input stage amplifier circuit, and the second calibration module is arranged between the output end of the first input stage amplifier circuit and the input end of the intermediate stage amplifier circuit, wherein the power spectrum density of the clock signal of the chopping circuit unit is a constant. The embodiments of the present disclosure can reduce the influence of mismatched charge during sampling of the self-zeroing circuit unit, so that all samples can obtain lower ripples without increasing the cost and design complexity.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an operational amplifier device and an electronic device. Background Art

[0002] After the Opamp (operational amplifier) ​​circuit is manufactured, due to the influence of process angle (P), power supply voltage (V), temperature (T) (PVT) and matching, an offset voltage that deviates from TYP (typical operating voltage) is usually observed at the input end, and some additional calibration or mismatch reduction circuits need to be added during the design. Usually, a CHOP circuit (chopping circuit) is used to modulate the mismatch voltage to the chopping frequency to obtain a very low DC offset voltage. However, this method will cause ripples at the level of hundreds of uV or even mV, which seriously affects the performance of the circuit; AZ (Auto Zero) is another commonly used method. The offset voltage is stored on the capacitor through sampling, and the stored offset voltage is subtracted when the system is working normally, which can also achieve the purpose of reducing the DC offset voltage. However, this method will introduce folding noise during the sampling process, which will deteriorate the low-frequency noise performance. Summary of the invention

[0003] According to one aspect of the present disclosure, an operational amplifier device is provided, the device comprising an operational amplifier circuit, a first calibration module, and a second calibration module, the operational amplifier circuit comprising a first input stage amplifier circuit, a second input stage amplifier circuit, an intermediate stage amplifier circuit, and an output stage amplifier circuit, all of which are used for performing an amplification operation, the first calibration module and the second calibration module both comprising a chopping circuit unit and a self-zeroing circuit unit, wherein:

[0004] The first calibration module is arranged at the input end of the first input stage amplifier circuit, and the second calibration module is arranged between the output end of the first input stage amplifier circuit and the input end of the intermediate stage amplifier circuit.

[0005] The input end of the second input stage amplifier circuit and the input end of the first calibration module are used to receive input signals.

[0006] The output end of the second input stage amplifier circuit and the output end of the intermediate stage amplifier circuit are connected to the input end of the output stage amplifier circuit.

[0007] The output end of the output stage amplifier circuit is used to output an amplified signal.

[0008] Wherein, in the first calibration module and the second calibration module: the power spectrum density of the clock signal of the chopper circuit unit is a constant.

[0009] In a possible implementation, the clock signal of the chopping circuit unit in the first calibration module and the second calibration module is a random clock signal with a pulse width greater than or equal to 1 / Fchop, and the frequency of the clock signal of the self-zero circuit unit is 2k×Fchop, wherein Fchop is the frequency of the first target clock signal of the chopping circuit unit, and k is a positive integer.

[0010] In a possible implementation, the device further includes a clock signal generating module, which is used to generate a clock signal of the chopper circuit unit and a clock signal of the self-return-to-zero circuit unit, wherein:

[0011] The clock signal generating module comprises:

[0012] An oscillating unit, configured to generate a first clock signal;

[0013] A frequency division unit, connected to the oscillation unit, for dividing the first clock signal to obtain a first target clock signal and a second target clock signal, wherein the frequency of the first target clock signal is Fchop, the frequency of the second target clock signal is 2k×Fchop, k is a positive integer, and the second target clock signal is used as a clock signal of the self-return-to-zero circuit unit;

[0014] A signal generating unit is connected to the frequency dividing unit and is used to generate a clock signal of the chopping circuit unit according to the first target clock signal.

[0015] In a possible implementation, the signal generating unit includes a random number generator.

[0016] In a possible implementation, the frequency division unit includes a plurality of cascaded frequency dividers.

[0017] In a possible implementation, the clock signal generating module further includes a shaping unit, the shaping unit is connected to the signal generating unit, and the shaping unit is used to implement shaping filtering of the clock signal of the chopper circuit unit.

[0018] In a possible implementation, the shaping unit includes a first-order shaping unit and a multi-order shaping unit, wherein:

[0019] The first-order shaping unit includes a code converter, which is used to correct the high level of the clock signal using a first combination code and correct the low level of the clock signal using a second combination code, wherein the sum of each digital code in the first combination code and the second combination code is 0;

[0020] The multi-order shaping unit includes a delta-sigma modulator, and the delta-sigma modulator is used to perform high-order shaping filtering on the clock signal of the chopper circuit unit.

[0021] The pulse width of the clock signal output after being shaped by the shaping unit is 1 / (2Fchop).

[0022] In a possible implementation, in the first calibration module: the input end of the chopper circuit unit serves as the input end of the first calibration module, the output end of the chopper circuit unit is connected to the input end of the self-zero circuit unit, and the output end of the self-zero circuit unit serves as the output end of the first calibration module.

[0023] In a possible implementation, in the second calibration module: the input end of the self-zeroing circuit unit serves as the input end of the second calibration module, the output end of the self-zeroing circuit unit is connected to the input end of the chopping circuit unit, and the output end of the chopping circuit unit serves as the output end of the second calibration module.

[0024] In a possible implementation manner, the self-zeroing circuit unit of the first calibration module includes a first switch, a second switch, and a third switch, wherein:

[0025] The first end of the first switch and the first end of the third switch serve as input ends of the self-return-to-zero circuit unit.

[0026] A common node of the second end of the first switch, the first end of the second switch, the second end of the third switch, and the second end of the second switch serves as an output end of the self-return-to-zero circuit unit.

[0027] In a possible implementation manner, the self-zeroing circuit unit of the second calibration module includes a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first capacitor, and a second capacitor, wherein:

[0028] A common node of the first end of the fourth switch and the first end of the sixth switch, and a common node of the first end of the fifth switch and the first end of the seventh switch serve as an input end of the self-return-to-zero circuit unit,

[0029] The second end of the fourth switch and the second end of the fifth switch serve as output ends of the self-return-to-zero circuit unit.

[0030] The second end of the sixth switch and the first end of the first capacitor are both connected to the first feedback node of the first input stage amplifier circuit.

[0031] The second end of the seventh switch and the first end of the second capacitor are both connected to the second feedback node of the first input stage amplifier circuit.

[0032] The second end of the first capacitor and the second end of the second capacitor are grounded.

[0033] In a possible implementation, the self-reset-to-zero circuit unit cycles between a first working mode and a second working mode, wherein:

[0034] In the first working mode, the second switch, the sixth switch, and the seventh switch are all closed, and the first switch, the third switch, the fourth switch, and the fifth switch are all open.

[0035] In the second working mode, the second switch, the sixth switch, and the seventh switch are all opened, and the first switch, the third switch, the fourth switch, and the fifth switch are all closed.

[0036] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the operational amplifier device.

[0037] The embodiment of the present disclosure provides an operational amplifier device, the device comprising an operational amplifier circuit, a first calibration module, and a second calibration module. The operational amplifier circuit comprises a first input stage amplifier circuit, a second input stage amplifier circuit, an intermediate stage amplifier circuit, and an output stage amplifier circuit, all of which are used for performing an amplification operation. The first calibration module and the second calibration module both comprise a chopping circuit unit and a self-zeroing circuit unit, wherein: the first calibration module is arranged at the input end of the first input stage amplifier circuit, the second calibration module is arranged between the output end of the first input stage amplifier circuit and the input end of the intermediate stage amplifier circuit, the input end of the second input stage amplifier circuit and the input end of the first calibration module are used to receive an input signal, the output end of the second input stage amplifier circuit and the output end of the intermediate stage amplifier circuit are connected to the input end of the output stage amplifier circuit, and the output end of the output stage amplifier circuit is used to output an amplified signal. By setting the first calibration module and the second calibration module: the power spectrum density of the clock signal of the chopping circuit unit is a constant, so that the embodiment of the present disclosure can reduce the influence of mismatched charge when the self-zeroing circuit unit is sampled, so that all samples can obtain lower ripples without increasing the cost and design complexity.

[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0040] Figure 1A schematic diagram of an operational amplifier device according to an embodiment of the present disclosure is shown.

[0041] Figure 2 A schematic diagram of an operational amplifier device according to an embodiment of the present disclosure is shown.

[0042] Figure 3 A schematic diagram of a clock signal generating module according to an embodiment of the present disclosure is shown.

[0043] Figure 4 A schematic diagram showing a clock signal of a chopper circuit unit and a clock signal of a self-zero circuit unit is shown.

[0044] Figure 5a The figure shows the ripple amplitude diagram before first-order shaping. Figure 5b Figure 2 shows a schematic diagram of the ripple amplitude after first-order shaping. DETAILED DESCRIPTION

[0045] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0046] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0047] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0048] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0049] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0050] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0051] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0052] Based on the defects of the prior art mentioned in the background technology, the embodiments of the present disclosure can use CHOP and AZ together to solve the above two problems at the same time: AZ reduces the DC offset voltage, greatly reducing the Ripple at Fchop, and the folding noise caused by AZ is moved to Fchop by CHOP, and the low-frequency noise is also optimized. This method can indeed achieve good performance under ideal conditions, but there are many mismatches inside the actual circuit. For example, when the AZ switch is switched, the injected charge mismatch will be caused by the switch mismatch, or the voltage on both sides of the asymmetric circuit switch is different, which also causes charge injection mismatch. The charge mismatch generates a mismatch voltage on the AZ sampling capacitor and generates a system error, which ultimately generates a Ripple of uV to tens of uV. If Fchop is not high enough and not far enough away from the signal bandwidth, even a Ripple of uV level will affect the performance.

[0053] In addition, each chip can be trimmed to reduce adaptation, but this method requires a lot of time and cost; another method is to rely on a sieve, because the injected charge mismatch conforms to the normal distribution, the sieve can be used to select samples that meet the requirements, but this method also requires a lot of time and cost; you can also connect multiple input stages in parallel to average the mismatch, but this method requires more parallel branches to achieve better results, which consumes a lot of area and power consumption, and adds additional cost and design complexity.

[0054] In view of this, an embodiment of the present disclosure provides an operational amplifier device, the device comprising an operational amplifier circuit, a first calibration module, and a second calibration module. The operational amplifier circuit comprises a first input stage amplifier circuit, a second input stage amplifier circuit, an intermediate stage amplifier circuit, and an output stage amplifier circuit, all of which are used for performing an amplification operation. The first calibration module and the second calibration module both comprise a chopping circuit unit and a self-zeroing circuit unit, wherein: the first calibration module is arranged at the input end of the first input stage amplifier circuit, the second calibration module is arranged between the output end of the first input stage amplifier circuit and the input end of the intermediate stage amplifier circuit, the input end of the second input stage amplifier circuit and the input end of the first calibration module are used to receive an input signal, the output end of the second input stage amplifier circuit and the output end of the intermediate stage amplifier circuit are connected to the input end of the output stage amplifier circuit, and the output end of the output stage amplifier circuit is used to output an amplified signal, wherein in the first calibration module and the second calibration module: the power spectrum density of the clock signal of the chopping circuit unit is a constant, so that the embodiment of the present disclosure can reduce the influence of mismatch charge when the self-zeroing circuit unit is sampled, so that all samples can obtain lower ripples without increasing the cost and design complexity.

[0055] See also Figure 1 , Figure 1 A schematic diagram of an operational amplifier device according to an embodiment of the present disclosure is shown.

[0056] like Figure 1 As shown, the device includes an operational amplifier circuit, a first calibration module 10, and a second calibration module 20. The operational amplifier circuit includes a first input stage amplifier circuit Gm1, a second input stage amplifier circuit Gm2, an intermediate stage amplifier circuit Gm3, and an output stage amplifier circuit Gm4, all of which are used for performing an amplification operation. The first calibration module 10 and the second calibration module 20 both include a chopper circuit unit and a self-zeroing circuit unit ( Figure 1 not shown), where:

[0057] The first calibration module 10 is arranged at the input end of the first input stage amplifier circuit Gm1, and the second calibration module 20 is arranged between the output end of the first input stage amplifier circuit Gm1 and the input end of the intermediate stage amplifier circuit Gm3.

[0058] The input end of the second input stage amplifier circuit Gm2 and the input end of the first calibration module 10 are used to receive an input signal (VIP / VIN).

[0059] The output end of the second input stage amplifier circuit Gm2 and the output end of the intermediate stage amplifier circuit Gm3 are connected to the input end of the output stage amplifier circuit Gm4.

[0060] The output end of the output stage amplifier circuit Gm4 is used to output an amplified signal VOUT.

[0061] Wherein, in the first calibration module 10 and the second calibration module 20: the power spectrum density of the clock signal of the chopper circuit unit is a constant.

[0062] The embodiment of the present disclosure sets the power spectral density of the clock signal of the chopper circuit unit to be a constant, so that the spectrum can be changed from a single frequency point to a "white" noise floor, which is equivalent to breaking up the energy of the single frequency point. Due to the law of conservation of energy, the energy of a single frequency point is evenly distributed on all frequencies, thereby effectively reducing the ripple caused by switch adaptation.

[0063] The disclosed embodiment utilizes a self-zeroing circuit unit to suppress offset voltage and utilizes a chopper circuit unit to reduce low-frequency noise, thereby achieving the purpose of low offset and low noise.

[0064] The disclosed embodiments do not limit the specific implementation of the operational amplifier circuit, the first calibration module 10, the second calibration module 20, the chopper circuit unit and the self-zeroing circuit unit, and do not limit the specific implementation of the first input stage amplifier circuit Gm1, the second input stage amplifier circuit Gm2, the intermediate stage amplifier circuit Gm3 and the output stage amplifier circuit Gm4. Those skilled in the art may implement them using appropriate technical means according to actual conditions and needs.

[0065] The embodiment of the present disclosure does not limit the method for generating the clock signal of the chopper circuit unit, and those skilled in the art may configure it according to actual conditions and needs.

[0066] In a possible implementation, the clock signal of the chopping circuit unit in the first calibration module 10 and the second calibration module 20 may be a random clock signal having a pulse width greater than or equal to 1 / Fchop, and the frequency of the clock signal of the self-return-to-zero circuit unit is 2k×Fchop, wherein Fchop is the frequency of the first target clock signal of the chopping circuit unit, and k is a positive integer.

[0067] It should be noted that the “pulse width” of the clock signal in the embodiment of the present disclosure refers to the duration of the high level (1).

[0068] The disclosed embodiment of the present invention does not limit the method for generating the clock signal (random clock signal) of the chopper circuit unit, and does not limit the specific size of k. By way of example, the clock signal of the chopper circuit unit may include multiple random clock signals with a pulse width of 1 / Fchop and a pulse width greater than 1 / Fchop. The frequency spectrum of the random clock signal is "white", that is, the disclosed embodiment converts a square wave of a fixed frequency into a random square wave with a minimum pulse width of 1 / Fchop. The frequency spectrum changes from a single frequency point to a "white" noise floor, which is equivalent to breaking up the energy of the single frequency point. However, due to the law of conservation of energy, the energy of a single frequency point is evenly distributed on all frequency points, effectively reducing the ripple caused by switch adaptation.

[0069] See also Figure 2 , Figure 2 A schematic diagram of an operational amplifier device according to an embodiment of the present disclosure is shown.

[0070] In a possible implementation, Figure 2 As shown, in the first calibration module 10: the input end of the chopping circuit unit 110 serves as the input end of the first calibration module 10, the output end of the chopping circuit unit 110 is connected to the input end of the self-zeroing circuit unit 120, and the output end of the self-zeroing circuit unit 120 serves as the output end of the first calibration module 10.

[0071] In a possible implementation, Figure 2 As shown, in the second calibration module 20: the input end of the self-zeroing circuit unit 220 serves as the input end of the second calibration module 20, the output end of the self-zeroing circuit unit 220 is connected to the input end of the chopping circuit unit 210, and the output end of the chopping circuit unit 210 serves as the output end of the second calibration module 20.

[0072] The embodiments of the present disclosure do not limit the specific implementation of each chopping circuit unit and each self-zeroing circuit unit. Those skilled in the art can set them according to actual conditions and needs. The chopping circuit unit and the self-zeroing circuit unit can be implemented using technical solutions in conventional technologies.

[0073] In a possible implementation, Figure 2 As shown, the self-zero circuit unit 120 of the first calibration module 10 may include a first switch S1, a second switch S2, and a third switch S3, wherein:

[0074] The first end of the first switch S1 and the first end of the third switch S3 serve as input ends of the self-return-to-zero circuit unit 120.

[0075] A common node of the second end of the first switch S1 , the first end of the second switch S2 , the second end of the third switch S3 , and the second end of the second switch S2 serves as an output end of the self-return-to-zero circuit unit 120 .

[0076] In a possible implementation, Figure 2 As shown, the self-zero circuit unit 220 of the second calibration module 20 may include a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, a first capacitor C1, and a second capacitor C2, wherein:

[0077] A common node of the first end of the fourth switch S4 and the first end of the sixth switch S6, a common node of the first end of the fifth switch S5 and the first end of the seventh switch S7 serves as an input end of the self-return-to-zero circuit unit 220.

[0078] The second end of the fourth switch S4 and the second end of the fifth switch S5 serve as the output end of the self-return-to-zero circuit unit 220.

[0079] The second end of the sixth switch S6 and the first end of the first capacitor C1 are both connected to the first feedback node of the first input stage amplifier circuit Gm1.

[0080] The second end of the seventh switch S7 and the first end of the second capacitor C2 are both connected to the second feedback node of the first input stage amplifier circuit Gm1.

[0081] The second end of the first capacitor C1 and the second end of the second capacitor C2 are grounded.

[0082] In a possible implementation manner, the self-return-to-zero circuit unit (self-return-to-zero circuit unit 120 and self-return-to-zero circuit unit 220) cycles between a first working mode and a second working mode, wherein:

[0083] In the first working mode, the second switch S2, the sixth switch S6, and the seventh switch S7 are all closed, and the first switch S1, the third switch S3, the fourth switch S4, and the fifth switch S5 are all open.

[0084] In the second working mode, the second switch S2, the sixth switch S6, and the seventh switch S7 are all opened, and the first switch S1, the third switch S3, the fourth switch S4, and the fifth switch S5 are all closed.

[0085] Exemplarily, the frequency of AZ (self-zeroing circuit unit 120 and self-zeroing circuit unit 220) can be first set to twice that of CHOP (chopping circuit unit 110 and chopping circuit unit 210), so that self-zeroing is performed once at the high level (for example, the first working mode) and the low level (for example, the second working mode) of the CHOP clock. When the level is high, the second switch S2, the sixth switch S6, and the seventh switch S7 are all closed, and the first switch S1, the third switch S3, the fourth switch S4, and the fifth switch S5 are all disconnected, so that the offset voltage of the first input stage amplifier circuit Gm1 is stored in the first capacitor C1 and the second capacitor C2; when the level is low, the second switch S2, the sixth switch S6, and the seventh switch S7 are all disconnected, and the first switch S1, the third switch S3, the fourth switch S4, and the fifth switch S5 are all closed, and the circuit works normally. At this time, the output of the first input stage amplifier circuit Gm1 will be affected by the offset voltage at the input end and the offset voltage stored on the first capacitor C1 and the second capacitor C2 at the same time, and the offset voltage can be offset by controlling the polarity. The above process reduces the offset voltage at the DC, initially reduces the Ripple energy generated by the switch movement of the chopper circuit unit, and effectively alleviates the noise floor rise caused by the subsequent Ripple dispersion.

[0086] In a possible implementation manner, the device may further include a clock signal generating module, configured to generate a clock signal of the chopper circuit unit and a clock signal of the self-return-to-zero circuit unit.

[0087] The embodiments of the present disclosure do not limit the specific implementation of the clock signal generating module. Those skilled in the art may adopt relevant technologies to implement it according to actual conditions and needs, which is exemplarily introduced below.

[0088] See also Figure 3 , Figure 3 A schematic diagram of a clock signal generating module according to an embodiment of the present disclosure is shown.

[0089] In a possible implementation, Figure 3 As shown, the clock signal generating module may include:

[0090] The oscillating unit 310 is used to generate a first clock signal, wherein the frequency Fosc of the first clock signal is, for example, at the MHz level;

[0091] A frequency division unit 320, connected to the oscillation unit 310, is used to divide the first clock signal to obtain a first target clock signal and a second target clock signal, wherein the frequency of the first target clock signal is Fchop, the frequency of the second target clock signal is 2k×Fchop, k is a positive integer, and the second target clock signal is used as a clock signal of the self-return-to-zero circuit unit;

[0092] The signal generating unit 330 is connected to the frequency dividing unit 320, and is used to generate a clock signal (CLK / CLKB) of the chopping circuit unit according to the first target clock signal.

[0093] Through the above clock signal generating module, the embodiment of the present disclosure can quickly and efficiently generate the clock signal of the chopper circuit unit and the clock signal of the self-return-to-zero circuit unit.

[0094] The embodiments of the present disclosure do not limit the specific implementation methods of the oscillation unit 310, the frequency division unit 320, and the signal generation unit 330. Those skilled in the art may adopt relevant technologies to implement them according to actual conditions and needs. For example, the oscillation unit 310 may include an oscillator, the frequency division unit 320 may include one or more cascaded frequency dividers, and the signal generation unit 330 may include a signal generator, a random number generator, etc.

[0095] In a possible implementation, Figure 3 As shown, the clock signal generating module may further include a shaping unit 340, which is connected to the signal generating unit 330. The shaping unit 340 is used to implement shaping filtering of the clock signal of the chopping circuit unit and output the filtered clock signal (CLK / CLKB) of the chopping circuit unit.

[0096] The embodiment of the present disclosure does not limit the specific implementation method of the shaping unit 340, and those skilled in the art can adopt relevant technologies to implement it according to actual conditions and needs.

[0097] See also Figure 4 , Figure 4 A schematic diagram showing a clock signal of a chopper circuit unit and a clock signal of a self-zero circuit unit is shown.

[0098] For example, the clock signal (CLK / CLKB) output by the shaping unit 340 can be used to control the switch of the chopping circuit unit, so that the ripple of the chopping circuit unit can be shaped without affecting the low-frequency noise performance. The clock signal of the self-returning-to-zero circuit unit can be obtained by extracting the second-to-last stage output of the multi-stage frequency divider in the frequency dividing unit 320, that is, a square wave with a frequency of 2*Fchop, and can be generated by a non-overlapping clock generating circuit to generate clocks CLKaz and clocks CLKBaz, forming a clock relationship of Faz=2Fchop.

[0099] In a possible implementation, the shaping unit 340 may include a first-order shaping unit and a multi-order shaping unit.

[0100] Exemplarily, the first-order shaping unit includes a code converter, which is used to correct the high level of the clock signal using a first combination code and to correct the low level of the clock signal using a second combination code, wherein the sum of each digital code in the first combination code and the second combination code is 0.

[0101] For example, first-order shaping can use Manchester code. Assuming that the high and low levels of the above random clock are 1 and -1 respectively, Manchester code uses the combination of the first combination code (1, -1) to represent the high level 1, and the combination of the second combination code (-1, 1) to represent the low level -1. The sequence after conversion has two characteristics: ① The average value of the sequence is 0, that is, there is a zero point at DC; ② The sequence must be bounded. These two characteristics mean that the sequence is represented by (1-z -1 ), that is, the first-order shaping is completed. Specifically, a software module of a Manchester code shaping unit can be written to implement the first-order shaping. The average value of the result converted by the Manchester code must be 0, and the sum of the entire sequence is bounded, which satisfies the two characteristics of the first-order filtering.

[0102] See also Figure 5a and Figure 5b , Figure 5a The figure shows the ripple amplitude diagram before first-order shaping. Figure 5b Figure 2 shows a schematic diagram of the ripple amplitude after first-order shaping.

[0103] For example, Figure 5a As shown in the figure, before shaping: the ripple amplitude at 50KHz is 9uV. Figure 5b As shown in the figure, after the first-order shaping, the ripple is controlled within 100nV, which is significantly lower than before the shaping.

[0104] Exemplarily, the multi-order shaping unit may include a Δ-Σ modulator (Delta Sigma Modulator), and the Δ-Σ modulator is used to perform high-order shaping filtering on the clock signal of the chopper circuit unit.

[0105] The pulse width of the clock signal output after being shaped by the shaping unit is 1 / (2Fchop).

[0106] Exemplarily, in order to meet the requirements of higher application signal bandwidth and further reduce the impact of shaping on low-frequency noise, high-order shaping can also be used. High-order shaping can be achieved through a Δ-Σ modulator, and the specific order and oversampling rate can be adjusted according to the needs. Exemplarily, the order of the Δ-Σ modulator can be adjusted first according to the shaping requirements, and the Δ-Σ modulator can use a conventional structure, which is not limited to the embodiments of the present disclosure. Secondly, in order to obtain better low-frequency noise performance, the oversampling rate OSR of the Δ-Σ modulator can be increased. For example, an additional two-way frequency divider can be added after the sampling clock is generated by 2 / N division, so that the OSR of the Δ-Σ modulator can be made 2. If the OSR needs to be increased, the added two-way frequency division can be changed to four-way frequency division (OSR=4) or eight-way frequency division (OSR=8), and so on.

[0107] The embodiment of the present disclosure sets the first calibration module 10 and the second calibration module 20 such that the power spectral density of the clock signal of the chopper circuit unit is a constant, so as to break up the clock frequency of the chopper circuit unit, and thus break up the ripple frequency, so that the harmonic energy that should appear at Fchop is dispersed to various frequency points. In this way, the embodiment of the present disclosure can reduce the influence of mismatched charge during sampling of the self-zeroing circuit unit, so that all samples can obtain lower ripples without increasing the cost and design complexity. Moreover, the embodiment of the present disclosure further performs first-order or even high-order shaping while breaking up the harmonics, so as to reduce the influence on low-frequency noise.

[0108] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the operational amplifier device.

[0109] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. An operational amplifier device, characterized in that: The device comprises an operational amplifier circuit, a first calibration module, and a second calibration module. The operational amplifier circuit comprises a first input stage amplifier circuit, a second input stage amplifier circuit, an intermediate stage amplifier circuit, and an output stage amplifier circuit, all of which are used for performing an amplification operation. The first calibration module and the second calibration module both comprise a chopping circuit unit and a self-zeroing circuit unit, wherein: The first calibration module is arranged at the input end of the first input stage amplifier circuit, and the second calibration module is arranged between the output end of the first input stage amplifier circuit and the input end of the intermediate stage amplifier circuit. The input end of the second input stage amplifier circuit and the input end of the first calibration module are used to receive input signals. The output end of the second input stage amplifier circuit and the output end of the intermediate stage amplifier circuit are connected to the input end of the output stage amplifier circuit. The output end of the output stage amplifier circuit is used to output an amplified signal. Wherein, in the first calibration module and the second calibration module: the power spectrum density of the clock signal of the chopper circuit unit is a constant, The device also includes a clock signal generating module, which is used to generate a clock signal of the chopper circuit unit and a clock signal of the self-return-to-zero circuit unit, wherein: The clock signal generating module comprises: An oscillating unit, configured to generate a first clock signal; A frequency division unit, connected to the oscillation unit, for dividing the first clock signal to obtain a first target clock signal and a second target clock signal, wherein the frequency of the first target clock signal is Fchop, the frequency of the second target clock signal is 2k×Fchop, k is a positive integer, and the second target clock signal is used as a clock signal of the self-return-to-zero circuit unit; A signal generating unit is connected to the frequency dividing unit and is used to generate a clock signal of the chopping circuit unit according to the first target clock signal.

2. The device according to claim 1, characterized in that The clock signal of the chopping circuit unit in the first calibration module and the second calibration module is a random clock signal with a pulse width greater than or equal to 1 / Fchop, and the frequency of the clock signal of the self-zeroing circuit unit is 2k×Fchop, where Fchop is the frequency of the first target clock signal of the chopping circuit unit, and k is a positive integer.

3. The device according to claim 1, characterized in that The signal generating unit comprises a random number generator, The frequency division unit includes a plurality of cascaded frequency dividers, The clock signal generating module further comprises a shaping unit, which is connected to the signal generating unit and is used to implement shaping filtering on the clock signal of the chopping circuit unit.

4. The device according to claim 3, characterized in that The shaping unit includes a first-order shaping unit and a multi-order shaping unit, wherein: The first-order shaping unit includes a code converter, which is used to correct the high level of the clock signal using a first combination code and correct the low level of the clock signal using a second combination code, wherein the sum of each digital code in the first combination code and the second combination code is 0; The multi-order shaping unit includes a delta-sigma modulator, and the delta-sigma modulator is used to perform high-order shaping filtering on the clock signal of the chopper circuit unit. The pulse width of the clock signal output after being shaped by the shaping unit is 1 / (2Fchop).

5. The device according to claim 1, characterized in that In the first calibration module: the input end of the chopper circuit unit serves as the input end of the first calibration module, the output end of the chopper circuit unit is connected to the input end of the self-zero circuit unit, and the output end of the self-zero circuit unit serves as the output end of the first calibration module. In the second calibration module: the input end of the self-zero circuit unit serves as the input end of the second calibration module, the output end of the self-zero circuit unit is connected to the input end of the chopping circuit unit, and the output end of the chopping circuit unit serves as the output end of the second calibration module.

6. The device according to claim 5, characterized in that The self-zeroing circuit unit of the first calibration module includes a first switch, a second switch, and a third switch, wherein: The first end of the first switch and the first end of the third switch serve as input ends of the self-return-to-zero circuit unit. A common node of the second end of the first switch, the first end of the second switch, the second end of the third switch, and the second end of the second switch serves as an output end of the self-return-to-zero circuit unit.

7. The device according to claim 6, characterized in that The self-zeroing circuit unit of the second calibration module includes a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first capacitor, and a second capacitor, wherein: A common node of the first end of the fourth switch and the first end of the sixth switch, and a common node of the first end of the fifth switch and the first end of the seventh switch serve as an input end of the self-return-to-zero circuit unit, The second end of the fourth switch and the second end of the fifth switch serve as output ends of the self-return-to-zero circuit unit. The second end of the sixth switch and the first end of the first capacitor are both connected to the first feedback node of the first input stage amplifier circuit. The second end of the seventh switch and the first end of the second capacitor are both connected to the second feedback node of the first input stage amplifier circuit. The second end of the first capacitor and the second end of the second capacitor are grounded.

8. The device according to claim 7, characterized in that The self-zero circuit unit cycles between a first working mode and a second working mode, wherein: In the first working mode, the second switch, the sixth switch, and the seventh switch are all closed, and the first switch, the third switch, the fourth switch, and the fifth switch are all open. In the second working mode, the second switch, the sixth switch, and the seventh switch are all opened, and the first switch, the third switch, the fourth switch, and the fifth switch are all closed.

9. An electronic device, characterized in that: The electronic device comprises the operational amplifier device according to any one of claims 1-8.

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