A novel super junction SGT MOSFET device and its preparation method

Abstract

The present invention discloses a novel super junction SGT MOSFET device and a preparation method thereof, belonging to the field of semiconductor technology, comprising a drain contact metal layer and a source contact metal layer, and an N+ type substrate, a super junction region and an isolation oxide layer arranged therebetween, wherein the super junction region comprises a super junction N column region and two lower super junction P column regions, an upper P column region is arranged above the lower super junction P column region, a P well is embedded in the upper P column region, and a source region for N+ ion implantation is embedded in the P well; a deep trench is arranged above the super junction N column region, and a control gate, a shielding gate and a gate oxide layer are arranged in the deep trench. The present invention further reduces the on-resistance, increases the withstand voltage, adjusts the electric field distribution in the drift region, improves the quality of the polysilicon deposited in the control gate, and improves the capacitance effect, and the preparation method provided by the present application simplifies the process steps of the novel super junction SGT MOSFET device and saves the manufacturing cost.

Description

Technical Field

[0001] The present invention mainly relates to the field of semiconductor technology, and in particular to a novel super junction SGT MOSFET device and a preparation method thereof. Background Art

[0002] In power semiconductor devices, low on-resistance, low loss and high breakdown voltage are the main performance indicators studied. Figure 1 The figure shows the structure of a traditional power MOSFET device represented by Trench MOSFET. Compared with the traditional VDMOS device, this structure eliminates the JFET region, that is, it does not generate neck resistance, thereby reducing the on-resistance value. However, as the breakdown voltage of the device increases, the depth of the trench also increases. Too deep a trench depth will affect the performance of the device. At the same time, the charge-coupled MOSFET increases the contact area between the gate and the drift regions on both sides while deepening the trench. Therefore, the gate capacitance and gate charge increase, which has a certain impact on the frequency response characteristics of the device. Therefore, in order to further optimize the capacitance characteristics, a split-gate trench MOSFET, namely SGT MOSFET (Split-Gate MOSFET), is produced, as shown below Figure 2 As shown in the figure, compared with the traditional Trench MOSFET power device, the depth of the trench of this structure is deeper, and the added shielding gate plays the role of the internal field plate in the drift region, which significantly improves the on-resistance and quality factor of the device. At the same time, through the separated gate structure, the gate-drain capacitance is converted into gate-source capacitance, which greatly reduces the gate-drain capacitance, makes the switching speed faster, and has better device performance. Therefore, it is widely used in communications, computers, automobiles and other industries.

[0003] However, as the breakdown voltage of the device increases to 200V and above, it is difficult to achieve it simply by increasing the trench depth. In addition, due to the limitations of the structural characteristics of trench power semiconductor devices, the source and drain terminals often suddenly bear a large voltage when working, thereby generating a large electric field, which is more likely to be concentrated at the corners of the gate oxide layer, which may cause the gate oxide layer to be broken down. How to solve the contradiction between low specific on-resistance and high breakdown voltage has become the main research direction for the development of trench power MOSFET devices.

[0004] In order to solve the contradiction between on-resistance and breakdown voltage, the concept of full super junction was introduced. In 1988, Academician Chen Xingbi and others proposed the theory of super junction withstand voltage structure. This structure broke the silicon limit theory and the contradiction between on-resistance and breakdown voltage. The P column and N column were introduced into the traditional lower doped drift layer. This structure can greatly reduce the on-resistance of the drift region. Therefore, a relatively low on-resistance can be obtained under the same withstand voltage. In addition, with the continuous development of science and technology, how to further reduce the on-resistance, process difficulty and manufacturing cost of super junction SGT MOSFET is still an important research topic in the industry. Summary of the invention

[0005] The technical solution of the present invention aims at the technical problem that the existing technical solutions are too single, and provides a solution that is significantly different from the existing technologies. It mainly provides a new super junction SGT MOSFET device, which has the advantages of reducing the on-resistance of the device under the same withstand voltage conditions, adjusting the electric field distribution in the drift region, increasing the breakdown voltage, improving the quality of the polysilicon deposited in the control gate, and improving the capacitance effect; the application also provides a method for preparing a new super junction SGT MOSFET device, which further simplifies the process steps and reduces the manufacturing cost.

[0006] The technical solution adopted by the present invention to solve the above technical problems is:

[0007] A novel super junction SGT MOSFET device comprises a drain contact metal layer and a drain connected thereto, and a source contact metal layer and a source connected thereto; an N+ type substrate is provided on the side of the drain contact metal layer facing the source contact metal layer, a super junction region is provided on the side of the N+ type substrate facing the source contact metal layer, the super junction region comprises an N column and two P columns respectively located on two opposite sides of the N column, the P column comprises an upper P column region facing the source contact metal layer and a lower super junction P column region contacting the N+ type substrate, a P well is embedded in the upper P column region, a source region implanted with N+ ions is embedded in the P well, an isolation oxide layer is provided between the upper P column region and the source contact metal layer; a deep trench is provided on the side of the N column close to the source contact metal layer, a control gate and a shield gate are provided in the deep trench, and a gate oxide layer is located on the sidewall and bottom of the deep trench and isolates the control gate and the shield gate.

[0008] Furthermore, the device has holes on both sides that penetrate the isolation oxide layer and the N+ ion-implanted source region and extend to the P well, and a P+ ion-implanted region is provided in the hole; the source contact metal layer has a conductive structure connected to the P+ ion-implanted region along the hole.

[0009] Furthermore, the N column is aligned with a portion of a lower super junction P column region to form a super junction N column region, the bottom of the control gate is in an inverted isosceles trapezoid, and the bottom of the shield gate is in a multi-step shape.

[0010] Preferably, the distance between the side of the deep trench facing the drain contact metal layer and the drain contact metal layer is not greater than the distance between the side of the lower super junction P column region and the super junction N column region close to the source contact metal layer and the drain contact metal layer.

[0011] Preferably, the widths of the N+ ion-implanted source region, P well, upper P column region and lower super junction P column region are the same, and the N+ ion-implanted source region, P well and upper P column region are aligned toward the side of the source contact metal layer.

[0012] Preferably, the thicknesses of the upper P column region, the lower super junction P column region and the super junction N column region are equal.

[0013] Furthermore, the doping concentration of the upper P column region is below 2E15, the doping concentration of the lower super junction P column region and the super junction N column region is above 5E15, and the lower super junction P column region and the super junction N column region satisfy an alternating complementary relationship.

[0014] The present invention also provides a method for preparing the novel super junction SGT MOSFET device, comprising the following steps:

[0015] S1: providing a drain contact metal layer, and growing an N+ type substrate on the drain contact metal layer, the N+ type substrate and the drain contact metal layer form an ohmic contact, and the drain contact metal layer is connected to the drain;

[0016] S2: growing a high-concentration N-type doped layer on an N+-type substrate;

[0017] S3: using a trenching process, symmetrically digging deep trenches on both sides of the high-concentration N-type doped layer to obtain two symmetrical deep trenches penetrating the upper and lower surfaces of the high-concentration N-type doped layer, and then performing CVD deposition on the two deep trenches to deposit two layers of P-type impurity silicon with different doping concentrations, namely, a lower super-junction P column region and an upper P column region, wherein the doping concentration of the lower super-junction P column region is greater than that of the upper P column region, thereby forming two symmetrical P column regions;

[0018] S4: a deep trench is dug in the middle of the high-concentration N-type doped layer to obtain a deep trench penetrating the upper surface of the high-concentration N-type doped layer, and the remaining high-concentration N-type doped layer forms a super-junction N-column region; then an oxide layer is deposited and grown in the deep trench above the super-junction N-column region;

[0019] S5: growing a layer of polysilicon on the oxide layer by chemical vapor deposition, etching back the polysilicon, and after etching back to a certain depth, starting to perform the first etching back on the oxide layer, and then repeating the above process flow to perform the second etching back until the Nth etching back, and finally obtaining a shielding grid with a multi-step bottom and a side oxide wall around it;

[0020] S6: thermally oxidizing the polysilicon in the shielding gate to grow an oxide layer, the oxide layer serving as a dielectric isolation layer;

[0021] S7: depositing polysilicon again and etching back to form a control gate with an inverted isosceles trapezoidal bottom and side oxide walls around it, and the gate oxide layer is completely formed;

[0022] S8: ion implantation of P-type impurity ions is performed in the two upper P column regions respectively, and high-temperature diffusion is performed to form a P well;

[0023] S9: ion implanting heavily doped N-type impurities into each P well, and forming two symmetrical N+ ion implanted source regions after annealing;

[0024] S10: growing an isolation oxide layer on the control gate, the gate oxide layer and the two N+ ion-implanted source regions;

[0025] S11: using a photolithography process, etching a hole that penetrates the isolation oxide layer and the source region for N+ ion implantation and extends into the P well, and injecting heavily doped P+ ions into two symmetrical holes respectively to form a P+ ion implantation region;

[0026] S12: depositing a metal aluminum layer on the isolation oxide layer by CVD to form a source contact metal layer, wherein the source contact metal layer has a conductive structure connected to the P+ ion implantation region; the source contact metal layer is connected to the source.

[0027] Furthermore, in step S2, the thickness of the high-concentration N-type doping layer is not greater than the maximum depth of the deep trenching process.

[0028] Furthermore, the doping types of N-type and P-type silicon are interchanged.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) The super junction region in the present invention does not use multiple epitaxy and multiple ion implantation to form longitudinally alternating P column regions and N column regions, because it is difficult to form high-concentration and narrow-strip P column regions and N column regions, which will limit the further reduction of the device on-resistance. At the same time, in order to avoid the high cost and high process difficulty caused by multiple epitaxy and multiple ion implantation, the present invention adopts a trenching and deposition process to symmetrically dig deep grooves on both sides of the high-concentration N-type doped layer to obtain two symmetrical deep grooves that penetrate the upper and lower surfaces of the super junction region, and the deep trenches of the double gate are also formed by trenching. Therefore, there is no need to add other process equipment and process flows, further simplifying the process steps and reducing manufacturing costs. Then, two layers of P-type impurity silicon with different doping concentrations are deposited in the two deep trenches by CVD, thereby forming two symmetrical P columnar regions. When applied, the two low-doped upper P-column regions can induce electrons when the device is turned on, thereby forming a conductive path, further reducing the drift region resistance generated by the low-doped upper P-column region, thereby effectively reducing the on-resistance of the device; and the upper P-column region acts as a voltage support layer. As the source-drain voltage increases, the voltage support layer will be completely exhausted before reaching the breakdown voltage. The upper P-column region and the super junction region bear a higher breakdown voltage together, thereby increasing the breakdown voltage of the device, so that the device can withstand a higher withstand voltage value; the lower super junction P-column region and the super junction N-column region form an alternating complementary relationship, and the two are in basic charge balance in the drift region. In addition, the P-column region adopts a two-layer structure with different doping concentrations, which can make the current in the entire P-column region relatively evenly distributed, further changing the path of the avalanche current, suppressing the avalanche current, and making the device less prone to damage.

[0031] (2) The present invention can increase the depletion region of the device when it is in an avalanche state by having a multi-step shielding gate and a stepped gate oxide layer, and can adjust the electric field distribution in the drift region, thereby increasing the breakdown voltage of the device. At the same time, under the same withstand voltage conditions, the on-resistance of the device can be further reduced.

[0032] (3) In the present invention, the bottom opening of the control gate is etched into an inverted isosceles trapezoid by wet etching, and then filled with a conductive medium. The conductive medium is polysilicon. The bottom thickness of the SGT MOSFET device trench can be made greater than the side wall mainly due to the strong filling ability of polysilicon. The inverted isosceles trapezoid at the bottom opening can improve the quality of deposited polysilicon.

[0033] (4) In the present invention, the dielectric layer between the control gate and the shield gate is formed by thermally oxidizing polysilicon to grow an oxide layer. In this way, the distance between the two layers of polysilicon filled in the trench can be increased, thereby reducing the capacitance of the gate and the source, and further improving the capacitance effect of the device.

[0034] (5) In the present invention, the source contact metal layer is formed by drilling holes deep into the P-well region and performing P+ ion implantation, so that the P+ ion implantation region is short-circuited with the source region implanted with N+ ions, thereby eliminating the liner bias effect and forming a better ohmic contact. Metal aluminum is then deposited to form a source contact metal layer, reducing the P-well adjustment injection region, thereby simplifying the process steps and saving manufacturing costs.

[0035] The present invention will be explained in detail below with reference to the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The present invention is a schematic diagram of a cell structure of a Trench MOSFET device in the prior art;

[0037] Figure 2 It is a schematic diagram of a cell structure of a SGT MOSFET device in the prior art;

[0038] Figure 3 It is a schematic diagram of the cell structure of the novel super junction SGT MOSFET device in the present invention.

[0039] Reference numerals:

[0040] 1. Source contact metal layer; 2. Isolation oxide layer; 3. N+ ion implanted source region; 4. P+ ion implanted region; 5. P well; 6. Upper P column region; 7. Lower super junction P column region; 8. Super junction N column region; 9. Control gate; 10. Shielding gate; 11. Gate oxide layer; 12. N+ type substrate; 13. Drain contact metal layer; 14. Drain; 15. Source. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings, but the present invention can be implemented in different forms and is not limited to the embodiments described in the text. On the contrary, these embodiments are provided to make the content disclosed in the present invention more thorough and comprehensive.

[0042] It should be noted that when an element is referred to as being "fixed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used in this article are for illustrative purposes only.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly connected by technicians in the technical field to which the present invention belongs. The terminology used in the specification of the present invention is for the purpose of describing specific embodiments and is not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0044] Example 1: Please refer to the attached Figure 3 , a new super junction SGT MOSFET device, comprising:

[0045] An N+ type substrate 12, wherein a drain contact metal layer 13 is provided at the bottom of the N+ type substrate 12, and the drain contact metal layer 13 is connected to a drain 14;

[0046] A super junction region, located above the N+ type substrate 12, the super junction region including two lower super junction P column regions 7 and one super junction N column region 8;

[0047] Two upper P column regions 6 (i.e., P-voltage support layers) are located above the two lower super junction P column regions 7 in a one-to-one correspondence;

[0048] Two P wells 5 are respectively embedded in the upper parts of the two upper P column regions 6;

[0049] Two N+ ion-implanted source regions 3 are respectively embedded in the upper parts of the two P wells 5;

[0050] A deep trench is formed above the super junction N column region 8 and between the two upper P column regions 6, and a gate oxide layer 11, a control gate 9 and a shielding gate 10 are provided in the deep trench, wherein the control gate 9 is located above the shielding gate 10, the bottom of the control gate 9 is in an inverted isosceles trapezoid, and the bottom of the shielding gate 10 is in a multi-step shape; the control gate 9 and the shielding gate 10 are isolated by the gate oxide layer 11, and the sidewalls and the bottom of the deep trench are isolated by the gate oxide layer 11;

[0051] An isolation oxide layer 2 is located above two N+ ion-implanted source regions 3 and a control gate 9, and holes are provided on both sides of the device, penetrating the isolation oxide layer 2 and the N+ ion-implanted source regions 3 and extending to the P well 5, and a P+ ion-implanted region 4 is provided at the bottom of the hole;

[0052] The source contact metal layer 1 is located above the isolation oxide layer 2 . The source contact metal layer 1 has a conductive structure connected to the P+ ion implantation region 4 along the hole. The source contact metal layer 1 is connected to the source 15 .

[0053] In this embodiment, the top of the lower super junction P column region 7 and the top of the super junction N column region 8 are flush with the bottom of the gate oxide layer 11 in the deep trench.

[0054] In this embodiment, the width of the P-well 5 is the same as the width of the corresponding lower super junction P-column region 7 , and the top of the P-well 5 is flush with the top of the corresponding upper P-column region 6 .

[0055] In this embodiment, the width of the N+ ion-implanted source region 3 is the same as that of the corresponding P-well 5 , and the top of the N+ ion-implanted source region 3 is flush with the top of the corresponding P-well 5 .

[0056] In this embodiment, the doping concentrations of the two upper P column regions 6 are both low-doping, with the doping concentration being less than 2E15.

[0057] In this embodiment, the doping concentrations of the lower super junction P column region 7 and the super junction N column region 8 are both highly doped, with a doping concentration above 5E15, and the lower super junction P column region 7 and the super junction N column region 8 satisfy an alternating complementary relationship.

[0058] In this embodiment, the thicknesses of the upper P column region 6 , the lower super junction P column region 7 and the super junction N column region 8 are equal.

[0059] The method for preparing the novel super junction SGT MOSFET device comprises the following steps:

[0060] Step 1: providing a drain contact metal layer 13, and growing an N+ type substrate 12 on the drain contact metal layer 13, wherein the N+ type substrate 12 forms an ohmic contact with the drain contact metal layer 13; the drain contact metal layer 13 is connected to the drain 14;

[0061] Step 2: growing a high-concentration N-type doping layer on the N+ type substrate 12;

[0062] Step 3: Use a trenching process to symmetrically dig deep trenches on both sides of the high-concentration N-type doped layer to obtain two symmetrical deep trenches that penetrate the upper and lower surfaces of the high-concentration N-type doped layer, and then perform CVD deposition (chemical vapor deposition) of two layers of P-type impurity silicon with different doping concentrations in the two deep trenches, respectively, which are an upper P column region 6 and a lower super junction P column region 7. The doping concentration of the lower super junction P column region 7 is greater than the doping concentration of the upper P column region 6, thereby forming two symmetrical P column regions. The upper P column region 6 (P-region) can be used as a voltage support layer to withstand part of the withstand voltage, thereby increasing the breakdown voltage of the device and reducing the on-resistance of the device; the lower super junction P column region 7 (P region) forms an alternating complementary relationship with the super junction N column region 8 (their arrangement positions form an alternating complementary relationship, 1 N column and 1 P column alternate in sequence, Figure 3 A single cell is shown, and the device is formed by connecting many single cells in parallel), and both are in basic charge balance in the drift region;

[0063] Step 4: a deep trench is dug in the middle of the high-concentration N-type doped layer to obtain a deep trench penetrating the upper surface of the high-concentration N-type doped layer, the bottom of the deep trench is flush with the top of the lower super-junction P column region 7, and the remaining high-concentration N-type doped layer forms a super-junction N column region 8; then an oxide layer is deposited and grown in the deep trench above the super-junction N column region 8;

[0064] Step 5: A layer of polysilicon is grown on the oxide layer by chemical vapor deposition, and the polysilicon is etched back. After the polysilicon is etched back to a certain depth, the oxide layer is etched back for the first time. Attention should be paid to the control of the etching depth of the polysilicon, which needs to be determined according to the number of steps. Then the above process flow is repeated to perform the second etching back until the Nth etching back, and finally a shielding gate 10 with a multi-step bottom and a side oxide wall (i.e., part of the gate oxide layer 11) on the side thereof is obtained. The appropriate number of steps is selected in combination with the actual production process line and the performance of the device;

[0065] Step 6: thermally oxidize the polysilicon in the shielding gate 10 to grow an oxide layer, which serves as a dielectric isolation layer between the control gate 9 and the shielding gate 10;

[0066] Step 7: Polysilicon is deposited again and etched back to form the control gate 9 and the side oxide walls around it. The gate oxide layer 11 is then completely formed. The bottom opening of the control gate 9 is wet-etched to form an inverted isosceles trapezoid, and then filled with a conductive medium, which is polysilicon.

[0067] Step 8: ion implantation of P-type impurity ions is performed in two symmetrical upper P column regions 6, and high-temperature diffusion is performed to form a P well 5 (ie, P-body);

[0068] Step 9: ion implantation of heavily doped N-type impurities is performed in each P-well 5, and two symmetrical N+ ion implanted source regions 3 are formed after annealing;

[0069] Step 10: growing an isolation oxide layer 2 on the two N+ ion implanted source regions 3, the control gate 9 and the gate oxide layer 11;

[0070] Step 11: using a photolithography process, etching a hole that penetrates the isolation oxide layer 2 and the N+ ion-implanted source region 3 and extends to the P well 5, and injecting heavily doped P+ ions into two symmetrical holes respectively to form a P+ ion implantation region 4;

[0071] Step 12: A metal aluminum layer is deposited on the isolation oxide layer 2 by CVD to form a source contact metal layer 1, and the source contact metal layer 1 has a conductive structure connected to the P+ ion implantation area 4; the source contact metal layer 1 is connected to the source 15.

[0072] When applied, the two low-doped upper P column regions 6 can induce electrons when the device is turned on, thereby forming a conductive path, further reducing the drift region resistance generated by the low-doped upper P column region 6, thereby effectively reducing the on-resistance of the device; and the upper P column region 6 acts as a voltage support layer. As the source-drain voltage increases, the p-voltage support layer will be completely exhausted before reaching the breakdown voltage. The upper P column region 6 and the super junction region bear a higher breakdown voltage, thereby increasing the breakdown voltage of the device, so that the device can withstand a higher withstand voltage value; the lower super junction P column region 7 and the super junction N column region 8 form an alternating complementary relationship, and the two are in basic charge balance in the drift region. In addition, the P column region adopts a two-layer structure with different doping concentrations, which can make the current in the entire P column region relatively evenly distributed, further change the path of the avalanche current, suppress the avalanche current, and make the device less prone to damage;

[0073] The P+ ion implantation region 4 is short-circuited with the N+ ion implantation source region 3, thereby eliminating the liner bias effect and providing better ohmic contact;

[0074] By having a multi-step shielding gate 10 and a step-shaped gate oxide layer 11, the depletion region of the device in an avalanche state can be increased, and the electric field distribution in the drift region can be adjusted, thereby increasing the breakdown voltage of the device. At the same time, under the same withstand voltage condition, the on-resistance of the device can be further reduced;

[0075] The bottom opening of the control gate 9 is etched into an inverted isosceles trapezoid by wet etching, and then filled with a conductive medium. The conductive medium is polysilicon. The bottom thickness of the SGT MOSFET device trench can be made greater than the side wall mainly by virtue of the strong filling ability of polysilicon. The inverted isosceles trapezoid at the bottom opening can improve the quality of the deposited polysilicon.

[0076] The dielectric layer between the control gate 9 and the shield gate 10 is formed by thermally oxidizing polysilicon to grow an oxide layer. This method can increase the distance between the two layers of polysilicon filled in the trench, thereby reducing the capacitance of the gate and the source, and further improving the capacitance effect of the device.

[0077] Embodiment 2: This embodiment differs from Embodiment 1 in that:

[0078] In this embodiment, the bottom of the deep trench is lower than the upper surface of the lower super junction P column region 7 and the super junction N column region 8 .

[0079] In step 2, the thickness of the high-concentration N-type doping layer above the N+-type substrate 12 is not greater than the maximum depth of the deep trenching process.

[0080] In this embodiment, the doping types of N-type and P-type silicon in the first embodiment are interchanged.

[0081] The rest is the same as the first embodiment.

[0082] The above is an exemplary description of the present invention in combination with the accompanying drawings. It is obvious that the specific implementation of the present invention is not limited to the above-mentioned method. As long as such non-substantial improvements are made by adopting the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. A novel super junction SGT MOSFET device, comprising a drain contact metal layer and a drain connected thereto, and a source contact metal layer and a source connected thereto; characterized in that: An N+ type substrate is provided on the side of the drain contact metal layer facing the source contact metal layer, a super junction region is provided on the side of the N+ type substrate facing the source contact metal layer, the super junction region includes an N column and two P columns respectively located on two opposite sides of the N column, the P column includes an upper P column region facing the source contact metal layer and a lower super junction P column region contacting the N+ type substrate, a P well is embedded in the upper P column region, a source region implanted with N+ ions is embedded in the P well, and an isolation oxide layer is provided between the upper P column region and the source contact metal layer; a deep trench is provided on the side of the N column close to the source contact metal layer, a control gate and a shielding gate are provided in the deep trench, and a gate oxide layer is located on the sidewall and bottom of the deep trench and isolates the control gate and the shielding gate; The device has holes on both sides that penetrate the isolation oxide layer and the source region of the N+ ion implantation and extend to the P well, and a P+ ion implantation region is provided in the hole; the source contact metal layer has a conductive structure connected to the P+ ion implantation region along the hole; The N column is aligned with the lower super junction P column region to form a super junction N column region, the bottom of the control gate is in an inverted isosceles trapezoid, and the bottom of the shield gate is in a multi-step shape; The distance between the side of the deep trench facing the drain contact metal layer and the drain contact metal layer is not greater than the distance between the lower super junction P column region and the side of the super junction N column region close to the source contact metal layer and the drain contact metal layer; The widths of the N+ ion-implanted source region, the P well, the upper P column region, and the lower super junction P column region are the same, and the N+ ion-implanted source region, the P well, and the upper P column region are aligned toward the side of the source contact metal layer; The thicknesses of the upper P column region, the lower super junction P column region and the super junction N column region are equal; The doping concentration of the upper P column region is below 2E15, the doping concentration of the lower super junction P column region and the super junction N column region is above 5E15, and the lower super junction P column region and the super junction N column region satisfy an alternating complementary relationship.

2. A method for preparing the novel super junction SGT MOSFET device according to claim 1, characterized in that: The steps include: S1: providing a drain contact metal layer, and growing an N+ type substrate on the drain contact metal layer, the N+ type substrate and the drain contact metal layer form an ohmic contact, and the drain contact metal layer is connected to the drain; S2: growing a high-concentration N-type doped layer on an N+-type substrate; S3: using a trenching process, symmetrically digging deep trenches on both sides of the high-concentration N-type doped layer to obtain two symmetrical deep trenches penetrating the upper and lower surfaces of the high-concentration N-type doped layer, and then performing CVD deposition on the two deep trenches to deposit two layers of P-type impurity silicon with different doping concentrations, namely, a lower super-junction P column region and an upper P column region, wherein the doping concentration of the lower super-junction P column region is greater than that of the upper P column region, thereby forming two symmetrical P column regions; S4: a deep trench is dug in the middle of the high-concentration N-type doped layer to obtain a deep trench penetrating the upper surface of the high-concentration N-type doped layer, and the remaining high-concentration N-type doped layer forms a super-junction N-column region; then an oxide layer is deposited and grown in the deep trench above the super-junction N-column region; S5: growing a layer of polysilicon on the oxide layer by chemical vapor deposition, etching back the polysilicon, and after etching back to a certain depth, starting to perform the first etching back on the oxide layer, and then repeating the above process flow to perform the second etching back until the Nth etching back, and finally obtaining a shielding grid with a multi-step bottom and a side oxide wall around it; S6: thermally oxidizing the polysilicon in the shielding gate to grow an oxide layer, the oxide layer serving as a dielectric isolation layer; S7: depositing polysilicon again and etching back to form a control gate with an inverted isosceles trapezoidal bottom and side oxide walls around it, and the gate oxide layer is completely formed; S8: ion implantation of P-type impurity ions is performed in the two upper P column regions respectively, and high-temperature diffusion is performed to form a P well; S9: ion implanting heavily doped N-type impurities into each P well, and forming two symmetrical N+ ion implanted source regions after annealing; S10: growing an isolation oxide layer on the control gate, the gate oxide layer and the two N+ ion-implanted source regions; S11: using a photolithography process, etching a hole that penetrates the isolation oxide layer and the source region for N+ ion implantation and extends into the P well, and injecting heavily doped P+ ions into two symmetrical holes respectively to form a P+ ion implantation region; S12: depositing a metal aluminum layer on the isolation oxide layer by CVD to form a source contact metal layer, wherein the source contact metal layer has a conductive structure connected to the P+ ion implantation region; The source contact metal layer is connected to the source.

3. A method for preparing a novel super junction SGT MOSFET device according to claim 2, characterized in that: In step S2, the thickness of the high-concentration N-type doping layer is not greater than the maximum depth of the deep trenching process.

4. A method for preparing a novel super junction SGT MOSFET device according to claim 2, characterized in that: The doping types of N-type and P-type silicon are interchanged.

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