Test circuit and chip test method

Abstract

The present application relates to a test circuit and a chip test method, including: an FPGA control module, a power module and at least one digital resistor module, the FPGA control module is used to respond to an input instruction to output a control signal, wherein the input instruction includes target voltage information, each digital resistor module is connected to the FPGA control module and the power module respectively, the digital resistor module is used as a voltage divider element of the power module, and changes the output resistance according to the control signal to adjust the output voltage of the power module so that the output voltage of the power module corresponds to the target voltage information. The test circuit in the present application can change the output voltage according to the test requirements, and the test circuit may include multiple digital resistor modules so as to output multiple different output voltages at the same time, thereby reducing the dependence on the power supply, improving the simplicity of the test circuit, and thus improving the test efficiency.

Description

Technical Field

[0001] The present application relates to the field of testing technology, and in particular to a testing circuit and a chip testing method. Background Art

[0002] The digital signal processing chip can collect various analog signals through sensors, convert the collected analog signals into digital signals through analog-to-digital conversion chips, analyze and calculate the digital signals, and finally output control instructions.

[0003] When performing power supply tolerance testing on digital processing chips, the output voltage of the power supply can be set to test the performance of the digital signal processing chip under different voltages. However, since each tested pin of the digital signal processing chip needs to be configured with an independent power supply, different pins have different requirements for voltage values, resulting in the need for multiple different power supplies for the test circuit, a high reliance on power supplies, complex test circuits, and low test efficiency. Summary of the invention

[0004] Based on this, it is necessary to provide a test circuit and a chip testing method that can reduce the dependence on power supply, so as to reduce the complexity of the circuit.

[0005] Based on the above problems, on the one hand, the present application provides a test circuit, the test circuit comprising: an FPGA control module, a power supply module and at least one digital resistance module;

[0006] The FPGA control module is used to output a control signal in response to an input instruction, wherein the input instruction includes target voltage information;

[0007] Each digital resistor module is connected to the FPGA control module and the power module respectively. The digital resistor module is used as a voltage divider element of the power module and changes the output resistance according to the control signal to adjust the output voltage of the power module so that the output voltage of the power module corresponds to the target voltage information.

[0008] In one embodiment, the power module includes:

[0009] A voltage divider circuit, wherein a first end of the voltage divider circuit is grounded, and a second end of the voltage divider circuit is connected to the digital resistance module;

[0010] The power control circuit is connected to the second end of the voltage divider circuit and the digital resistance module respectively, and is used to output the output voltage according to the potential of the second end of the voltage divider circuit.

[0011] In one embodiment, the number of the digital resistance module is one; the voltage divider circuit includes:

[0012] A first resistor, wherein a first end of the first resistor is connected to a common ground, and a second end of the first resistor is respectively connected to the power control circuit and the digital resistor module.

[0013] In one embodiment, the power control circuit includes: a power control chip, a second resistor, and a first capacitor; wherein, the power feedback pin of the power control chip is connected to the first end of the second resistor, the second end of the second resistor is used to receive a first power signal, and is respectively connected to the first end of the first capacitor and the power end of the power control chip, the second end of the first capacitor is connected to the common ground end, the voltage control pin of the power control chip is respectively connected to the second end of the first resistor and the digital resistor module, the output end of the power control chip is connected to the digital resistor module, and the output end is used to output the output voltage.

[0014] In one embodiment, the power module further includes:

[0015] A feedback circuit is connected to the power control circuit and is used to output a feedback voltage to the power control circuit according to the output voltage output by the power control circuit when the power module is disconnected from the digital resistance module.

[0016] In one embodiment, the feedback circuit includes: a second capacitor, a third resistor, a fourth resistor and a fifth resistor; wherein the first end of the second capacitor is respectively connected to the voltage control pin of the power control chip and the first end of the third resistor, the second end of the second capacitor is connected to the first end of the fourth resistor, the second end of the fourth resistor is respectively connected to the second end of the third resistor and the first end of the fifth resistor, and the second end of the fifth resistor is connected to the output end of the power control chip.

[0017] In one embodiment, the digital resistance module includes: a digital potentiometer and a sixth resistor; wherein the first resistance terminal of the digital potentiometer is connected to the output end of the power control chip, the second resistance terminal of the digital potentiometer is connected to the first end of the sixth resistor, the second end of the sixth resistor is respectively connected to the voltage control pin of the power control chip and the third resistance terminal of the digital potentiometer, and the input end of the digital potentiometer is connected to the FPGA control module.

[0018] In one embodiment, the digital resistor module includes a first digital resistor module and a second digital resistor module; the output voltage includes a first output voltage and a second output voltage; the power control circuit includes: a power control chip, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; wherein the first voltage control pin of the power control chip is respectively connected to the second end of the voltage divider circuit and the first digital resistor module, the first output end of the power control chip is connected to the first end of the seventh resistor, the second end of the seventh resistor is used to output the first output voltage, the first reset end of the power control chip is connected to the first end of the eighth resistor, and the second end of the eighth resistor is connected to the second end of the seventh resistor; the second voltage control pin of the power control chip is respectively connected to the second end of the voltage divider circuit and the second digital resistor module, the second output end of the power control chip is connected to the first end of the ninth resistor, the second end of the ninth resistor is used to output the second output voltage, the second reset end of the power control chip is connected to the first end of the tenth resistor, and the second end of the tenth resistor is connected to the second end of the seventh resistor.

[0019] In one embodiment, the test circuit includes at least one of the following features:

[0020] The first digital resistor module includes: a digital potentiometer, an eleventh resistor, and a twelfth resistor; wherein the first resistor terminal of the digital potentiometer is connected to the second end of the seventh resistor, the second resistor terminal of the digital potentiometer is connected to the first end of the eleventh resistor, the second end of the eleventh resistor is respectively connected to the first end of the twelfth resistor and the third resistor terminal of the digital potentiometer, and the second end of the twelfth resistor is connected to the first voltage control pin of the power control chip;

[0021] The second digital resistor module includes: a digital potentiometer, a thirteenth resistor, and a fourteenth resistor; wherein the third resistor terminal of the digital potentiometer is connected to the second end of the ninth resistor, the second resistor terminal of the digital potentiometer is connected to the first end of the thirteenth resistor, the second end of the thirteenth resistor is respectively connected to the first end of the fourteenth resistor and the first resistor terminal of the digital potentiometer, and the second end of the fourteenth resistor is connected to the second voltage control pin of the power control chip.

[0022] In a second aspect, the present application further provides a chip testing method, which is implemented based on the test circuit described in any one of the embodiments of the present application; the chip testing method comprises:

[0023] Obtain the voltage test requirements of the chip to be tested;

[0024] Acquiring target voltage information according to the voltage test requirement;

[0025] The resistance value of each of the digital resistance modules is controlled according to the target voltage information to adjust the output voltage of the power module so that the output voltage of the power module corresponds to the target voltage information.

[0026] The test circuit and chip test method of the present application include: an FPGA control module, a power module and at least one digital resistor module, the FPGA control module is used to respond to an input instruction to output a control signal, wherein the input instruction includes target voltage information, each digital resistor module is connected to the FPGA control module and the power module respectively, the digital resistor module is used as a voltage divider element of the power module, and changes the output resistance according to the control signal to adjust the output voltage of the power module, so that the output voltage of the power module corresponds to the target voltage information. The present application enables the FPGA module to output a control signal in response to the input instruction, the digital resistor module receives the control signal, and changes the output resistance according to the control signal. Since the digital resistor module is used as a voltage divider element of the power module, when the output resistance of the digital resistor module changes, the voltage divider received by the power module will also change, thereby changing the output voltage, so that the output voltage corresponds to the target voltage information, that is, the test circuit in the present application can change the output voltage according to the test requirements, and the test circuit can include multiple digital resistor modules, so as to output multiple different output voltages at the same time, thereby reducing the dependence on the power supply, improving the simplicity of the test circuit, and thus improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a schematic diagram of the structure of a test circuit provided in an embodiment;

[0029] Figure 2 A schematic diagram of the structure of a test circuit provided in another embodiment;

[0030] Figure 3 A schematic diagram of the structure of a test circuit provided in another embodiment;

[0031] Figure 4 The figure is a flow chart of a chip testing method provided in one embodiment.

[0032] Description of reference numerals:

[0033] 102, FPGA control module; 104, digital resistor module; 106, power module; 108, chip under test; 201, power control circuit; 211, power control chip; 213, digital potentiometer; 223, first digital resistor module; 224, second digital resistor module; 301, voltage divider circuit. DETAILED DESCRIPTION

[0034] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0036] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0037] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0038] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least part of an element” means part or all of an element.

[0039] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0040] In one embodiment, please refer to Figure 1The present application provides a test circuit, which includes: a field programmable gate array (FPGA) control module 102, a power module 106 and at least one digital resistor module 104; the FPGA control module 102 is used to respond to an input instruction to output a control signal, wherein the input instruction includes target voltage information; each digital resistor module 104 is connected to the FPGA control module 102 and the power module 106 respectively, and the digital resistor module 104 is used to serve as a voltage divider element of the power module 106, and changes the output resistance according to the control signal to adjust the output voltage of the power module 106, so that the output voltage of the power module 106 corresponds to the target voltage information.

[0041] The input instruction is an instruction from a host computer or an operator, and the input instruction may be a level signal including target voltage information. The target voltage information may include the voltage value of the output voltage, the number of output voltages, the pins for outputting the output voltages, etc. As an example, when testing the chip 108 to be tested, the output of the control power module 106 is connected to the pin of the chip 108 to be tested.

[0042] In the above embodiment, an FPGA control module, a power module and at least one digital resistor module are provided. The FPGA control module is used to output a control signal in response to an input instruction, wherein the input instruction includes target voltage information. Each digital resistor module is respectively connected to the FPGA control module and the power module. The digital resistor module is used to serve as a voltage divider element of the power module and to change the output resistance according to the control signal to adjust the output voltage of the power module so that the output voltage of the power module corresponds to the target voltage information. The present application enables the FPGA module to output a control signal in response to an input instruction, and the digital resistor module receives the control signal and changes the output resistance according to the control signal. Since the digital resistor module is used as a voltage divider element of the power module, when the output resistance of the digital resistor module changes, the voltage divider received by the power module will also change, thereby changing the output voltage so that the output voltage corresponds to the target voltage information. That is, the test circuit in the present application can change the output voltage according to the test requirements, and the test circuit may include multiple digital resistor modules to output multiple different output voltages at the same time, thereby reducing the dependence on the power supply and improving the simplicity of the test circuit. In addition, the use of the FPGA control module can obtain higher computing speed and response capability, and its parallel processing capability can greatly improve the performance of the test circuit, thereby improving the test efficiency.

[0043] In one embodiment, the power supply module includes: a voltage divider circuit and a power supply control circuit, wherein the first end of the voltage divider circuit is grounded, and the second end of the voltage divider circuit is connected to the digital resistance module; the power supply control circuit is respectively connected to the second end of the voltage divider circuit and the digital resistance module, and is used to output the output voltage according to the potential of the second end of the voltage divider circuit.

[0044] In the above embodiment, since the voltage divider circuit is used as a voltage divider element of the power module, when the output resistance of the digital resistor module changes, the potential of the second end of the voltage divider circuit changes, and the voltage divider received by the power control circuit also changes, thereby changing the output voltage.

[0045] In one embodiment, please refer to Figure 2 , the number of digital resistance modules is one; the voltage divider circuit includes: a first resistor R1; wherein the first end of the first resistor R1 is connected to the common ground GND, and the second end of the first resistor R1 is connected to the power control circuit 201 and the digital resistance module 104 respectively.

[0046] In one embodiment, please continue to refer to Figure 2 The power control circuit includes: a power control chip 211, a second resistor R2, and a first capacitor C1; wherein, a power feedback pin PWROD of the power control chip 211 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is used to receive the first power signal, and is respectively connected to the first end of the first capacitor C1 and the power end of the power control chip 211, the power end includes a first power end VIN1, a second power end VIN2, and a third power end VIN3, and the second end of the first capacitor C1 is connected to the common ground end GND, and the voltage control pin VSENSE of the power control chip 211 is respectively connected to the second end of the first resistor R1 and the digital resistor module 104, and the output end of the power control chip 211 (including a first output end PH1, a second output end PH2, a third output end PH3, a fourth output end PH4, and a fifth output end PH5) is connected to the digital resistor module 104, and the output end is used to output the output voltage.

[0047] As an example, the first power signal is used to provide the power control chip 211 with the voltage required for operation, the power end of the power control chip 211 is used to receive the first power signal to put the power control chip 211 in a working state, the power feedback pin PWROD is used to receive the sampling signal of the power end, so as to monitor the voltage of the power end to determine whether the working state of the power control chip 211 is normal, the second resistor R2 is a sampling resistor, which is used to convert the first power signal into a sampling signal, the first capacitor C1 is used to filter the first power signal to improve the stability of the first power signal, and the power control chip 211 is used to output the output voltage according to the potential of the second end of the first resistor R1. Among them, the voltage value of the first power signal can be +5V. The present application does not make specific restrictions on the voltage value of the first power signal, and the first power signal can be set according to the power control chip 211.

[0048] In one embodiment, the power module also includes: a feedback circuit; the feedback circuit is connected to the power control circuit, and is used to output a feedback voltage to the power control circuit according to the output voltage output by the power control circuit when the power module is disconnected from the digital resistance module.

[0049] As an example, the first end of the feedback circuit is connected to the voltage control pin of the power control chip of the power control circuit, and the second end of the feedback circuit is connected to the output end of the power control chip. The feedback circuit may include multiple resistors to adjust the feedback voltage to a voltage value that matches the voltage control pin.

[0050] In one embodiment, please continue to refer to Figure 2 The feedback circuit includes: a second capacitor C2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5; wherein the first end of the second capacitor C2 is respectively connected to the voltage control pin VSENSE of the power control chip 211 and the first end of the third resistor R3, the second end of the second capacitor C2 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is respectively connected to the second end of the third resistor R3 and the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the output end of the power control chip 211.

[0051] In the above embodiment, by making the feedback circuit include the second capacitor C2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5, while outputting a suitable feedback voltage, the feedback voltage can also change slowly, playing a buffering role, thereby preventing sudden changes in the feedback voltage from affecting the power control chip 211.

[0052] In one embodiment, please continue to refer to Figure 2 The digital resistor module includes: a digital potentiometer 213 and a sixth resistor R6; wherein, the first resistor terminal A of the digital potentiometer 213 is connected to the output end of the power control chip 211, the second resistor terminal W of the digital potentiometer 213 is connected to the first end of the sixth resistor R6, the second end of the sixth resistor R6 is respectively connected to the voltage control pin VSENSE of the power control chip 211 and the third resistor terminal B of the digital potentiometer 213, and the input end DIN of the digital potentiometer 213 is connected to the FPGA control module 102.

[0053] As an example, the reset pin *RESET, the working status pin RDY, the serial data output pin SDO, the falling edge synchronization pin *SYNC, and the clock pin SCLK of the digital potentiometer 213 can all be connected to the FPGA control module 102 .

[0054] As an example, the digital potentiometer 213 and the first resistance terminal A are connected to the output end of the power control chip 211 through the connection interface 205, and the connection interface 205 can be disconnected when no test is required. When the first resistance terminal A of the digital potentiometer 213 is connected to the output end of the power control chip 211, the first resistor R1, the sixth resistor R6, and the resistance between the first resistance terminal A and the second resistance terminal W, and the resistance between the second resistance terminal W and the third resistance terminal B jointly participate in the voltage division, and the potential of the second end of the first resistor R1 is changed by adjusting the resistance between the first resistance terminal A and the second resistance terminal W, and the resistance between the second resistance terminal W and the third resistance terminal B. In addition, the first power supply terminal VDD and the second power supply terminal VLOGIC of the digital potentiometer 213 are connected to the second power supply signal, and the voltage value of the second power supply signal can be 3V. Among them, the chip model of the digital potentiometer can adopt multiple models such as AD5292.

[0055] In one embodiment, please refer to Figure 3 The voltage divider circuit includes: a fifteenth resistor R15; wherein a first end of the fifteenth resistor R15 is connected to the common ground GND, and a second end of the fifteenth resistor R15 is connected to the power control circuit 201 and the digital resistor module 104 respectively.

[0056] In one embodiment, please continue to refer to Figure 3 , the digital resistor module 104 includes a first digital resistor module 223; the output voltage includes a first output voltage DV3.3; the power control circuit 201 includes: a power control chip 221, a seventh resistor, and an eighth resistor; wherein the first voltage control pin Vsns1 / FB1 of the power control chip is respectively connected to the second end of the voltage divider circuit 301 and the first digital resistor module 223, the first output end Vout1 of the power control chip is connected to the first end of the seventh resistor R7, the second end of the seventh resistor R7 is used to output the first output voltage DV3.3, the first reset end of the power control chip 211 The first end of the eighth resistor R8 is connected to the second end of the seventh resistor R7. In other embodiments, other power control chips can be selected according to the test requirements of the chip to be tested.

[0057] In the above embodiment, by setting the seventh resistor R7, the fault can be isolated when the circuit of the chip under test, the digital resistor module 104, etc. fails to avoid affecting the power control chip 211. The eighth resistor R8 is used as a pull-up resistor to pull up the first reset terminal. The potential.

[0058] In one embodiment, please continue to refer to Figure 3The first digital resistor module 223 includes: a digital potentiometer 213, an eleventh resistor R11, and a twelfth resistor R12; wherein the first resistor terminal A of the digital potentiometer 213 is connected to the second end of the seventh resistor R7, the second resistor terminal W of the digital potentiometer 213 is connected to the first end of the eleventh resistor R11, the second end of the eleventh resistor R11 is respectively connected to the first end of the twelfth resistor R12 and the third resistor terminal B of the digital potentiometer 213, and the second end of the twelfth resistor R12 is connected to the first voltage control pin Vsns1 / FB1 of the power control chip 211.

[0059] As an example, the reset pin *RESET, working status pin RDY, serial data output pin SDO, falling edge synchronization pin *SYNC, and clock pin SCLK of the digital potentiometer 213 can all be connected to the FPGA control module 102, and the logic power interface VLOGIC and the power supply interface VDD are connected to the second end of the seventh resistor R7.

[0060] As an example, the voltage divider circuit 301, the eleventh resistor R11, the twelfth resistor R12, and the resistance between the first resistor terminal A and the second resistor terminal W, and the resistance between the second resistor terminal W and the third resistor terminal B jointly participate in voltage division, and the potential of the second end of the voltage divider circuit 301 is changed by adjusting the resistance between the first resistor terminal A and the second resistor terminal W, and the resistance between the second resistor terminal W and the third resistor terminal B.

[0061] In one embodiment, please continue to refer to Figure 3 The voltage divider circuit 301 includes: a sixteenth resistor R16; wherein a first end of the sixteenth resistor R16 is connected to the common ground GND, and a second end of the sixteenth resistor R16 is connected to the power control circuit 201 and the digital resistor module 104 respectively.

[0062] In one embodiment, please continue to refer to Figure 3 , the digital resistor module 104 includes a second digital resistor module 224; the output voltage includes a second output voltage DV1.2; the power control circuit 201 includes: a power control chip 211, a ninth resistor R9, and a tenth resistor R10; wherein the second voltage control pin Vsns2 / FB2 of the power control chip 201 is respectively connected to the second end of the voltage divider circuit 301 and the second digital resistor module 224, the second output end Vout2 of the power control chip 211 is connected to the first end of the ninth resistor R9, the second end of the ninth resistor R9 is used to output the second output voltage DV1.2, and the second reset end of the power control chip 211 The first end of the tenth resistor R10 is connected to the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is connected to the second end of the seventh resistor R7.

[0063] In the above embodiment, by setting the ninth resistor, the fault can be isolated when the circuit of the chip under test, the digital resistor module, etc. fails to avoid affecting the power control chip. The tenth resistor R10 is used as a pull-up resistor to pull up the second reset terminal. The potential.

[0064] In one embodiment, the second digital resistor module includes: a digital potentiometer 213, a thirteenth resistor R13, and a fourteenth resistor R14; wherein the third resistor terminal B of the digital potentiometer 213 is connected to the second end of the ninth resistor R9, the second resistor terminal W of the digital potentiometer 213 is connected to the first end of the thirteenth resistor R13, the second end of the thirteenth resistor R13 is respectively connected to the first end of the fourteenth resistor R14 and the first resistor terminal A of the digital potentiometer, and the second end of the fourteenth resistor R14 is connected to the second voltage control pin Vsns2 / FB2 of the power control chip 211.

[0065] As an example, the voltage divider circuit 301, the thirteenth resistor R13, the fourteenth resistor R14, and the resistance between the first resistor terminal A and the second resistor terminal W, and the resistance between the second resistor terminal W and the third resistor terminal B jointly participate in voltage division, and the potential of the second end of the voltage divider circuit 301 is changed by adjusting the resistance between the first resistor terminal A and the second resistor terminal W, and the resistance between the second resistor terminal W and the third resistor terminal B.

[0066] In one embodiment, the power module further includes: a filter circuit, which is connected to the output end of the power control chip and is used to filter the output voltage of the power control chip.

[0067] In one embodiment, please continue to refer to Figure 2 The filtering circuit includes: a first inductor L1, a third capacitor C3 and a fourth capacitor C4; wherein, the first end of the first inductor L1 is connected to the output end of the power control chip 211, the second end of the first inductor L1 is respectively connected to the first end of the third capacitor C3 and the first end of the fourth capacitor C4, the second end of the third capacitor C3 is respectively connected to the second end of the fourth capacitor C4 and the common ground GND; wherein, the second end of the first inductor L1 is connected to the chip under test 108.

[0068] In one embodiment, please continue to refer to Figure 3 The filtering circuit includes: a fifth capacitor C5 and a sixth capacitor C6; wherein, a first end of the fifth capacitor C5 is connected to a second end of the seventh resistor R7, and a second end of the fifth capacitor C5 is connected to a common ground terminal GND; a first end of the sixth capacitor C6 is connected to a second end of the ninth resistor R9, and a second end of the sixth capacitor C6 is connected to a common ground terminal GND.

[0069] In one embodiment, the power control circuit further includes: a seventh capacitor C7 and an eighth capacitor C8; wherein the first end of the seventh capacitor C7 is respectively connected to the first end of the eighth capacitor C8 and the power end of the power control chip 211 (including the first power end Vin1 and the second power end Vin1), and the second end of the seventh capacitor C7 is respectively connected to the second end of the eighth capacitor C8 and the common ground end GND.

[0070] In one embodiment, the test circuit also includes: a seventeenth resistor R17, an eighteenth resistor R18, a first light-emitting diode DV1, and a second light-emitting diode DV2; wherein, the first end of the seventeenth resistor R17 is connected to the second end of the seventh resistor R7, the second end of the seventeenth resistor R17 is connected to the positive electrode of the first light-emitting diode DV1, and the negative electrode of the first light-emitting diode DV1 is connected to the common ground terminal GND; the first end of the eighteenth resistor R18 is connected to the power supply terminal of the power control chip 211, the second end of the eighteenth resistor R18 is connected to the positive electrode of the second light-emitting diode DV2, and the negative electrode of the second light-emitting diode DV2 is connected to the common ground terminal GND.

[0071] In the above embodiment, whether the voltages at the first output terminal Vout1 and the power terminal of the power control chip 211 are normal can be determined by the light emitting states of the first light emitting diode DV1 and the second light emitting diode DV2 .

[0072] In one embodiment, please refer to Figure 4 The present application also provides a chip testing method, which is implemented based on the test circuit of any one of the embodiments of the present application; the chip testing method includes: step S402-step S406.

[0073] Step S402: Obtain voltage test requirements of the chip to be tested.

[0074] As an example, the voltage test requirement may be the power port characteristics of the chip under test, such as the number of power supplies required by the chip under test, the power supply voltage required by the chip under test, etc. A suitable power control chip and digital potentiometer may be designed according to the number of power supplies required by the chip under test.

[0075] Step S404: acquiring target voltage information according to voltage test requirements.

[0076] As an example, target voltage information, such as a voltage value of an output voltage and a quantity of an output voltage, is acquired according to a voltage test requirement of the chip to be tested.

[0077] Step S406: controlling the resistance of each digital resistance module according to the target voltage information to adjust the output voltage of the power module so that the output voltage of the power module corresponds to the target voltage information.

[0078] As an example, the resistance value of the output resistor to be output by the digital resistor module is determined according to the voltage value of the output voltage and the circuit structure of the power module and the digital resistor module, and then the corresponding resistance value output by each digital resistor module is controlled, so that the output voltage of the power module corresponds to the target voltage information, and the test program corresponding to the chip to be tested is run in the FPGA control module to complete the test of the chip to be tested.

[0079] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0080] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A test circuit, characterized in that: The test circuit includes: an FPGA control module, a power supply module and at least one digital resistance module; The FPGA control module is used to output a control signal in response to an input instruction, wherein the input instruction includes target voltage information; Each digital resistance module is connected to the FPGA control module and the power module respectively, and the digital resistance module is used as a voltage divider element of the power module, and changes the output resistance value according to the control signal to adjust the output voltage of the power module so that the output voltage of the power module corresponds to the target voltage information; Wherein, the power module comprises: A voltage divider circuit, wherein a first end of the voltage divider circuit is grounded, and a second end of the voltage divider circuit is connected to the digital resistance module; A power control circuit, connected to the second end of the voltage divider circuit and the digital resistance module respectively, and configured to output the output voltage according to the potential of the second end of the voltage divider circuit; The digital resistor module includes a first digital resistor module and a second digital resistor module; the output voltage includes a first output voltage and a second output voltage; the power control circuit includes: a power control chip, a seventh resistor, an eighth resistor, a ninth resistor, and a tenth resistor; wherein the first voltage control pin of the power control chip is respectively connected to the second end of the voltage divider circuit and the first digital resistor module, the first output end of the power control chip is connected to the first end of the seventh resistor, the second end of the seventh resistor is used to output the first output voltage, the first reset end of the power control chip is connected to the first end of the eighth resistor, and the second end of the eighth resistor is connected to the second end of the seventh resistor; the second voltage control pin of the power control chip is respectively connected to the second end of the voltage divider circuit and the second digital resistor module, the second output end of the power control chip is connected to the first end of the ninth resistor, the second end of the ninth resistor is used to output the second output voltage, the second reset end of the power control chip is connected to the first end of the tenth resistor, and the second end of the tenth resistor is connected to the second end of the seventh resistor; The test circuit includes at least one of the following features: The first digital resistor module includes: a digital potentiometer, an eleventh resistor, and a twelfth resistor; wherein the first resistor terminal of the digital potentiometer is connected to the second end of the seventh resistor, the second resistor terminal of the digital potentiometer is connected to the first end of the eleventh resistor, the second end of the eleventh resistor is respectively connected to the first end of the twelfth resistor and the third resistor terminal of the digital potentiometer, and the second end of the twelfth resistor is connected to the first voltage control pin of the power control chip; The second digital resistor module includes: a digital potentiometer, a thirteenth resistor, and a fourteenth resistor; wherein the third resistor terminal of the digital potentiometer is connected to the second end of the ninth resistor, the second resistor terminal of the digital potentiometer is connected to the first end of the thirteenth resistor, the second end of the thirteenth resistor is respectively connected to the first end of the fourteenth resistor and the first resistor terminal of the digital potentiometer, and the second end of the fourteenth resistor is connected to the second voltage control pin of the power control chip; The voltage divider circuit includes: a fifteenth resistor and a sixteenth resistor, wherein a first end of the fifteenth resistor is connected to a common ground terminal, and a second end of the fifteenth resistor is respectively connected to a power control circuit and a digital resistor module; a first end of the sixteenth resistor is connected to a common ground terminal, and a second end of the sixteenth resistor is respectively connected to a power control circuit and a digital resistor module; The power control circuit further includes: a seventh capacitor and an eighth capacitor; the first end of the seventh capacitor is respectively connected to the first end of the eighth capacitor and the power end of the power control chip, and the second end of the seventh capacitor is respectively connected to the second end of the eighth capacitor and the common ground end; The test circuit also includes: a seventeenth resistor, an eighteenth resistor, a first light-emitting diode, and a second light-emitting diode; the first end of the seventeenth resistor is connected to the second end of the seventh resistor, the second end of the seventeenth resistor is connected to the positive electrode of the first light-emitting diode, and the negative electrode of the first light-emitting diode is connected to the common ground terminal; the first end of the eighteenth resistor is connected to the power supply terminal of the power control chip, the second end of the eighteenth resistor is connected to the positive electrode of the second light-emitting diode, and the negative electrode of the second light-emitting diode is connected to the common ground terminal.

2. The test circuit according to claim 1, characterized in that: The number of the digital resistance module is one; the voltage divider circuit comprises: A first resistor, wherein a first end of the first resistor is connected to a common ground, and a second end of the first resistor is respectively connected to the power control circuit and the digital resistor module.

3. The test circuit according to claim 2, characterized in that: The power control circuit includes: a power control chip, a second resistor, and a first capacitor; wherein, a power feedback pin of the power control chip is connected to the first end of the second resistor, the second end of the second resistor is used to receive a first power signal, and is respectively connected to the first end of the first capacitor and the power end of the power control chip, the second end of the first capacitor is connected to the common ground end, the voltage control pin of the power control chip is respectively connected to the second end of the first resistor and the digital resistor module, the output end of the power control chip is connected to the digital resistor module, and the output end is used to output the output voltage.

4. The test circuit according to claim 3, characterized in that: The power module also includes: A feedback circuit is connected to the power control circuit and is used to output a feedback voltage to the power control circuit according to the output voltage output by the power control circuit when the power module is disconnected from the digital resistance module.

5. The test circuit according to claim 4, characterized in that: The feedback circuit includes: a second capacitor, a third resistor, a fourth resistor and a fifth resistor; wherein the first end of the second capacitor is respectively connected to the voltage control pin of the power control chip and the first end of the third resistor, the second end of the second capacitor is connected to the first end of the fourth resistor, the second end of the fourth resistor is respectively connected to the second end of the third resistor and the first end of the fifth resistor, and the second end of the fifth resistor is connected to the output end of the power control chip.

6. The test circuit according to claim 3, characterized in that: The digital resistor module includes: a digital potentiometer and a sixth resistor; wherein the first resistor terminal of the digital potentiometer is connected to the output end of the power control chip, the second resistor terminal of the digital potentiometer is connected to the first end of the sixth resistor, the second end of the sixth resistor is respectively connected to the voltage control pin of the power control chip and the third resistor terminal of the digital potentiometer, and the input end of the digital potentiometer is connected to the FPGA control module.

7. A chip testing method, characterized in that: Based on the test circuit implementation according to any one of claims 1 to 6; the chip testing method comprises: Obtain the voltage test requirements of the chip to be tested; Acquiring target voltage information according to the voltage test requirement; The resistance value of each of the digital resistance modules is controlled according to the target voltage information to adjust the output voltage of the power module so that the output voltage of the power module corresponds to the target voltage information.

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