Hardware Emulation Trigger System Based on Programmable Boolean Processor

Abstract

The present invention relates to the field of computer technology, and particularly to a hardware simulation trigger system based on a programmable Boolean processor, which includes a host computer, a programmable Boolean processor, and M FPGAs; the host computer is used to obtain pre-generated trigger state machine code, compile it into a bit map file of the Boolean processor, and download it to the programmable Boolean processor; it is also used to load the DUT database on all F m ; the host computer is further used to run a test program and set the states of the programmable Boolean processor and F m to the working state; F m is used to collect DUT signals based on a hardware simulation clock in the working state; the programmable Boolean processor is used to run the bit map file of the Boolean processor in the working state and obtain the DUT signals collected by F m in real time. When the DUT signals collected by F m conform to the preset trigger logic, a trigger signal is sent to the corresponding F m . The present invention reduces the compilation time cost of modifying the trigger state machine.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a hardware simulation trigger system based on a programmable Boolean processor. Background Art

[0002] In an existing Field-Programmable Gate Array (FPGA) hardware simulation system, during the process of capturing the waveform of a Design Under Test (DUT) signal, triggering is required to capture the exact position of the waveform intended for debugging. Most of the implementations of such triggering in FPGA adopt the following two methods: (1) Insert a trigger logic circuit into the DUT before compilation. (2) Insert a pre-compiled customized programmable trigger IP (Intellectual Property) into the DUT netlist after compilation.

[0003] Method (1) can use languages such as Specification and Description Language (SDL) or Verilog to implement complex trigger state machine conditions. However, these complex trigger conditions cannot be modified after compilation. If the trigger state machine needs to be modified, the entire DUT database has to be recompiled, which requires a huge compilation time cost. Method (2) inserts a pre-compiled customized programmable trigger IP into the DUT netlist after compilation. Although the trigger IP supports a certain degree of reprogramming of the trigger state machine and does not require recompiling the DUT database to modify the trigger conditions within a certain range. However, the setting of the trigger conditions of such a state machine is relatively poor in supporting languages such as SDL or Verilog, or requires a large development cost to support, which is inconvenient to use and the support for trigger conditions is limited by the IP design definition. It can be seen that how to support languages such as SDL or Verilog to implement various complex state machines or trigger conditions and reduce the compilation time cost of modifying the trigger state machine has become a technical problem to be solved urgently. Summary of the Invention

[0004] The object of the present invention is to provide a hardware simulation trigger system based on a programmable Boolean processor, which can support languages such as SDL or Verilog to implement various complex state machines or trigger conditions, and has a low compilation time cost for modifying the trigger state machine.

[0005] According to a first aspect of the present invention, there is provided a hardware simulation trigger system based on a programmable Boolean processor, including a host computer, a programmable Boolean processor, and M FPGAs {F1, F2,..., F m ,..., F M}, where F m is the m-th FPGA, where m ranges from 1 to M, and M is the total number of FPGAs. The programmable Boolean processor is respectively connected to the host computer and each F m ;

[0006] The host computer is used to obtain the pre-generated trigger state machine code, compile the trigger state machine code into a bit map file of the Boolean processor, and download the bit map file of the Boolean processor to the programmable Boolean processor. The trigger state machine code is generated based on a preset trigger logic and includes a state machine code and a trigger condition code;

[0007] The host computer is also used to load the DUT database on all F m ;

[0008] The initial states of the programmable Boolean processor and F m are both non-working states;

[0009] The host computer is also used to run a test program and set the states of the programmable Boolean processor and F m to working states;

[0010] F m is used to collect DUT signals based on a hardware simulation clock in the working state;

[0011] The programmable Boolean processor is used to run the bit map file of the Boolean processor in the working state and obtain the DUT signals collected by F m in real time. When the DUT signals collected by F m meet the preset trigger logic, a trigger signal is sent to the corresponding F m to trigger the corresponding F m to perform a preset operation.

[0012] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, a hardware simulation trigger system based on a programmable Boolean processor provided by the present invention can achieve considerable technical progressiveness and practicality, and has wide industrial utilization value. It has at least the following beneficial effects:

[0013] The present invention obtains the pre-generated trigger state machine code through the host computer, compiles and generates a bit map file of the Boolean processor, and downloads the bit map file of the Boolean processor to the programmable Boolean processor. The programmable Boolean processor supports implementing various complex state machines or trigger conditions using languages such as SDL or Verilog. When the state machine or trigger condition changes, only the state machine code needs to be recompiled, without having to recompile the huge DUT database. Therefore, the compilation time cost of modifying the trigger state machine is greatly reduced. Brief Description of the Drawings

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 Schematic diagram of the hardware simulation trigger system based on a programmable Boolean processor provided by an embodiment of the present invention. Detailed Embodiments

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0017] An embodiment of the present invention provides a hardware simulation trigger system based on a programmable Boolean processor, as Figure 1 shown, including a host computer (Host PC), a programmable Boolean processor (BP), and M FPGAs {F1, F2,..., F m ,..., F M}, where F m is the m-th FPGA, the value range of m is from 1 to M, and M is the total number of FPGAs. The programmable Boolean processor is respectively connected to the host computer and each F m .

[0018] The host computer is used to obtain the pre-generated trigger state machine code, compile the trigger state machine code into a bit map file (Bit Map) of the Boolean processor, and download the bit map file of the Boolean processor to the programmable Boolean processor. The trigger state machine code is generated based on a preset trigger logic and includes a state machine code and a trigger condition code. Among them, the host computer includes a Boolean processor compiler (BP Compiler), and the Boolean processor compiler is used to compile the pre-generated trigger state machine code to generate a bit map file of the Boolean processor. It should be noted that the compilation speed of the Boolean processor compiler can reach 10,000 logic gates per second, and the compilation time can be almost ignored.

[0019] The host computer is also used to load the DUT database on all F m , and it should be noted that the DUT database includes DUT circuit data. On all Fm Loading the DUT database onto the FPGA means loading the DUT circuit data corresponding to each FPGA m onto the FPGA, so that M FPGAs form the hardware simulation architecture of the DUT. m The initial states of the programmable Boolean processor and the FPGA

[0020] are both in the non - working state. m The host computer is also used to run a test program and set the states of the programmable Boolean processor and the FPGA

[0021] to the working state. Specifically, the test program can be a user - written test program based on the DUT. When running the test program, it is necessary to set the states of the programmable Boolean processor and the FPGA m to the working state. It can be understood that before setting the states of the programmable Boolean processor and the FPGA m to the working state, the bit - mapped file of the Boolean processor is downloaded to the programmable Boolean processor and all FPGAs m and the operation of loading the DUT database onto the FPGA has been completed. m The FPGA is used to collect DUT signals based on the hardware simulation clock in the working state.

[0022] The FPGA m is used to collect DUT signals based on the hardware simulation clock in the working state.

[0023] The programmable Boolean processor is used to run the bit - mapped file of the Boolean processor in the working state and obtain the DUT signals collected by the FPGA in real - time. When the DUT signals collected by the FPGA m meet the preset trigger logic, a trigger signal is sent to the corresponding FPGA m to trigger the corresponding FPGA m to perform the preset operation. Since the trigger state - machine code is generated based on the preset trigger logic, including the state - machine code and the trigger - condition code, when running the Boolean processor, using the DUT signals collected by the FPGA m as the input signal, it can be determined whether the state - machine meets the trigger condition. If it does, it means that the DUT signals collected by the FPGA m meet the preset trigger logic. m As an embodiment, the programmable Boolean processor includes a control unit and a Boolean unit. The control unit is used to control the Boolean unit to perform a series of operations. Specifically, the control unit is used to control the Boolean unit to run the bit - mapped file of the Boolean processor in the working state and obtain the DUT signals collected by the FPGA in real - time. The control unit is also used to judge whether the DUT signals collected by the FPGA

[0024] meet the preset trigger logic. When the DUT signals collected by the FPGA m meet the preset trigger logic. The control unit is also used to judge whether the DUT signals collected by the FPGA m meet the preset trigger logic. When the DUT signals collected by the FPGA mWhen the collected DUT signal conforms to the preset trigger logic, the control Boolean unit sends a trigger signal to the corresponding F m to trigger the corresponding F m to perform the preset operation. It should be noted that the programmable Boolean processor supports implementing various complex state machines or trigger conditions using languages such as SDL or Verilog. Therefore, the pre-generated trigger state machine code is generated based on languages such as SDL or Verilog.

[0025] As an embodiment, F m includes a sampling bridge (Probe Bridger), and the sampling bridge is used to collect DUT signals based on the hardware simulation clock in the working state.

[0026] As an embodiment, the system further includes a first pipeline trigger and a second pipeline trigger. Both the first pipeline trigger and the second pipeline trigger are pipeline triggers (Pipe-Line FFs), but they have different functions. The first pipeline trigger is used to ensure the accuracy of the sampled data, and the second pipeline trigger is used to adjust the transmission path delay.

[0027] If the transmission path delay Ft m from F to the programmable Boolean processor m is greater than the hardware simulation clock cycle T, then X m first pipeline triggers need to be inserted on the transmission path from F m to the programmable Boolean processor to ensure the accuracy of the sampled data. Among them, the i-th first pipeline trigger is inserted at the sampling position of the i×T of the transmission path delay from F m to the programmable Boolean processor, and the value range of i is from 1 to X m .

[0028] After all the first pipeline triggers are inserted, since the lengths of the transmission paths from F m to the programmable Boolean processor are different, therefore, the number of triggers included in the transmission path from F m to the programmable Boolean processor after inserting the first pipeline trigger will also be different. In order to balance the problem of unequal transmission path delays of each F m to the programmable Boolean processor, the way of inserting the second pipeline trigger can be used to compensate the path with a shorter delay to be equal to the path with a longer delay. Specifically, the maximum value MX m of X x and the total number Y m of triggers included in the current transmission path from each F m, and then insert MX m into the transmission path from F x to the programmable Boolean processor m -Y Figure 1 second pipeline flip-flops. It should be noted that m is only a schematic diagram, only showing the connection relationship between F m and the programmable Boolean processor, and does not mean that the transmission path lengths from each F m to the programmable Boolean processor are equal, and the distances from each F

[0029] to the programmable Boolean processor may be different. m As an embodiment, the system further includes a time-division multiplexing module disposed between the programmable Boolean processor and F m for transmitting the DUT signals collected by F m to the programmable Boolean processor in a time-division multiplexing manner. It should be noted that the number of DUT signals collected by F

[0030] at the same time may be relatively large. In order to avoid an excessive number of DUT signals being transmitted to the programmable Boolean processor at the same time, based on the time-division multiplexing module, the DUT signals can be reasonably transmitted to the programmable Boolean processor in a time-division multiplexing manner, thereby improving the system performance. It should be noted that the time-division multiplexing module can be specifically implemented by using existing time-division multiplexing technologies, which will not be elaborated here.

[0031] As an embodiment, when the preset trigger logic changes, the host computer is used to obtain the updated trigger state machine code, compile the updated trigger state machine code into an updated bit map file of the Boolean processor, and download the updated bit map file of the Boolean processor to the programmable Boolean processor. The updated trigger state machine code is generated based on the changed preset trigger logic. It should be noted that when the preset trigger logic changes, only the trigger state machine code needs to be updated, the trigger state machine code is recompiled, and the updated bit map file of the Boolean processor is downloaded to the programmable Boolean processor. There is no need to recompile the huge DUT database. Moreover, since the compilation speed of the Boolean processor compiler can reach 10,000 logic gates per second and the compilation time can be almost ignored, the system of the present invention only needs a very small time cost to quickly update the trigger state machine when the preset trigger logic changes, and realizes the update of the entire hardware simulation trigger system.

[0032] In the embodiment of the present invention, a programmable Boolean processor is used to replace the customized programmable trigger IP in the method (2) mentioned in the background art, thereby integrating the advantages of the methods (1) and (2) mentioned in the background art, solving the disadvantages of the methods (1) and (2) mentioned in the background art. The trigger state machine code pre-generated is obtained through the host computer, and a bit map file of the Boolean processor is compiled and generated. The bit map file of the Boolean processor is downloaded to the programmable Boolean processor, and the programmable Boolean processor supports implementing various complex state machines or trigger conditions using languages such as SDL or Verilog. When the state machine or trigger condition changes, only the state machine code needs to be recompiled, without the need to recompile the huge DUT database, so the compilation time cost of modifying the trigger state machine is greatly reduced.

[0033] The above are only preferred embodiments of the present invention and do not impose any formal limitations on the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A hardware simulation trigger system based on a programmable Boolean processor, characterized in that: It includes a host computer, a programmable Boolean processor, M FPGAs {F1, F2, ..., F m ,...,F M }, where F m is the mth FPGA, the value range of m is 1 to M, M is the total number of FPGAs, and the programmable Boolean processor communicates with the host computer and each F m connected; The host computer is used to obtain a pre-generated trigger state machine code, compile the trigger state machine code into a bit map file of a Boolean processor, and download the bit map file of the Boolean processor to the programmable Boolean processor, wherein the trigger state machine code is generated based on a preset trigger logic and includes a state machine code and a trigger condition code; The host computer is also used in all F m The DUT database includes the DUT circuit data. m Load the DUT database and set each F m The corresponding DUT circuit data is loaded into F m Thus, M FPGAs constitute the hardware simulation architecture of the DUT; The programmable Boolean processor and F m The initial state is non-working state; The host computer is also used to run the test program and programmable Boolean processor and F m The status is set to working status; F m Used to collect DUT signals based on hardware simulation clock in working state; The programmable Boolean processor is used to run the bit map file of the Boolean processor in a working state and obtain F in real time. m The collected DUT signal, when F m When the collected DUT signal meets the preset trigger logic, it sends a trigger to the corresponding F m Send a trigger signal to trigger the corresponding F m Execute the preset operation; When the preset trigger logic changes, the host computer is used to obtain an updated trigger state machine code, compile the updated trigger state machine code into a bit map file of an updated Boolean processor, and download the updated bit map file of the Boolean processor to the programmable Boolean processor. The updated trigger state machine code is generated based on the changed preset trigger logic.

2. The system according to claim 1, characterized in that The programmable Boolean processor comprises a control unit and a Boolean unit, wherein: The control unit is used to control the Boolean unit to run the bit map file of the Boolean processor in the working state, and obtain the F m The collected DUT signal; The control unit is also used to determine F m Whether the collected DUT signal meets the preset trigger logic, when F m When the collected DUT signal meets the preset trigger logic, the Boolean unit is controlled to the corresponding F m Send a trigger signal to trigger the corresponding F m Executes the preset action.

3. The system according to claim 1, characterized in that F m It includes a sampling bridge, which is used to collect DUT signals based on a hardware simulation clock in a working state.

4. The system according to claim 1, characterized in that The system further comprises a first pipeline trigger and a second pipeline trigger, wherein the first pipeline trigger is used to ensure the accuracy of the sampled data, and the second pipeline trigger is used to adjust the transmission path delay; If F m Transmission path delay Ft to programmable Boolean processor m is greater than the hardware simulation clock period T, then at F m Insert X on the transmission path to the programmable Boolean processor m The first pipeline flip-flop, Among them, in F m The transmission path delay to the programmable Boolean processor is inserted into the i-th first pipeline trigger at the i×T sampling position, where the value of i ranges from 1 to X m ; After all first pipeline triggers are inserted, obtain X m The maximum value of MX x And each current F m The total number of flip-flops contained in the transmission path to the programmable Boolean processor is Y m , in F m Insert MX in the transmission path to the programmable Boolean processor x -Y m A second pipeline trigger.

5. The system according to claim 1, characterized in that The system also includes a programmable Boolean processor and an F m The time division multiplexing module between F m The collected DUT signals are transmitted to the programmable Boolean processor in a time-division multiplexing manner.

6. The system according to claim 1, characterized in that The pre-generated trigger state machine code is generated based on SDL or Verilog language.

7. The system according to claim 1, characterized in that The preset operations include stopping the hardware simulation clock signal and triggering the waveform capture operation.

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