Chip coarse-grained partitioning method and system based on resource and port semaphore

Abstract

The application discloses a chip coarse-grained partitioning method and system based on resources and port signal quantities, and comprises the following steps: determining coarse-grained modules in a chip design under test (DUT); expanding the coarse-grained modules to construct a coarse-grained connection relationship graph, and obtaining port signal quantities between the coarse-grained modules; obtaining the number of interconnection channels between each FPGA chip in an FPGA verification platform; if the number of interconnection channels between each two FPGA chips is the same, then the nodes in the coarse-grained connection relationship graph are blocked with the maximum value of the sum of signal edge weights between the blocks as the target; otherwise, the nodes in the coarse-grained connection relationship graph are blocked with the sum of signal edge weights between the blocks as small as possible as the target to obtain a coarse-grained partitioning result. The application aims to improve the efficiency and performance of coarse-grained partitioning when a large-scale chip is mapped to different FPGAs for prototype verification.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of prototype verification of large-scale chips, and in particular to a chip coarse-grained partitioning method and system based on resource and port signal quantity. BACKGROUND

[0002] With the design scale of chips becoming larger and larger, single FPGA cannot meet the prototype verification needs of large-scale chips due to resource limitations. Therefore, multiple FPGAs need to be interconnected to build a larger prototype verification system. At this time, the large-scale chip design needs to be partitioned, and the partitioned blocks are mapped to different FPGAs, and the signals between the partitioned blocks are transmitted through the interconnection channels between FPGAs.

[0003] The traditional partitioning method is to first synthesize the user design into a netlist, abstract the netlist into an undirected graph with edge weights and node weights to represent it, and then use graph partitioning algorithms for partitioning. The principle is that the total amount of resources of each partitioned block does not exceed the threshold value of a single FPGA, and the sum of the weights of the edges between the partitioned blocks is as small as possible, and the sum of the edge weights between the global partitioned blocks is as balanced as possible. The partitioning based on the netlist is actually a large graph partitioning problem. Since graph partitioning is an NP-complete problem, it is difficult to solve. The mainstream solutions include Metis partitioning algorithm, parallel algorithm PMetis derived from Metis, and hypergraph partitioning algorithm HMetis. However, as the circuit scale becomes larger, the time complexity of the partitioning algorithm increases exponentially, and the partitioning effect of the algorithm will decrease significantly. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a chip coarse-grained partitioning method and system based on resource and port signal quantity, which improves the efficiency and performance of coarse-grained partitioning when a large-scale chip is mapped to different FPGAs for prototype verification.

[0005] To solve the above technical problems, the technical scheme adopted by the present application is:

[0006] A chip coarse-grained partitioning method based on resource and port signal quantity, comprising:

[0007] S101, determining a coarse-grained module in a chip design DUT that cannot be subdivided into different FPGAs;

[0008] S102, expanding and constructing a coarse-grained connection relationship graph for the coarse-grained module, wherein the coarse-grained connection relationship graph takes the coarse-grained module as a node, the connection signal between the coarse-grained modules as a signal edge, the attribute of the node as the resource required by the coarse-grained module corresponding to the node, and the weight of the signal edge as the port signal quantity between the coarse-grained modules;

[0009] S103, obtaining the number of interconnection channels between each FPGA chip in the FPGA verification platform, and if the number of interconnection channels between each two FPGA chips is the same, then the nodes in the coarse-grained connection relationship graph are blocked with the maximum value of the sum of signal edge weights between blocks as the target; otherwise, the nodes in the coarse-grained connection relationship graph are blocked with the sum of signal edge weights between blocks as small as possible as the target, and finally the coarse-grained division result of the chip design DUT under test is obtained.

[0010] Optionally, when the nodes in the coarse-grained connection relationship graph are blocked, the sum of resources of each module in each block is taken as a constraint condition.

[0011] Optionally, the specified proportion is valued between 60% and 80%.

[0012] Optionally, the specified proportion is valued at 70%.

[0013] Optionally, the blocking of the nodes in the coarse-grained connection relationship graph refers to the blocking of the nodes in the coarse-grained connection relationship graph by using a preset division algorithm.

[0014] Optionally, the preset division algorithm is a multi-level division algorithm, a binary strategy division algorithm or a multi-path strategy division algorithm.

[0015] Optionally, step S101 comprises:

[0016] S201, analyzing and obtaining the resources required by each module in the chip design DUT under test and the connection signals between the modules;

[0017] S202, constructing a design hierarchical tree by taking each module as a node in the design hierarchical tree and the connection signals between the modules as edges in the design hierarchical tree, and marking the required resources in the nodes in the design hierarchical tree;

[0018] S203, marking the coarse-grained modules that cannot be divided in the design hierarchical tree according to prior knowledge, and marking the modules whose required FPGA resources are less than a preset division granularity threshold as coarse-grained modules that cannot be divided, so as to obtain the coarse-grained modules in the chip design DUT under test that cannot be divided onto different FPGAs of the FPGA hardware platform.

[0019] Optionally, the analysis and obtaining of the resources required by each module in the chip design DUT under test in step S201 refers to the analysis and obtaining of the resources required by each module in the chip design DUT under test by using a synthesis tool to synthesize the chip design DUT under test.

[0020] Further, the present application also provides a chip coarse-grained partitioning system based on resource and port signal quantity, comprising a microprocessor and a memory connected with each other, wherein the microprocessor is programmed or configured to execute the chip coarse-grained partitioning method based on resource and port signal quantity.

[0021] Further, the present application also provides a computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, and the computer program is used to program or configure a microprocessor to execute the chip coarse-grained partitioning method based on resource and port signal quantity.

[0022] Further, the present application also provides a computer program product, comprising computer programs / instructions which are programmed or configured to execute the chip coarse-grained partitioning method based on resource and port signal quantity by a processor.

[0023] Compared with the prior art, the present application has the following advantages: the present application comprises determining coarse-grained modules in a design under test (DUT) which cannot be subdivided into different FPGAs; expanding the coarse-grained modules to construct a coarse-grained connection relationship graph, wherein the coarse-grained modules are nodes, the connection signals between the coarse-grained modules are signal edges, the attribute of the node is the resource required by the coarse-grained module corresponding to the node, and the weight of the signal edge is the port signal quantity between the coarse-grained modules; obtaining the number of interconnection channels between each FPGA chip in an FPGA verification platform, if the number of interconnection channels between each two FPGA chips is the same, then the nodes in the coarse-grained connection relationship graph are blocked with the maximum value of the sum of the signal edge weights between the blocks as the target being the smallest; otherwise, the nodes in the coarse-grained connection relationship graph are blocked with the sum of the signal edge weights between the blocks being as small as possible as the target, and finally the coarse-grained partitioning result of the design under test (DUT) is obtained. Through the above manner, the user's prior knowledge is introduced before automatic partitioning, the design is preprocessed, the complexity of the partitioning algorithm is greatly reduced, and the partitioning time is saved. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a basic flowchart of the embodiment method of the present application.

[0025] Figure 2 It is a design under test instance tree (marked resource) in the embodiment of the present application.

[0026] Figure 3 It is a design under test instance tree (unsubdividable granularity is set according to prior knowledge) in the embodiment of the present application.

[0027] Figure 4 It is a design under test instance tree (unsubdividable granularity is determined according to resource) in the embodiment of the present application.

[0028] Figure 5For the user in the embodiment of the application after unfolding.

[0029] Figure 6 For the FPGA platform and resource situation in the embodiment of the application.

[0030] Figure 7 For the coarse-grained partitioning result in the embodiment of the application. DETAILED DESCRIPTION

[0031] As Figure 1 shown, the chip coarse-grained partitioning method based on resources and port signal quantities in the embodiment includes:

[0032] S101, determining a coarse-grained module in a chip under test DUT that cannot be subdivided into different FPGAs; the chip under test is a large-scale chip, specifically a chip that cannot meet the prototyping verification requirement with a single FPGA and needs multiple FPGAs to meet the prototyping verification requirement;

[0033] S102, unfolding the coarse-grained module to construct a coarse-grained connection relationship graph, in which the coarse-grained module is a node, the connection signal between the coarse-grained modules is a signal edge, the attribute of the node is the resource required by the coarse-grained module corresponding to the node, and the weight of the signal edge is the port signal quantity between the coarse-grained modules;

[0034] S103, acquiring the number of interconnection channels between each FPGA chip in the FPGA verification platform, and if the number of interconnection channels between the FPGA chips is the same, block the nodes in the coarse-grained connection relationship graph with the maximum value of the sum of the signal edge weights between the blocks as the target; otherwise, block the nodes in the coarse-grained connection relationship graph with the sum of the signal edge weights between the blocks as small as possible as the target, and finally obtain the coarse-grained partitioning result of the chip under test DUT.

[0035] When the nodes in the coarse-grained connection relationship graph are blocked in the embodiment, the sum of the resources of each module in each block is taken as a constraint condition, and the specified proportion of the resources in a FPGA chip is generally taken as 60-80%, for example, the specified proportion is taken as 70% in the embodiment.

[0036] The blocking of the nodes in the coarse-grained connection relationship graph in the embodiment refers to the blocking of the nodes in the coarse-grained connection relationship graph by using a preset partitioning algorithm. The preset partitioning algorithm is a multi-level partitioning algorithm, a binary strategy partitioning algorithm, or a multi-way strategy partitioning algorithm. Since the above partitioning algorithms are known algorithms, the implementation details are not described herein.

[0037] The step S101 in the embodiment includes:

[0038] S201, analyze the resources required by each module in the chip design under test DUT and the connection signals between the modules;

[0039] S202, construct a design hierarchical tree with each module as a node in the design hierarchical tree and the connection signals between the modules as edges in the design hierarchical tree, and mark the required resources in the nodes in the design hierarchical tree;

[0040] S203, mark the coarse-grained modules that cannot be divided in the design hierarchical tree according to prior knowledge, and mark the modules whose number of required FPGA resources in the design hierarchical tree is less than a preset division granularity threshold as coarse-grained modules that cannot be divided, so as to obtain the coarse-grained modules in the chip design under test DUT that cannot be divided onto different FPGAs of the FPGA hardware platform.

[0041] In step S201 of the embodiment, the resources required by each module in the chip design under test DUT are analyzed, which means that the resources required by each module in the chip design under test DUT are analyzed by using a synthesis tool to synthesize the chip design under test DUT. For example, in the embodiment, the design is synthesized by using a synthesis tool (VIVADO) for the chip design under test DUT, the FPGA resource conditions of each module in the design are obtained, the instance tree of the design under test is obtained, and the resources are marked as shown in the following table: Figure 2 A M K , respectively, which are the marked resources of instances A-K in the instance tree of the design under test. The marked resources can be represented as:

[0042]

[0043] , which represent the first Figure 3 class resources, and the nodes need to be counted in total class resources. Designers or verification personnel set the modules with complex interconnection relationships in the design as coarse-grained modules that cannot be divided according to prior knowledge. For example, instance D in the table is a coarse-grained module that cannot be divided onto different FPGAs.

[0044] According to the scale of the FPGA in the prototype verification platform and the resource conditions of the complete design under test of the user, the embodiment selects a suitable level in the design hierarchical tree as the division granularity that cannot be divided. A certain proportion of the FPGA resource scale is selected as the threshold of the division granularity, and the modules greater than the threshold continue to be divided, and the modules less than the threshold are no longer divided. Taking Xilinx FPGA as an example, the total resources are denoted as , and the selected division granularity threshold is 2% of the total resources, that is, 2% Figure 4 M. Of course, according to the scale of the specific design, other suitable proportions can also be selected as the threshold value.​​​​The shown is the instance tree to be tested obtained in the embodiment (determined according to resources, non-divisible granularity), and instances C, D, J and K are marked as non-divisible coarse-grained modules on different FPGAs.

[0045] The user design is expanded to obtain a coarse-grained connection relationship diagram, wherein the coarse-grained modules are points, the weights are resources, and the connection signals between the coarse-grained modules are edges, and the weights are the sum of signal bit widths; the expanded user design is shown in Figure 5 , wherein S DK represents the weight (the sum of signal bit widths) between instances D and K. The allocated FPGA hardware platform conditions are obtained, including the number of FPGAs, the resources of each FPGA and the number of signal transmission channels between FPGAs, as shown in Figure 6 , wherein M represents the instances in the three FPGAs (FPGA0-FPGA2), W 01 , W 02 and W 12 represent the number of signal transmission channels between FPGAs. According to the number of FPGAs allocated in the previous step, the user design based on coarse-grained expansion is divided into corresponding blocks, and the target is to make the sum of signal edge weights between the divided blocks as small as possible. If the FPGA platform is symmetrical, that is, the number of interconnection channels between FPGA chips is the same, the target is to make the maximum value of the sum of signal edge weights between the divided blocks as small as possible. The constraint is that the sum of resources of each divided block does not exceed 70% of the resources of one FPGA. As shown in Figure 7 , the result after division is shown, and the resources of the divided blocks are , , . The signal edges between the divided blocks are , , . The target is to make as small as possible. The constraint condition is .

[0046] The chip coarse-grained division method based on resource and port signal quantity in the embodiment includes setting the department modules in the design as non-divisible granularity, which is coarse-grained relative to the original netlist. According to prior knowledge, first, the modules with complex interconnection relationship in the design are set as non-divisible granularity, then a certain proportion of the FPGA resource scale is selected as the threshold of non-divisible granularity, the modules greater than the threshold are continuously subdivided, and the modules less than the threshold are not subdivided, as non-divisible granularity. The chip coarse-grained division method based on resource and port signal quantity in the embodiment introduces user prior knowledge before automatic division, pre-processes the design, greatly reduces the complexity of the division algorithm, and saves the division time.

[0047] In addition, the embodiment further provides a chip coarse-grained partitioning system based on resource and port semaphore, comprising a microprocessor and a memory connected with each other, wherein the microprocessor is programmed or configured to execute the chip coarse-grained partitioning method based on resource and port semaphore.

[0048] In addition, the embodiment further provides a computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, and the computer program is used for programming or configuring a microprocessor to execute the chip coarse-grained partitioning method based on resource and port semaphore.

[0049] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer readable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) containing computer usable program code. The present application is described with reference to flowcharts and / or block diagrams of the methods, apparatus (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and a combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions, which are executed via the processor of the computer or other programmable data processing apparatus, generate a means for implementing the functions specified in the flowcharts and / or block diagrams of the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus with a means for performing the functions specified in the flowcharts and / or block diagrams of the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus with a means for performing the functions specified in the flowcharts and / or block diagrams of the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus with a means for performing the functions specified in the flowcharts and / or block diagrams of the flowcharts and / or block diagrams.

[0050] The above merely describes the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-described embodiments. Any technical solution falling within the concept of the present application shall fall within the protection scope of the present application. It should be noted that, for ordinary skilled persons in the art, some improvements and refinements without departing from the principles of the present application shall also be considered as falling within the protection scope of the present application.

Claims

1. A method for chip coarse-grained partitioning based on resource and port semaphore, characterized in that, The method comprises the following steps: S101, determining coarse-grained modules in a design under test (DUT) which cannot be subdivided into different FPGAs; S102, expanding the coarse-grained modules to build a coarse-grained connection relationship graph, wherein the coarse-grained modules are nodes, the connection signals between the coarse-grained modules are signal edges, the attribute of the node is the resource required by the coarse-grained module corresponding to the node, and the weight of the signal edge is the port signal amount between the coarse-grained modules; S103, obtaining the number of interconnection channels between each FPGA chip in an FPGA verification platform, and if the number of interconnection channels between each two FPGA chips is the same, the nodes in the coarse-grained connection relationship graph are blocked with the maximum value of the sum of the signal edge weights between the blocks as the target; otherwise, the nodes in the coarse-grained connection relationship graph are blocked with the sum of the signal edge weights between the blocks as small as possible as the target, and finally the coarse-grained division result of the design under test (DUT) is obtained.

2. The method of claim 1, wherein, When the nodes in the coarse-grained connection relationship graph are blocked, the sum of the resources of each module in each block is taken as a constraint condition, and the specified proportion of the resources in one FPGA chip is not more than 60-80%.

3. The method of claim 2, wherein, The specified proportion is 60-80%.

4. The method of claim 1, wherein, The nodes in the coarse-grained connection relationship graph are blocked by using a preset division algorithm.

5. The method of claim 4, wherein, The preset division algorithm is a multi-level division algorithm, a binary strategy division algorithm, or a multi-path strategy division algorithm.

6. The method of claim 1, wherein, Step S101 comprises: S201, analyzing and obtaining the resources required by each module in the design under test (DUT) and the connection signals between the modules; S202, constructing a design hierarchical tree by taking each module as a node in the design hierarchical tree and the connection signals between the modules as an edge in the design hierarchical tree, and marking the required resources in the node in the design hierarchical tree; S203, marking the coarse-grained modules which cannot be subdivided into different FPGAs on the FPGA hardware platform in the design hierarchical tree according to prior knowledge, and marking the modules whose required FPGA resource quantity is less than a preset division granularity threshold as coarse-grained modules which cannot be subdivided, so as to obtain the coarse-grained modules which cannot be subdivided into different FPGAs on the FPGA hardware platform in the design under test (DUT).

7. The method of claim 6, wherein, In step S201, the resources required by each module in the design under test (DUT) are analyzed and obtained by using a synthesis tool to synthesize the design under test (DUT).

8. A resource and port semaphore based chip coarse grain partitioning system comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to execute the chip coarse-grained division method based on resources and port signal amounts in any one of claims 1-7.

9. A computer-readable storage medium having stored therein a computer program, characterized in that, The computer program is used to program or configure the microprocessor to execute the chip coarse-grained division method based on resources and port signal amounts in any one of claims 1-7.

10. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is programmed or configured to execute the chip coarse-grained division method based on resources and port signal amounts in any one of claims 1-7 by the processor.

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