Inverter circuit, control circuit and control method

Abstract

The present invention relates to the field of power electronic converters, and discloses an inverter circuit, a control circuit and a control method; the inverter circuit comprises a first-stage inverter circuit, a second-stage inverter circuit and a power supply, the first-stage inverter circuit comprises a triode VT3, a triode VT4, a triode VT5 and a diode D2, and the second-stage inverter circuit comprises a triode VT1, a triode VT2, a triode VT6 and a diode D1; the control circuit is used to amplify the input power supply through the triode VT3, the triode VT4 and the triode VT5 in sequence to output a positive half-cycle output voltage, and is also used to amplify the input power supply through the triode VT1, the triode VT2 and the triode VT6 in sequence to output a negative half-cycle output voltage. The inverter circuit provided by the present invention improves system efficiency and reduces implementation costs.

Description

Technical Field

[0001] The present invention relates to the field of power electronic converters, and in particular to an inverter circuit, a control circuit and a control method. Background Art

[0002] As energy crisis and environmental problems become increasingly serious, renewable energy such as solar energy and wind energy are gaining more and more attention as a new type of energy. As the core technology of renewable energy power generation, power electronic conversion equipment plays an increasingly important role in energy conversion and transmission. The output voltage of renewable energy such as photovoltaic modules is usually low, so boost inverter becomes one of the important devices used to convert DC power into AC power.

[0003] However, the traditional boost inverter uses two-stage conversion to achieve buck-boost, that is, the boost converter and the inverter are cascaded, which reduces the system efficiency. Therefore, it is of great significance to develop an efficient, compact, and low-cost boost inverter and its control method. Summary of the invention

[0004] In view of this, the present invention provides an inverter circuit, a control circuit and a control method to solve the problems of low efficiency and complex structure of the inverter circuit.

[0005] In a first aspect, the present invention provides an inverter circuit, comprising a first-stage inverter circuit, a second-stage inverter circuit, and a power supply, wherein:

[0006] The first-stage inverter circuit includes transistor VT3, transistor VT4, transistor VT5 and diode D2; the second-stage inverter circuit includes transistor VT1, transistor VT2, transistor VT6 and diode D1;

[0007] The emitter E3 of the transistor VT3 in the first-stage inverter circuit is connected to the first input terminal of the diode D2, the first output terminal of the diode D2 is connected to the collector C5 of the transistor VT5, the collector C4 of the transistor VT4 is connected to the first input terminal, the emitter E4 of the transistor VT4 is connected to the negative electrode of the power supply, and the collector C3 of the transistor VT3 and the emitter E5 of the transistor VT5 are both connected to the positive electrode of the power supply;

[0008] The emitter E1 of the transistor VT1 in the second-stage inverter circuit is connected to the second input terminal of the diode D1, the second output terminal of the diode D1 is connected to the collector C6 of the transistor VT6 through the collector C5 in turn, the collector C2 of the transistor VT2 is connected to the second input terminal, the emitter E2 of the transistor VT2 and the collector C6 of the transistor VT6 are connected to the negative electrode of the power supply, and the collector C1 of the transistor VT1 and the emitter E6 of the transistor VT6 are both connected to the positive electrode of the power supply;

[0009] The power supply is used to supply power to the inverter circuit. The first-stage inverter circuit is used to amplify the input power through transistors VT3, VT4 and VT5 in sequence to output a positive half-cycle output voltage. The second-stage inverter circuit is used to amplify the input power through transistors VT1, VT2 and VT6 in sequence to output a negative half-cycle output voltage.

[0010] The boostable inverter circuit in the prior art usually adopts a bipolar mode, and the boost efficiency of the inverter circuit is low. However, the inverter circuit provided in the present application adopts a unipolar circuit. The unipolar circuit refers to an input signal provided by a single power supply. The positive half-cycle output signal and the negative half-cycle output signal are obtained through the first-stage inverter circuit and the second-stage inverter circuit in the present invention. The inverter circuit of the present invention improves the system efficiency, reduces the implementation cost, does not need to add additional circuits, has high accuracy, reduces the number of switching devices working at high frequency, and reduces switching losses; the inverter circuit in the present invention is controlled by a control circuit, and the inverter circuit adopts a new single-cycle control method to realize the buck and boost functions. It does not require a DC bias voltage and does not require a high-precision sampling link. In addition to precise control, it can respond quickly and accurately to external changes, thereby improving the inverter's response capability to input voltage changes.

[0011] In an optional implementation, the inverter circuit further includes a capacitor C and a resistor R;

[0012] The capacitor C is connected in parallel with the resistor R. One end of the capacitor C and the resistor R is connected to the collector C5, and the other end of the capacitor C and the resistor R is connected to the first output end.

[0013] Capacitor C plays a filtering role in the inverter circuit, and resistor R plays a load role in the inverter circuit. The filter capacitor C is set in the inverter circuit. When the first-stage inverter circuit or the second-stage inverter circuit generates an output signal, the filter capacitor C filters the output signal to make the filtered output signal have lower ripple and more accurate output signal.

[0014] In an optional implementation, the inverter circuit further includes an inductor L1;

[0015] The inductor L1 is connected in series between the emitter E1 and the second input terminal.

[0016] In an optional implementation, the inverter circuit further includes an inductor L2;

[0017] The inductor L2 is connected in series between the emitter E3 and the first input terminal.

[0018] In an optional embodiment, the present invention provides a control circuit, which is applied to the above-mentioned inverter circuit. The control circuit includes a detection unit, a reset integrator, a comparator, a trigger and a selection switch, wherein:

[0019] The detection unit is connected to the selection switch through a reset integrator, a comparator, and a trigger in sequence;

[0020] The detection unit is used to detect the output voltage V of the inverter circuit. o , reset the integrator for the power supply V g and output voltage V o The output value of the integrator is sent to one end of the comparator, which is used to compare the output value after integration with the given value V ref In comparison, the trigger is used to receive the output signal of the comparator and the clock signal, and to output a trigger signal, and the selection switch is used to receive the trigger signal, and to output a high level signal or a low level signal to control the device of the inverter circuit.

[0021] In an optional implementation, the reset integrator includes a first terminal, a second terminal, and a third terminal;

[0022] The first terminal is connected to the detection unit, the second terminal is connected to the non-inverting input terminal of the comparator, and the third terminal is connected to the fifth output terminal of the trigger.

[0023] In an optional implementation, the comparator further includes an inverting input terminal and a third output terminal;

[0024] The inverting input terminal is connected to the sixth terminal of the selection switch, and the third output terminal is connected to the fourth input terminal of the trigger.

[0025] In an optional embodiment, the trigger further includes a third input terminal and a fourth output terminal;

[0026] The third input terminal is connected to the external clock signal line, the fourth output terminal is connected to the fourth terminal of the selection switch, and the fifth output terminal is also connected to the fifth terminal of the selection switch.

[0027] In an optional implementation, the selection switch further includes a sixth output terminal, a seventh output terminal, an eighth output terminal, a ninth output terminal, a tenth output terminal and an eleventh output terminal;

[0028] The sixth output terminal is connected to the base B1 in the transistor VT1, the seventh output terminal is connected to the base B2 in the transistor VT2, the eighth output terminal is connected to the base B3 in the transistor VT3, the ninth output terminal is connected to the base B4 in the transistor VT4, the tenth output terminal is connected to the base B5 in the transistor VT5, and the eleventh output terminal is connected to the base B6 in the transistor VT6.

[0029] The control circuit includes a detection unit, a reset integrator, a comparator, a trigger and a selection switch. The detection unit detects the value of the output voltage and then adds it to the DC side voltage value. The obtained sum is sent to the reset integrator; the output end of the reset integrator is connected to an input end of the comparator, and a given voltage value is input to the other end of the comparator. The output end of the comparator is connected to the reset end of the trigger. The output end of the trigger is connected to the selection switch on the one hand and to the reset integrator on the other hand. The output end of the trigger is connected to the selection switch, and the output of the selection switch is used to control the opening and closing of the switch devices of the first-stage inverter circuit and the second-stage inverter circuit.

[0030] In a second aspect, the present invention provides a control method for an inverter circuit, the method being applied to the above-mentioned inverter circuit, the method comprising:

[0031] The transistor VT3 in the inverter circuit receives the high-level signal output by the selection switch in the control circuit and remains turned on. The transistor VT4 and the transistor VT5 alternately receive the high-level signal output by the selection switch and alternately turn on to output the positive half-cycle output signal. The transistor VT1, the transistor VT2 and the transistor VT6 receive the low-level signal output by the selection switch and remain turned off.

[0032] In an optional embodiment, the transistor VT1 in the inverter circuit receives a high-level signal output by the selection switch in the control circuit and remains turned on, the transistor VT2 and the transistor VT6 alternately receive the high-level signal output by the selection switch and alternately turn on to output the negative half-cycle output signal, and the transistor VT3, the transistor VT4 and the transistor VT5 receive the low-level signal output by the selection switch and remain turned off.

[0033] This control method controls the first-stage inverter circuit and the second-stage inverter circuit respectively according to the positive and negative half-cycles of the given output voltage, and realizes the buck and boost inverter functions by changing the size of the given voltage. This single-cycle control method does not require a DC bias voltage or a high-precision sampling link. In addition to precise control, it can respond quickly and accurately to external changes, thereby improving the inverter's ability to respond to input voltage changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 is a structural schematic diagram of an inverter circuit according to an embodiment of the present invention;

[0036] Figure 2 is a schematic structural diagram of a control circuit according to an embodiment of the present invention;

[0037] Figure 3 is a structural schematic diagram of an inverter circuit in a first mode according to an embodiment of the present invention;

[0038] Figure 4 is a structural schematic diagram of an inverter circuit in a second mode according to an embodiment of the present invention;

[0039] Figure 5 is a schematic structural diagram of an inverter circuit in a third mode according to an embodiment of the present invention;

[0040] Figure 6 is a structural schematic diagram of an inverter circuit in a fourth mode according to an embodiment of the present invention;

[0041] Figure 7 is a waveform diagram of the driving signals of the transistor VT3, the transistor VT4 and the transistor VT5 in the positive half cycle of the inverter circuit according to the embodiment of the present invention;

[0042] Figure 8 is a waveform diagram of a step-down signal output by an inverter circuit according to an embodiment of the present invention;

[0043] Fig. 9 is a waveform diagram of a boost signal output by an inverter circuit according to an embodiment of the present invention;

[0044] Fig.10 4 is a waveform diagram of the output voltage of the inverter circuit according to the embodiment of the present invention when the input voltage jumps. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0046] like Figure 1 As shown, the present invention provides an inverter circuit, characterized in that it includes a first-stage inverter circuit, a second-stage inverter circuit, and a power supply, wherein:

[0047] The first-stage inverter circuit includes transistor VT3, transistor VT4, transistor VT5 and diode D2; the second-stage inverter circuit includes transistor VT1, transistor VT2, transistor VT6 and diode D1;

[0048] The emitter E3 of the transistor VT3 in the first-stage inverter circuit is connected to the first input terminal of the diode D2, the first output terminal of the diode D2 is connected to the collector C5 of the transistor VT5, the collector C4 of the transistor VT4 is connected to the first input terminal, the emitter E4 of the transistor VT4 is connected to the negative electrode of the power supply, and the collector C3 of the transistor VT3 and the emitter E5 of the transistor VT5 are both connected to the positive electrode of the power supply;

[0049] The emitter E1 of the transistor VT1 in the second-stage inverter circuit is connected to the second input terminal of the diode D1, the second output terminal of the diode D1 is connected to the collector C6 of the transistor VT6 through the collector C5 in turn, the collector C2 of the transistor VT2 is connected to the second input terminal, the emitter E2 of the transistor VT2 and the collector C6 of the transistor VT6 are connected to the negative electrode of the power supply, and the collector C1 of the transistor VT1 and the emitter E6 of the transistor VT6 are both connected to the positive electrode of the power supply;

[0050] The power supply is used to supply power to the inverter circuit. The first-stage inverter circuit is used to amplify the input power through transistors VT3, VT4 and VT5 in sequence to output a positive half-cycle output voltage. The second-stage inverter circuit is used to amplify the input power through transistors VT1, VT2 and VT6 in sequence to output a negative half-cycle output voltage.

[0051] The boostable inverter circuit in the prior art usually adopts a bipolar mode, and the boost efficiency of the inverter circuit is low. However, the inverter circuit provided in the present application adopts a unipolar circuit. The unipolar circuit refers to an input signal provided by a single power supply. The positive half-cycle output signal and the negative half-cycle output signal are obtained through the first-stage inverter circuit and the second-stage inverter circuit in the present invention. The inverter circuit of the present invention improves the system efficiency, reduces the implementation cost, does not need to add additional circuits, has high accuracy, reduces the number of switching devices working at high frequency, and reduces switching losses; the inverter circuit in the present invention is controlled by a control circuit, and the inverter circuit adopts a new single-cycle control method to realize the buck and boost functions. It does not require a DC bias voltage and does not require a high-precision sampling link. In addition to precise control, it can respond quickly and accurately to external changes, thereby improving the inverter's response capability to input voltage changes.

[0052] In this embodiment, the inverter circuit further includes a capacitor C and a resistor R.

[0053] The capacitor C is connected in parallel with the resistor R. One end of the capacitor C and the resistor R is connected to the collector C5, and the other end of the capacitor C and the resistor R is connected to the first output end.

[0054] Capacitor C plays a filtering role in the inverter circuit, and resistor R plays a load role in the inverter circuit. The filter capacitor C is set in the inverter circuit. When the first-stage inverter circuit or the second-stage inverter circuit generates an output signal, the filter capacitor C filters the output signal to make the filtered output signal have lower ripple and more accurate output signal.

[0055] In this embodiment, the inverter circuit further includes an inductor L1.

[0056] The inductor L1 is connected in series between the emitter E1 and the second input terminal.

[0057] In this embodiment, the inverter circuit further includes an inductor L2.

[0058] The inductor L2 is connected in series between the emitter E3 and the first input terminal.

[0059] like Figure 2 As shown, the present invention provides a control circuit, which is applied to the above-mentioned inverter circuit. The control circuit includes a detection unit, a reset integrator, a comparator, a trigger and a selection switch, wherein:

[0060] The detection unit is connected with the selection switch through a reset integrator, a comparator, and a trigger in sequence.

[0061] The detection unit is used to detect the output voltage V of the inverter circuit. o , reset the integrator for the power supply V g and output voltage V o The output value of the integrator is sent to one end of the comparator, which is used to compare the output value after integration with the given value V ref In comparison, the trigger is used to receive the output signal of the comparator and the clock signal, and to output a trigger signal, and the selection switch is used to receive the trigger signal, and to output a high level signal or a low level signal to control the device of the inverter circuit.

[0062] In this embodiment, the reset integrator includes a first terminal, a second terminal and a third terminal.

[0063] The first terminal is connected to the detection unit, the second terminal is connected to the non-inverting input terminal of the comparator, and the third terminal is connected to the fifth output terminal of the trigger.

[0064] In this embodiment, the comparator further includes an inverting input terminal and a third output terminal.

[0065] The inverting input terminal is connected to the sixth terminal of the selection switch, and the third output terminal is connected to the fourth input terminal of the trigger.

[0066] In this embodiment, the trigger further includes a third input terminal and a fourth output terminal.

[0067] The third input terminal is connected to the external clock signal line, the fourth output terminal is connected to the fourth terminal of the selection switch, and the fifth output terminal is also connected to the fifth terminal of the selection switch.

[0068] In this embodiment, the selection switch further includes a sixth output terminal, a seventh output terminal, an eighth output terminal, a ninth output terminal, a tenth output terminal and an eleventh output terminal.

[0069] The sixth output terminal is connected to the base B1 in the transistor VT1, the seventh output terminal is connected to the base B2 in the transistor VT2, the eighth output terminal is connected to the base B3 in the transistor VT3, the ninth output terminal is connected to the base B4 in the transistor VT4, the tenth output terminal is connected to the base B5 in the transistor VT5, and the eleventh output terminal is connected to the base B6 in the transistor VT6.

[0070] The control circuit includes a detection unit, a reset integrator, a comparator, a trigger and a selection switch. The detection unit detects the value of the output voltage and then adds it to the DC side voltage value. The obtained sum is sent to the reset integrator; the output end of the reset integrator is connected to an input end of the comparator, and a given voltage value is input to the other end of the comparator. The output end of the comparator is connected to the reset end of the trigger. The output end of the trigger is connected to the selection switch on the one hand and to the reset integrator on the other hand. The output end of the trigger is connected to the selection switch, and the output of the selection switch is used to control the opening and closing of the switch devices of the first-stage inverter circuit and the second-stage inverter circuit.

[0071] In this embodiment, the present invention provides a control method for an inverter circuit, which is applied to the above-mentioned inverter circuit, and the method includes:

[0072] The transistor VT3 in the inverter circuit receives the high-level signal output by the selection switch in the control circuit and remains turned on. The transistor VT4 and the transistor VT5 alternately receive the high-level signal output by the selection switch and alternately turn on to output the positive half-cycle output signal. When the transistor VT3 remains turned on, the transistors VT1, VT2 and VT6 receive the low-level signal output by the selection switch and remain turned off.

[0073] In this embodiment, the transistor VT1 in the inverter circuit receives the high-level signal output by the selection switch in the control circuit and remains turned on, the transistor VT2 and the transistor VT6 alternately receive the high-level signal output by the selection switch and alternately turn on to output the negative half-cycle output signal, and when the transistor VT1 remains turned on, the transistors VT3, VT4 and VT5 receive the low-level signal output by the selection switch and remain turned off.

[0074] Furthermore, according to the control circuit controlling the conduction of the devices in the inverter circuit, the conduction of the inverter circuit is divided into four modes:

[0075] In the first mode, the control circuit controls the transistors VT3 and VT4 to be turned on, and controls the transistors VT1, VT2 and VT6 to be turned off. At this time, the inverter circuit is as follows Figure 3 As shown, a loop is formed, and the positive half-cycle output signal is output according to the current flow from power supply Vg→transistor VT3→inductor L2→transistor VT4→power supply Vg.

[0076] In the second mode, the control circuit controls the transistors VT3 and VT5 to be turned on, and controls the transistors VT1, VT2 and VT6 to be turned off. At this time, the inverter circuit is as follows Figure 4 As shown, a loop is formed, and the positive half-cycle output signal is output according to the current flow direction of transistor VT3 → inductor L2 → diode D2 → capacitor C / / resistor R → transistor VT5 → transistor VT3.

[0077] In the third mode, the control circuit controls transistors VT1 and VT2 to be turned on, and controls transistors VT3, VT4 and VT5 to be turned off. At this time, the inverter circuit is as follows Figure 5 As shown, a loop is formed, and the negative half-cycle output signal is output according to the current flow from power supply Vg→transistor VT1→inductor L1→transistor VT2→power supply Vg.

[0078] In the fourth mode, the control circuit controls transistors VT1 and VT6 to be turned on, and controls transistors VT3, VT4 and VT5 to be turned off. At this time, the inverter circuit is as follows: Figure 6 As shown, a loop is formed, and the negative half-cycle output signal is output according to the current flow direction of transistor VT1 → inductor L1 → diode D1 → capacitor C / / resistor R → transistor VT6 → transistor VT1.

[0079] This control method controls the first-stage inverter circuit and the second-stage inverter circuit respectively according to the positive and negative half-cycles of the given output voltage, and determines the boost or buck by the size of the given voltage value. A high given voltage value, that is, an output voltage value higher than the input voltage, is boosted, and an output voltage value lower than the input voltage is bucked, thereby realizing buck and boost inverter functions. This single-cycle control method does not require a DC bias voltage or a high-precision sampling link. In addition to precise control, it can respond quickly and accurately to external changes, thereby improving the inverter's ability to respond to input voltage changes.

[0080] The present invention provides specific embodiments based on the above-mentioned inverter circuit, control circuit and control method. Figure 7 The driving signals of transistors VT3, VT4 and VT5 in the positive half cycle of the inverter circuit using single-cycle control are shown in the figure. As can be seen from the figure, only two switching tubes work at high frequency, thereby reducing switching losses. Figure 8The inverter output voltage of the inverter circuit with single-cycle control in step-down mode is shown in Figure 1. At this time, the input voltage is 50V, and the output voltage is given as a 30V, 50Hz sinusoidal voltage. Figure 8 , through the inverter circuit of the present invention, given an input signal, the output signal after voltage reduction can be accurately obtained; Fig. 9 The output voltage of the inverter circuit with single-cycle control is inverted when the voltage is increased. The input DC voltage is 50V, and the output given voltage is 110V, 50Hz sinusoidal voltage. Figure 8 , through the inverter circuit of the present invention, given an input signal, the boosted output signal can be accurately obtained; Fig.10 This is the output voltage waveform when the input voltage jumps. It can be seen from the figure that it has a strong inhibitory effect on fluctuations on the input side.

[0081] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0082] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0083] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0084] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0085] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. An inverter circuit, characterized in that: It includes a first-stage inverter circuit, a second-stage inverter circuit, and a power supply, wherein: The first-stage inverter circuit includes transistor VT3, transistor VT4, transistor VT5 and diode D2; the second-stage inverter circuit includes transistor VT1, transistor VT2, transistor VT6 and diode D1; The emitter E3 of the transistor VT3 in the first-stage inverter circuit is connected to the first input end of the diode D2, the first output end of the diode D2 is connected to the collector C5 of the transistor VT5, the collector C4 of the transistor VT4 is connected to the first input end, the emitter E4 of the transistor VT4 is connected to the negative electrode of the power supply, and the collector C3 of the transistor VT3 and the emitter E5 of the transistor VT5 are both connected to the positive electrode of the power supply; The emitter E1 of the transistor VT1 in the second-stage inverter circuit is connected to the second input end of the diode D1, the second output end of the diode D1 is connected to the collector C6 of the transistor VT6 through the collector C5 in sequence, the collector C2 of the transistor VT2 is connected to the second input end, the emitter E2 of the transistor VT2 and the collector C6 of the transistor VT6 are connected to the negative electrode of the power supply, and the collector C1 of the transistor VT1 and the emitter E6 of the transistor VT6 are both connected to the positive electrode of the power supply; The power supply is used to supply power to the inverter circuit. The first-stage inverter circuit is used to amplify the input power supply through transistors VT3, VT4 and VT5 in sequence and output a positive half-cycle output voltage. The second-stage inverter circuit is used to amplify the input power supply through transistors VT1, VT2 and VT6 in sequence and output a negative half-cycle output voltage.

2. The inverter circuit according to claim 1, characterized in that: The inverter circuit also includes a capacitor C and a resistor R; The capacitor C is connected in parallel with the resistor R. One end of the capacitor C and the resistor R is connected to the collector C5, and the other end of the capacitor C and the resistor R is connected to the first output end.

3. The inverter circuit according to claim 1, characterized in that: The inverter circuit also includes an inductor L1; The inductor L1 is connected in series between the emitter E1 and the second input terminal.

4. The inverter circuit according to claim 1, characterized in that: The inverter circuit also includes an inductor L2; The inductor L2 is connected in series between the emitter E3 and the first input terminal.

5. A control circuit, characterized in that: The control circuit is connected to an inverter circuit, and the inverter circuit is an inverter circuit as claimed in any one of claims 1 to 4; The control circuit comprises: a detection unit, a reset integrator, a comparator, a trigger and a selection switch, wherein the detection unit is connected to the selection switch via the reset integrator, the comparator and the trigger in sequence; The detection unit is used to detect the output voltage V of the inverter circuit. o , the reset integrator is used to reset the power supply V g and output voltage V o The difference is integrated, and the output value of the integrator is sent to one end of the comparator, which is used to compare the integrated output value with the given value V ref In comparison, the trigger is used to receive the output signal and the clock signal of the comparator, and to output a trigger signal, and the selection switch is used to receive the trigger signal, and to output a high level signal or a low level signal to control the device of the inverter circuit.

6. The control circuit according to claim 5, characterized in that: The reset integrator includes a first terminal, a second terminal and a third terminal; The first terminal is connected to the detection unit, the second terminal is connected to the non-inverting input terminal of the comparator, and the third terminal is connected to the fifth output terminal of the trigger.

7. The control circuit according to claim 6, characterized in that: The comparator further comprises an inverting input terminal and a third output terminal; The inverting input terminal is connected to the sixth terminal of the selection switch, and the third output terminal is connected to the fourth input terminal of the trigger.

8. The control circuit according to claim 7, characterized in that: The trigger also includes a third input terminal and a fourth output terminal; The third input terminal is connected to an external clock signal line, the fourth output terminal is connected to a fourth terminal of the selection switch, and the fifth output terminal is also connected to a fifth terminal of the selection switch.

9. The control circuit according to claim 8, characterized in that: The selection switch further includes a sixth output terminal, a seventh output terminal, an eighth output terminal, a ninth output terminal, a tenth output terminal and an eleventh output terminal; The sixth output terminal is connected to the base B1 in the transistor VT1, the seventh output terminal is connected to the base B2 in the transistor VT2, the eighth output terminal is connected to the base B3 in the transistor VT3, the ninth output terminal is connected to the base B4 in the transistor VT4, the tenth output terminal is connected to the base B5 in the transistor VT5, and the eleventh output terminal is connected to the base B6 in the transistor VT6.

10. A control method for an inverter circuit, characterized in that: The method is applied to the inverter circuit according to any one of claims 1 to 4, and the method comprises: When the transistor VT3 in the inverter circuit receives the high level signal output by the control circuit, the transistor VT3 is turned on; After the transistor VT3 is turned on, the transistor VT4 receives the high level signal output by the selection switch in the control circuit, and the transistor VT4 is turned on and outputs the first positive half-cycle output signal; After the transistor VT4 outputs the first positive half-cycle output signal, the transistor VT4 is turned off after receiving the low-level signal output by the selection switch, and the transistor VT5 receives the high-level signal output by the selection switch, and the transistor VT5 outputs the second positive half-cycle output signal; When the transistor VT3 is turned on, the transistors VT1, VT2 and VT6 receive the low level signal output by the control circuit and remain turned off.

11. The control method according to claim 10, characterized in that: When the transistor VT1 in the inverter circuit receives the high-level signal output by the control circuit, the transistor VT1 is turned on; After the transistor VT1 is turned on, the transistor VT2 receives the high level signal output by the selection switch in the control circuit, and the transistor VT2 is turned on and outputs the first negative half-cycle output signal; After the transistor VT2 outputs the first negative half-cycle output signal, the transistor VT2 is closed after receiving the low-level signal output by the selection switch, the transistor VT6 receives the high-level signal output by the control circuit, and the transistor VT6 outputs the second negative half-cycle output signal; When the transistor VT1 is turned on, the transistors VT3, VT4 and VT5 receive the low level signal output by the selection switch and remain turned off.

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