Method for improving PCB core board warping, computer program product and printed circuit board

Abstract

The application relates to a method and device for improving PCB core plate warping, a computer program product and a printed circuit board. The method comprises the following steps: acquiring a first residual copper rate corresponding to a first functional area of a first functional layer of a core plate and a second residual copper rate corresponding to a second functional area of a second functional layer; the first functional layer and the second functional layer are respectively located on two sides of the core plate; and the first residual copper rate of a first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of a second edge sealing area corresponding to the second functional layer are configured based on the first residual copper rate and the second residual copper rate. The scheme can be used to alleviate the warping phenomenon of the PCB.

Description

Technical Field

[0001] This application relates to the field of printed circuit board technology, and in particular to a method for improving PCB core board warping, an apparatus for improving PCB core board warping, a computer program product, and a printed circuit board. Background Technology

[0002] Printed Circuit Boards (PCBs) are crucial components in the electronics industry. With the rapid development of electronic products, the demands for signal transmission speeds and functionalities are increasing, leading to higher signal integrity requirements and more sophisticated multi-layered integration in PCB manufacturing. From a manufacturing perspective, the different residual copper ratios on both sides of a single core board (CORE), coupled with the relaxation effect of polymer materials, result in uneven stress distribution on both sides of the CORE. For a single CORE, the bending strength decreases as the CORE thickness decreases, and this uneven stress can easily cause warping after inner layer etching. Summary of the Invention

[0003] Therefore, it is necessary to provide a method and apparatus, computer program product, or printed circuit board for improving PCB core board warping, thereby alleviating PCB warping.

[0004] In a first aspect, this application provides a method for improving PCB core board warping, comprising:

[0005] The first residual copper ratio corresponding to the first functional area of ​​the first functional layer of the core board and the second residual copper ratio corresponding to the second functional area of ​​the second functional layer are obtained; wherein the first functional layer and the second functional layer are located on both sides of the core board respectively;

[0006] Configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer based on the first residual copper rate and the second residual copper rate.

[0007] In one possible implementation, configuring the first residual copper rate of the first edge sealing region corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing region corresponding to the second functional layer based on the first residual copper rate and the second residual copper rate includes:

[0008] The difference in residual copper rate is determined based on the first residual copper rate and the second residual copper rate.

[0009] Based on the difference in residual copper rate, the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer are configured according to an inverse proportional relationship.

[0010] In one possible implementation, the method further includes:

[0011] Obtain the original warping parameters of the core board;

[0012] Based on the original warping parameters, the first residual copper rate, and the second residual copper rate, configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer, and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer.

[0013] In one possible implementation, configuring the first residual copper rate of the first edge sealing region corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing region corresponding to the second functional layer by combining the original warping parameters, the first residual copper rate, and the second residual copper rate includes:

[0014] Combining the original warping parameters and the residual copper rate difference, configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer, and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer; wherein, the residual copper rate difference is determined based on the first residual copper rate and the second residual copper rate.

[0015] In one possible implementation, the original warping parameters are determined based on the original warping height of the core board and the projection length of the core board in the first direction.

[0016] In one possible implementation, the first edge-sealing area includes a first process strip, and the second edge-sealing area includes a second process strip; the method further includes:

[0017] Based on the residual copper rate of the edge sealing area, configure the process strip parameters corresponding to the edge sealing area.

[0018] In one possible implementation, configuring the process strip parameters corresponding to the process strip of the edge-sealing area based on the residual copper ratio of the edge-sealing area includes:

[0019] Based on the residual copper rate of the sealing area and the target performance parameters corresponding to the process strip, the parameters of the process strip are configured; wherein, the target performance parameters of the process strip include: strength parameters.

[0020] In one possible implementation, configuring the process strip parameters corresponding to the process strip of the edge-sealing area based on the residual copper ratio of the edge-sealing area includes:

[0021] The process strip parameters are configured based on the residual copper rate of the sealing area, the target performance parameters corresponding to the process strip, and the dielectric layer thickness parameters; wherein, the dielectric layer thickness parameters are determined based on the adhesive flow rate and the process strip structure.

[0022] In one possible implementation, the process strip comprises several layers of elements arranged sequentially;

[0023] The process parameters include any one or a combination of any of the following: element arrangement direction, element size, element spacing, and number of element layers.

[0024] A second aspect of this application provides an apparatus for improving PCB core board warping, the apparatus comprising:

[0025] The first residual copper rate acquisition module is used to acquire the first residual copper rate corresponding to the first functional area of ​​the first functional layer of the core board, and the second residual copper rate corresponding to the second functional area of ​​the second functional layer; wherein the first functional layer and the second functional layer are respectively located on both sides of the core board;

[0026] The second residual copper rate configuration module is used to configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer based on the first residual copper rate and the second residual copper rate.

[0027] A second aspect of this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method as described in any embodiment of the first aspect.

[0028] A second aspect of this application provides a printed circuit board, including at least one core board, wherein a first functional layer and a second functional layer are respectively disposed on both sides of the core board;

[0029] The first functional layer includes a first functional area and a first sealing edge area disposed around the first functional area;

[0030] The second functional layer includes a second functional area and a second sealing area disposed around the perimeter of the second functional area;

[0031] The first residual copper ratio of the first edge sealing area corresponding to the first functional layer and / or the second residual copper ratio of the second edge sealing area corresponding to the second functional layer are configured based on the first residual copper ratio of the first functional area and the second residual copper ratio of the second functional area.

[0032] This invention provides a method for improving PCB core board warping. By obtaining the residual copper ratio of the first functional area of ​​the first functional layer on both sides of the core board and the second functional area of ​​the second functional layer, the residual copper ratio of the first edge sealing area outside the first functional layer and / or the residual copper ratio of the second edge sealing area outside the second functional layer can be configured based on the first and second residual copper ratios. By controlling the residual copper ratio of the edge sealing area, the inner layer edge sealing during the circuit board production process is optimized, thereby effectively alleviating the warping phenomenon that occurs during the inner core board production process. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the PCB board warping effect in one embodiment;

[0035] Figure 2 This is a schematic diagram of the structure of a multilayer PCB board in one embodiment of this application;

[0036] Figure 3 This is a schematic diagram of a method for improving PCB core board warping in one embodiment of this application;

[0037] Figure 4 This is a schematic diagram illustrating the improvement of PCB core board warping effect in one embodiment of this application;

[0038] Figure 5 This is a schematic diagram of a PCB board in one embodiment of this application;

[0039] Figure 6 This is a schematic diagram of a device for improving PCB core board warping in one embodiment of this application. Detailed Implementation

[0040] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0041] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0042] In this document, spatial terms such as “upper” and “lower” are defined with reference to the accompanying drawings. Therefore, it will be understood that “upper” and “lower” are used interchangeably. It will be understood that when a layer is referred to as being “on” another layer, it can be formed directly on that other layer, or there may be intermediate layers. Therefore, it will be understood that when a layer is referred to as being “directly” on another layer, no intermediate layer is inserted in between.

[0043] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a layer or element is referred to as "on" another layer or substrate, the layer or element may be directly on said other layer or substrate, or there may be intermediate layers. Furthermore, it is understood that when a layer is referred to as "between" two layers, the layer may be the only layer between said two layers, or there may be one or more intermediate layers. Additionally, the same reference numerals always denote the same elements.

[0044] In the following text, although terms such as “first” and “second” may be used to describe various components, these components are not necessarily limited to the terms above. The terms above are used only to distinguish one component from another. It will also be understood that expressions used in the singular form include plural expressions unless the singular form has a distinct meaning in the context. Furthermore, in the embodiments below, it will also be understood that the terms “comprising” and / or “having” as used herein indicate the presence of the stated feature or component, but do not exclude the presence or addition of one or more other features or components.

[0045] In the following embodiments, when a layer, region, or element is “connected,” it can be interpreted as the layer, region, or element being connected not only directly but also through other constituent elements placed therebetween. For example, when a layer, region, element, etc., is described as being connected or electrically connected, the layer, region, element, etc., can not only be directly connected or directly electrically connected, but can also be connected or electrically connected through another layer, region, element, etc., placed therebetween.

[0046] In the application documents, the term “and / or” includes any and all combinations of one or more of the related listed items. When a statement such as “at least one of…” follows a list of elements, it modifies the entire list of elements, rather than individual elements within that list.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0048] It should also be understood that the terms “including / comprise” or “have” specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0049] Electronic or electrical devices and / or any other related devices or components according to embodiments of the inventive concepts described herein can be implemented using any suitable hardware, firmware, software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or on a separate IC chip. Alternatively, various components of these devices may be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate. Furthermore, various components of these devices may be processes or threads running on one or more processors in one or more computing devices to execute computer program instructions and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard storage devices such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of exemplary embodiments of the inventive concepts.

[0050] In related technologies, based on PCB routing rules, signal lines can be routed on the same layer as power lines and ground lines. However, for high-speed products, the return path is the shortest path for inductors and generally follows the trace path. This requires complete copper layers on both sides or one side of the signal line. High-speed products typically have strict impedance requirements, so the presence of unshielded ground plane references on both sides of the signal line directly affects the impedance of the signal line, thus requiring a separate ground plane. Power lines carry a significant amount of current, and the remaining space after routing on other layers may not be sufficient to carry the current. Therefore, a separate power plane needs to be designed, with increased copper thickness to handle the large current and optimize the power path. From a PCB manufacturing perspective, the functions of signal layers and ground planes determine the difference in their residual copper ratios. For example, signal layers have low residual copper ratios, while ground planes have high residual copper ratios. This difference translates into different residual copper ratios on both sides of a single inner core board in PCB manufacturing practice. Combined with the relaxation effect of polymer materials, the final result is uneven stress on both sides of the core board. For a single core board, the bending strength of the same type of core board decreases as the core board thickness decreases. Uneven stress can easily cause the core board to warp at the inner etching thickness; for example, reference Figure 1 As shown, the PCB board is tilted upwards along the arrow.

[0051] To address the technical deficiencies in related technologies, this invention provides a method for improving PCB core board warping, applicable to multilayer PCB structures. (Reference) Figure 2 As shown, a multilayer PCB board includes: a top layer 101, a prepreg (PP) layer 102, a ground / power layer 103, a core board 104, a signal layer 105, and a bottom layer 106. Multiple core boards 104 can be placed between the top layer 101 and the bottom layer 106. The ground layer 103 and signal layer 105 are etched on both sides of each core board 104. A prepreg layer 102 can also be placed between two adjacent core boards 104. The prepreg layer 102 mainly serves as a filler in the PCB, used to bond the core boards. Core boards of different thicknesses are laminated together using PP layers. The top layer 101 and the bottom layer 106 can serve as signal layers for placing traces and components.

[0052] In one exemplary embodiment, such as Figure 3 As shown, a method for improving PCB core board warping is provided, which is then applied to... Figure 2 Taking the PCB board as an example, the explanation includes the following steps S201 to S202. Wherein:

[0053] Step S201: Obtain the first residual copper rate corresponding to the first functional area of ​​the first functional layer of the core board, and the second residual copper rate corresponding to the second functional area of ​​the second functional layer; wherein the first functional layer and the second functional layer are located on both sides of the core board.

[0054] For example, refer to Figure 2 As shown, the first functional layer can be a ground layer on one side of the core board, and the second functional layer can be a signal layer on the other side of the core board. The first functional layer may include a first functional area and a first sealing edge area surrounding the first functional area; the second functional layer may include a second functional area and a second sealing edge area surrounding the second functional area. The first and second functional areas can be patterned areas within the board, or areas containing specific circuits and devices obtained after etching; the first and second sealing edge areas can be non-patterned areas, or sealing edge areas surrounding the functional areas on the entire printed circuit board. For example, refer to... Figure 5 As shown, multiple functional areas 301 can be planned on a single printed circuit board, and a sealing area 302 is provided on the outer side of each functional area. Two adjacent functional areas can be separated by the same sealing area 302.

[0055] Specifically, during the PCB design phase, based on the corresponding graphic design file of the core board, the first residual copper ratio corresponding to the first functional area on the first side of the core board and the second residual copper ratio corresponding to the second functional area on the second side of the core board can be calculated using software such as Genesis or InCAM. For example, for each functional layer, the residual copper ratio = copper area of ​​the graphic / profile area; where the copper area of ​​the copper layer graphic = polygon area of ​​the copper surface - bottom area of ​​the hole + inner wall area of ​​the hole + polygon perimeter of the copper surface × copper thickness, and the profile area = total board length × total board width. This application does not impose any special limitations on the specific calculation method of the residual copper ratio.

[0056] Step S202: Configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer based on the first residual copper rate and the second residual copper rate.

[0057] For example, after obtaining the residual copper ratio of the functional layers on both sides of the core board, the residual copper ratio of the outer edge sealing area can be configured according to the residual copper ratio of the pattern area. Specifically, a residual copper ratio design opposite to that of the internal pattern can be applied to the edge sealing area.

[0058] refer to Figure 4As shown, by configuring the residual copper rate of the edge sealing area according to the residual copper rate of the graphic area, the residual copper rate of the core board graphic area can be designed to be opposite to that of the residual copper rate of the edge sealing area. By controlling the use of different residual copper rates between different areas, the degree of board warping can be controlled, thereby optimizing the inner layer edge sealing during the circuit board production process and mitigating the warping phenomenon that affects the normal production of PCBs during the inner layer core board production process.

[0059] In an exemplary embodiment, in step S202 above, configuring the first residual copper rate of the first edge sealing region corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing region corresponding to the second functional layer based on the first residual copper rate and the second residual copper rate includes:

[0060] The difference in residual copper rate is determined based on the first residual copper rate and the second residual copper rate.

[0061] Based on the difference in residual copper rate, the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer are configured according to an inverse proportional relationship.

[0062] Specifically, the residual copper rate difference can be calculated based on the first residual copper rate corresponding to the first functional area of ​​the first functional layer and the second residual copper rate corresponding to the second functional area of ​​the second functional layer. This residual copper rate difference accurately represents the difference in residual copper rate between the patterned areas on both sides of the core board and determines the direction of warping. Based on this residual copper rate difference, the residual copper rate of the first edge sealing area or the second edge sealing area is configured in an inverse proportional relationship. For example, a residual copper rate difference threshold can be pre-configured. When the calculated residual copper rate difference is less than or equal to this threshold, a residual copper rate opposite to the internal rate can be applied only to the first or second edge sealing area, effectively mitigating PCB warping. Alternatively, when the calculated residual copper rate difference is greater than this threshold, a residual copper rate opposite to the internal rate can be applied to both the first and second edge sealing areas, effectively mitigating PCB warping.

[0063] For example, the first functional layer is the ground layer on one side of the core board, and the first residual copper ratio of the first functional area pattern; the second functional layer is the signal layer on the other side of the core board, and the second residual copper ratio of the second functional area pattern.

[0064] s1=ξ1*(Difference in first residual copper rate %)

[0065] Where s1 is the residual copper ratio of the grounding layer sealing edge; ξ1 is a coefficient, which is a constant; the difference in the first residual copper ratio = the second residual copper ratio - the first residual copper ratio.

[0066] s2=ξ2*(Difference in second residual copper rate %)

[0067] Where s2 is the residual copper ratio of the signal layer edge sealing; ξ2 is a coefficient, which is a constant; the difference in the second residual copper ratio = the first residual copper ratio - the second residual copper ratio.

[0068] For example, ξ1 can be configured based on the first residual copper ratio, and ξ2 can be configured based on the second residual copper ratio; for instance, when the first residual copper ratio is greater than the second residual copper ratio, ξ1 is configured to be less than ξ2.

[0069] By calculating the residual copper ratio difference between the first functional area of ​​the first functional layer and the second functional area of ​​the second functional layer, and configuring the residual copper ratio of the edge sealing area based on this residual copper ratio difference, the residual copper ratio of the edge sealing area can be precisely configured, further reducing the warping phenomenon of the PCB board.

[0070] In one exemplary embodiment, in step S202 above, the method further includes: obtaining the original warping parameters of the core board; and configuring the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer by combining the original warping parameters, the first residual copper rate and the second residual copper rate.

[0071] Specifically, when calculating the residual copper ratio in the edge-sealing area, in addition to considering the difference in residual copper ratio between the two graphic areas on both sides of the core board, the warping posture of the core board can be further considered and represented using the original warping parameters. Specifically, by calculating the original warping parameters and combining them with the difference in residual copper ratio, the warping state and specific parameter details of the core board can be described more accurately.

[0072] For example, the original warping parameters are determined based on the original warping height corresponding to the core board and the projection length of the core board in the first direction.

[0073] Among them, the original warping parameter can be the tangent value of the warping angle describing the core board; where,

[0074] Tangent of the lifting angle = h / x

[0075] Where h is the initial tilt height of the core board without design changes, and x is the projected length of the core board without design changes; this parameter can be obtained by actual measurement of the core board. The tangent of this tilt angle is proportional to 1 / d; where d is the thickness of the core board without copper.

[0076] For example, configuring the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer by combining the original warping parameters, the first residual copper rate and the second residual copper rate includes: configuring the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer by combining the original warping parameters and the residual copper rate difference; wherein, the residual copper rate difference is determined based on the first residual copper rate and the second residual copper rate.

[0077] Specifically, the residual copper rate of each edge banding area can be configured by combining the residual copper rate difference and the original warping parameter. For example, the residual copper rate difference can be calculated first, and the original warping parameter can be calculated when the residual copper rate difference is greater than a preset threshold; the residual copper rate difference and the original warping parameter can then be used to configure the residual copper rate of each edge banding area.

[0078] For example, refer to Figure 2 As shown, the first functional layer is the ground layer on one side of the core board, and the first residual copper ratio of the first functional area pattern is shown; the second functional layer is the signal layer on the other side of the core board, and the second residual copper ratio of the second functional area pattern is shown; correspondingly, the formula for calculating the residual copper ratio may include:

[0079]

[0080]

[0081] Where ξ1 and ξ2 are coefficients, and ξ2 is a constant; ξ1 can be configured according to the first residual copper ratio, and ξ2 can be configured according to the second residual copper ratio; tanθ is the tangent of the tilt angle; the residual copper ratio difference can be the absolute value of the difference between the residual copper ratio of the signal layer and the residual copper ratio of the ground layer.

[0082] For example, the residual copper content in the edge-sealing area can also be calculated using only the difference in residual copper content and the tangent of the warping angle. The calculation formula may include:

[0083]

[0084]

[0085] For example, the difference in residual copper rate is used to represent the difference in residual copper rate on both sides of the core board, and the degree of core board warping is represented by the warping angle tangent. By using the difference in residual copper rate between the ground layer and the signal layer, and the warping angle tangent, the residual copper rate of the sealing area is calculated. This allows for correction of core board warping from multiple data dimensions, accurate configuration of residual copper rate in the sealing area, and maximizing the elimination of PCB board warping.

[0086] In one exemplary embodiment, the first edge sealing region includes a first process strip, and the second edge sealing region includes a second process strip; the method further includes: configuring process strip parameters of the corresponding process strip of the edge sealing region based on the residual copper ratio of the edge sealing region.

[0087] For example, process strips can be set separately for each edge-sealing area; for instance, the pattern of the process strips can be constructed by etching. (See reference) Figure 5 As shown, a process strip can include several layers of elements arranged sequentially; the elements can be cubic structures with a rectangular cross-section. In the same row of elements, there is a gap between two adjacent process strip elements; in two adjacent rows of elements, the elements can be staggered to form a "wall" pattern. Process strips can be set in the sealing area of ​​the signal layer, and / or in the sealing area of ​​the ground layer.

[0088] For example, process strip parameters may include any one or a combination of any of the following: element arrangement direction, element size, element spacing, and number of element layers.

[0089] For example, to facilitate control of adhesive flow, refer to Figure 5 As shown, the element arrangement direction can be set so that the long side of the element is horizontal to the graphic area. Furthermore, to facilitate control of the glue flow rate, the density of the elements can be controlled by adjusting the spacing between elements and the number of element layers, thereby adjusting the glue flow rate. For example, as... Figure 5 As shown, the element layer is configured with 3 layers. Alternatively, in other exemplary embodiments, the element layer can be set to 2 layers. Furthermore, considering the bending strength of the process strip, the dimensions of the elements, including the length and width of the elements, can also be configured.

[0090] In one exemplary embodiment, the process strip parameters of the corresponding process strip for the edge sealing area are configured based on the residual copper rate of the edge sealing area, including: configuring the process strip parameters based on the residual copper rate of the edge sealing area and the target performance parameters corresponding to the process strip; wherein, the target performance parameters of the process strip include: strength parameters.

[0091] Specifically, the target performance parameters of the process strip can include strength parameters, namely, the bending strength of the process strip. After determining the residual copper ratio in the sealing area, the parameters of the elements in the process strip can be designed based on the residual copper ratio and bending strength. The bending strength F of the process strip is directly proportional to the size of the process strip elements and the number of element layers. For example,

[0092]

[0093] Where η is a coefficient and is a constant.

[0094] For example, the bending strength can be a range of strength values. First, the size and number of element layers can be configured based on the bending strength F. Then, it can be calculated whether the corresponding pattern meets the residual copper ratio requirements of the edge sealing area. For example, the first residual copper ratio of the first edge sealing area corresponding to the first functional layer, and / or the second residual copper ratio of the second edge sealing area corresponding to the second functional layer. If not, the element size and / or quantity can be adjusted until the bending strength and residual copper ratio meet the preset requirements.

[0095] In one exemplary embodiment, configuring the process strip parameters of the process strip corresponding to the edge sealing area based on the residual copper rate of the edge sealing area includes: configuring the process strip parameters according to the residual copper rate of the edge sealing area, the target performance parameters corresponding to the process strip, and the dielectric layer thickness parameters; wherein, the dielectric layer thickness parameters are determined based on the adhesive flow rate and the process strip structure.

[0096] Specifically, the theoretical thickness of the dielectric layer can be determined based on the copper thickness of the prepreg layer, and the calculation formula can include:

[0097]

[0098] Where T is the theoretical thickness of the dielectric layer; ε1 is the residual copper ratio on the upper surface of PP; ε2 is the residual copper ratio on the lower surface of PP; t1 is the copper thickness on the upper surface of PP; and t2 is the copper thickness on the lower surface of PP.

[0099] The actual thickness of the dielectric layer can be determined based on the theoretical thickness and the amount of adhesive flow. The calculation formula may include:

[0100]

[0101] Where T1 is the actual thickness of the dielectric layer; f is the amount of adhesive applied; and S is the board area. By controlling the amount of adhesive applied, the required board thickness can be achieved, thus controlling the dielectric layer thickness and consequently, the impedance. Furthermore, the amount of adhesive applied is directly proportional to the substrate flowability and the spacing between elements in the process strip; this can be expressed by the formula:

[0102]

[0103] The number of openings in the process strip can be determined based on the number of elements in each row.

[0104] For example, after determining the residual copper ratio of the edge sealing area, the process strip parameters corresponding to the specific graphic of the edge sealing area process strip can be configured based on the relationship between the amount of adhesive flow and the element, and the relationship between the element and the bending strength; for example, setting the number of element layers, the arrangement direction of the element, the element size, and the gap size between the elements.

[0105] By incorporating wall-like process strips in the edge-sealing area, the bending strength can be effectively enhanced while meeting the residual copper ratio requirements and effectively mitigating warping. Furthermore, by using multiple elements to create the process strip pattern, compared to existing technologies that use all-copper strips, normal adhesive flow can be ensured, reducing the obstruction of adhesive flow during subsequent lamination. Moreover, by adjusting the size and spacing of the elements, the density of the process strips can be adjusted, thereby achieving effective control over the adhesive flow.

[0106] The method for improving PCB core board warping provided in this application first determines the residual copper ratio corresponding to the patterned areas of the functional layers on both sides of the core board. Based on this residual copper ratio, the difference in residual copper ratio between the two functional layers can be calculated. Based on the residual copper ratio or the difference in residual copper ratio, the residual copper ratio corresponding to the edge sealing area can be configured inversely proportionally. This achieves the application of a residual copper ratio design opposite to the internal pattern in the edge sealing area, thereby alleviating PCB warping. Furthermore, by using the specific residual copper ratio value, the pattern, size, and density of the process strips in the edge sealing area can be specifically configured to effectively adjust the degree of control over board warping and the amount of adhesive applied during subsequent lamination; thus optimizing the inner layer edge sealing during PCB manufacturing.

[0107] Based on the same inventive concept, this application also provides an apparatus for improving PCB core board warping to implement the above-described method for improving PCB core board warping. The solution provided by this apparatus is similar to the solution described in the above-described method. Therefore, the specific limitations of one or more embodiments of the apparatus for improving PCB core board warping provided below can be found in the limitations of the method for improving PCB core board warping described above, and will not be repeated here.

[0108] In one exemplary embodiment, such as Figure 6 As shown, an apparatus 60 for improving PCB core board warping is provided, comprising: a first residual copper rate acquisition module 601 and a second residual copper rate configuration module 602, wherein:

[0109] The first residual copper rate acquisition module 601 is used to acquire the first residual copper rate corresponding to the first functional area of ​​the first functional layer of the core board, and the second residual copper rate corresponding to the second functional area of ​​the second functional layer; wherein the first functional layer and the second functional layer are respectively located on both sides of the core board.

[0110] The second residual copper rate configuration module 602 is used to configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer based on the first residual copper rate and the second residual copper rate.

[0111] In an exemplary embodiment, the second residual copper rate configuration module 602 can be used to determine the residual copper rate difference based on the first residual copper rate and the second residual copper rate; and based on the residual copper rate difference, configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer based on an inverse proportional relationship.

[0112] In an exemplary embodiment, the device further includes: a warping parameter calculation module, used to obtain the original warping parameters of the core board; and to configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer by combining the original warping parameters, the first residual copper rate and the second residual copper rate.

[0113] In an exemplary embodiment, the warping parameter calculation module is used to combine the original warping parameter and the residual copper rate difference to configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer, and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer; wherein, the residual copper rate difference is determined based on the first residual copper rate and the second residual copper rate.

[0114] In an exemplary embodiment, the original warping parameters are determined based on the original warping height corresponding to the core board and the projection length of the core board in the first direction.

[0115] In one exemplary embodiment, the first edge-sealing area includes a first process strip, and the second edge-sealing area includes a second process strip; the device further includes:

[0116] The process strip parameter calculation module is used to configure the process strip parameters corresponding to the edge sealing area based on the residual copper rate of the edge sealing area.

[0117] In an exemplary embodiment, the process strip parameter calculation module is used to configure the process strip parameters based on the residual copper rate of the sealing area and the target performance parameters corresponding to the process strip; wherein, the target performance parameters of the process strip include: strength parameters.

[0118] In an exemplary embodiment, the process strip parameter calculation module is used to configure the process strip parameters based on the residual copper rate of the sealing area, the target performance parameters corresponding to the process strip, and the dielectric layer thickness parameters; wherein the dielectric layer thickness parameters are determined based on the adhesive flow rate and the process strip structure.

[0119] In one exemplary embodiment, the process strip comprises several layers of elements arranged sequentially;

[0120] The process parameters include any one or a combination of any of the following: element arrangement direction, element size, element spacing, and number of element layers.

[0121] The modules in the aforementioned device for improving PCB core board warping can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0122] Based on the same inventive concept, this application also provides a printed circuit board, including at least one core board, with a first functional layer and a second functional layer respectively disposed on both sides of the core board; the first functional layer includes a first functional area and a first edge sealing area disposed around the first functional area; the second functional layer includes a second functional area and a second edge sealing area disposed around the second functional area; wherein, the first residual copper ratio of the first edge sealing area corresponding to the first functional layer and / or the second residual copper ratio of the second edge sealing area corresponding to the second functional layer are configured based on the first residual copper ratio of the first functional area and the second residual copper ratio of the second functional area.

[0123] For example, the first residual copper ratio of the first edge sealing area and / or the second residual copper ratio corresponding to the second edge sealing area of ​​the printed circuit board can be optimized using the method for improving PCB core board warping described in any of the above embodiments.

[0124] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0125] Step 201: Obtain the first residual copper ratio corresponding to the first functional area of ​​the first functional layer of the core board, and the second residual copper ratio corresponding to the second functional area of ​​the second functional layer; wherein the first functional layer and the second functional layer are located on both sides of the core board respectively;

[0126] Step 202: Configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer based on the first residual copper rate and the second residual copper rate.

[0127] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0128] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0130] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for improving PCB core board warping, characterized in that, The method includes: The first residual copper ratio corresponding to the first functional area of ​​the first functional layer of the core board and the second residual copper ratio corresponding to the second functional area of ​​the second functional layer are obtained; wherein the first functional layer and the second functional layer are located on both sides of the core board respectively; Obtain the original warping parameters of the core board; the original warping parameters are determined based on the original warping height of the core board and the projection length of the core board in the first direction; Combining the original warping parameters and the residual copper rate difference, configure the first residual copper rate of the first edge sealing area corresponding to the first functional layer, and / or the second residual copper rate of the second edge sealing area corresponding to the second functional layer; wherein, the residual copper rate difference is determined based on the first residual copper rate and the second residual copper rate; the first edge sealing area includes a first process strip, and the second edge sealing area includes a second process strip; Based on the residual copper rate of the edge sealing area, configure the process strip parameters corresponding to the edge sealing area.

2. The method according to claim 1, characterized in that, The process strip parameters for the corresponding process strip of the edge-sealing area are configured based on the residual copper rate of the edge-sealing area, including: Based on the residual copper rate of the sealing area and the target performance parameters corresponding to the process strip, the parameters of the process strip are configured; wherein, the target performance parameters of the process strip include: strength parameters.

3. The method according to claim 1, characterized in that, The process strip parameters for the corresponding process strip of the edge-sealing area are configured based on the residual copper rate of the edge-sealing area, including: The process strip parameters are configured based on the residual copper rate of the sealing area, the target performance parameters corresponding to the process strip, and the dielectric layer thickness parameters; wherein, the dielectric layer thickness parameters are determined based on the adhesive flow rate and the process strip structure.

4. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 3.

5. A printed circuit board, characterized in that, The printed circuit board is made using the method described in any one of claims 1 to 3; the printed circuit board includes at least one core board, and a first functional layer and a second functional layer are respectively disposed on both sides of the core board; The first functional layer includes a first functional area and a first sealing edge area disposed around the first functional area; The second functional layer includes a second functional area and a second sealing area disposed around the perimeter of the second functional area; The first residual copper ratio of the first edge sealing area corresponding to the first functional layer and / or the second residual copper ratio of the second edge sealing area corresponding to the second functional layer are configured based on the first residual copper ratio of the first functional area and the second residual copper ratio of the second functional area.

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