A layout structure of a PIP capacitor and a PIP capacitor

Abstract

The present invention discloses a layout structure of a PIP capacitor and a PIP capacitor, wherein the layout structure of the PIP capacitor includes: a first polysilicon layer; a second polysilicon layer, located on one side of the first polysilicon layer and spaced apart from the first polysilicon layer; and an external electric field shielding layer, located on the side of the second polysilicon layer away from the first polysilicon layer. The technical solution provided by the embodiment of the present invention reduces the dielectric polarization and charge dispersion caused by the external electric field on the capacitor dielectric layer, thereby reducing the influence of the external electric field on the device performance.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of electronic technology, and in particular to a layout structure of a PIP capacitor and a PIP capacitor. Background Art

[0002] Up to now, there are many capacitors available for semiconductor integrated circuit design, including MOS (metal-oxide-semiconductor) capacitors, PIP (polysilicon-insulator-polysilicon) capacitors, MIM (metal-insulator-metal) capacitors, MOM (metal-oxide-metal) capacitors, etc. In order to meet customers' requirements for capacitor characteristics and low cost, PIP capacitors have been widely used.

[0003] Usually in actual production, the upper and lower plates of the PIP capacitor are doped with phosphorus, which can not only obtain electrodes with smaller sheet resistance, but also minimize the voltage modulation effect caused by polysilicon depletion. At the same time, if the device is placed in a deep N-well, the heavily doped phosphorus will also accelerate local oxidation, forming a thick field oxide layer under the device, thereby reducing the parasitic capacitance between the lower plate of the capacitor and the substrate. However, the oxide layer dielectric introduced by the PIP capacitor will produce the following defects: 1) Dielectric polarization; Dielectric polarization refers to the phenomenon that the movement of charges in the insulator generates an electrostatic field. This electrostatic field comes from the redistribution of mobile ions in the oxide under an external electric field. When the electric field is enhanced, this electrostatic field weakens the original electric field strength. When the external electric field is removed, the redistribution of mobile ions causes a weak electric field in the capacitor that is opposite to the original electric field. The specific manifestation of this phenomenon on the PIP capacitor is: when the capacitor is charged, with the dielectric polarization phenomenon generated by the oxide layer and the silicon surface, the original electric field strength is weakened, the capacitor voltage drops, and it cannot reach the expected level. When the capacitor is discharged and disconnected, polarization causes a reverse bias voltage to form between the two plates. 2) Charge dispersion: Charge dispersion refers to the rapid accumulation or dispersion of static charge on the surface of an insulator under the action of an electric field. The effect of this phenomenon on PIP capacitance is similar to that caused by dielectric polarization. The difference is that the polarization rate limits the effect of dielectric polarization on capacitance, but charge dispersion is usually very fast and has a greater impact on capacitance in high-frequency application scenarios.

[0004] The dielectric polarization and charge dispersion generated by the electric field of the capacitor itself cannot usually be eliminated. The use of different dielectrics and growth processes can reduce these two to a negligible level. However, dielectric polarization and charge dispersion are not only generated by the electric field of the capacitor itself, but also by the external electric field. Therefore, how to reduce the impact of the external electric field on the PIP capacitor has become a technical problem that needs to be solved urgently by people in this field. Summary of the invention

[0005] The embodiments of the present invention provide a layout structure of a PIP capacitor and a PIP capacitor to reduce dielectric polarization and charge dispersion caused by an external electric field on a capacitor dielectric, thereby reducing the impact on device performance.

[0006] According to one aspect of the present invention, a layout structure of a PIP capacitor is provided, comprising:

[0007] a first polysilicon layer;

[0008] a second polysilicon layer, located on one side of the first polysilicon layer and spaced apart from the first polysilicon layer;

[0009] The external electric field shielding layer is located on a side of the second polysilicon layer away from the first polysilicon layer.

[0010] Optionally, the external electric field shielding layer is electrically connected to the first polysilicon layer.

[0011] Optionally, the second polysilicon layer includes a plurality of second polysilicon sub-layers extending along a first direction and arranged at intervals along a second direction; wherein the first direction is arranged to intersect with the second direction.

[0012] Optionally, the layout structure of the PIP capacitor further includes a first electrode and a second electrode;

[0013] The first electrode is electrically connected to the first polysilicon layer, and the second electrode is electrically connected to the second polysilicon layer; the first electrode is used to provide a first electrical signal to the first polysilicon layer; the second electrode is used to provide a second electrical signal to the second polysilicon layer.

[0014] Optionally, the first electrode and the second electrode are located in the same metal electrode layer, or in different metal electrode layers.

[0015] Optionally, when the first electrode and the second electrode are located in the same metal electrode layer, the first electrode and the second electrode form an interdigitated structure.

[0016] Optionally, the metal electrode layer is located between the external electric field shielding layer and the second polysilicon layer;

[0017] The first electrode is electrically connected to the first polysilicon layer through a plurality of first connection holes;

[0018] The second electrode is electrically connected to the second polysilicon layer through a plurality of second connection holes.

[0019] Optionally, in the case where the second polysilicon layer includes a plurality of second polysilicon sublayers extending along the first direction and arranged at intervals along the second direction;

[0020] The first electrode comprises a plurality of first electrode strips extending along the first direction and arranged at intervals along the second direction;

[0021] The second electrode comprises a plurality of second electrode strips extending along the first direction and arranged at intervals along the second direction;

[0022] The first electrode strip and the second electrode strip are arranged in sequence at intervals, and a vertical projection of the first electrode strip on the first polysilicon layer and a vertical projection of the second polysilicon sublayer on the first polysilicon layer at least partially do not overlap; a vertical projection of the second electrode strip on the first polysilicon layer and a vertical projection of the second polysilicon sublayer on the first polysilicon layer at least partially overlap.

[0023] Optionally, the area of ​​the first polysilicon layer is greater than the area of ​​the second polysilicon layer, and the area of ​​the external electric field shielding layer is greater than the area of ​​the second polysilicon layer.

[0024] According to another aspect of the present invention, a PIP capacitor is provided, which is prepared based on the layout structure of the PIP capacitor described in any embodiment of the present invention.

[0025] The embodiment of the present invention provides a layout structure of a PIP capacitor and a PIP capacitor, wherein the layout structure of the PIP capacitor includes: a first polysilicon layer; a second polysilicon layer, located on one side of the first polysilicon layer and spaced apart from the first polysilicon layer; and an external electric field shielding layer, located on the side of the second polysilicon layer away from the first polysilicon layer. The technical solution provided by the embodiment of the present invention provides an external electric field shielding layer on the side of the second polysilicon layer away from the first polysilicon layer, and shields the external electric field through the external electric field shielding layer, so as to reduce the dielectric polarization and charge dispersion caused by the external electric field on the capacitor dielectric, thereby reducing the impact on the device performance.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 is a cross-sectional view of a layout junction of a PIP capacitor provided by an embodiment of the present invention;

[0029] Figure 2is a top view of a second polysilicon layer provided by an embodiment of the present invention;

[0030] Figure 3 is a cross-sectional view of another layout junction of a PIP capacitor provided by an embodiment of the present invention;

[0031] Figure 4 is a top view of an interdigital structure composed of a first electrode and a second electrode provided in an embodiment of the present invention;

[0032] Figure 5 is a top perspective view of a layout junction of a PIP capacitor provided by an embodiment of the present invention;

[0033] Figure 6 yes Figure 5 A cross-sectional view of the structure shown along section line EE1;

[0034] Figure 7 is an equivalent circuit diagram of a PIP capacitor provided by an embodiment of the present invention;

[0035] Figure 8 is an equivalent circuit diagram of another PIP capacitor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] An embodiment of the present invention provides a layout structure of a PIP capacitor, including:

[0039] a first polysilicon layer;

[0040] A second polysilicon layer is located on one side of the first polysilicon layer and is spaced apart from the first polysilicon layer;

[0041] The external electric field shielding layer is located on a side of the second polysilicon layer away from the first polysilicon layer.

[0042] The technical solution provided by the embodiment of the present invention provides an external electric field shielding layer on the side of the second polysilicon layer away from the first polysilicon layer, so that the external electric field shielding layer can shield the external electric field, thereby reducing the dielectric polarization and charge dispersion caused by the external electric field on the capacitor dielectric layer, thereby reducing the impact on device performance.

[0043] The above is the core inventive concept of the present invention. For ease of understanding, the layout structure of the PIP capacitor is described in detail below with reference to the accompanying drawings.

[0044] Figure 1 is a cross-sectional view of a layout of a PIP capacitor provided by an embodiment of the present invention, with reference to Figure 1 , the first polysilicon layer 10 is used as the lower electrode; the second polysilicon layer 20 is used as the upper electrode. The layout structure of the PIP capacitor also includes a dielectric layer 40, and a dielectric layer 40 is arranged between the first polysilicon layer 10 and the second polysilicon layer 20. The external electric field shielding layer 30 is located on the side of the second polysilicon layer 20 away from the first polysilicon layer 10, that is, the external electric field shielding layer 30 is arranged between the external electric field and the second polysilicon layer 20. The external electric field shielding layer 30 can input an electric signal with the same potential as the first polysilicon layer, so that the external electric field shielding layer 30 can shield the external electric field, so as to reduce the dielectric polarization and charge dispersion caused by the external electric field on the capacitor dielectric layer, thereby reducing the impact on the device performance.

[0045] Based on the above embodiments, Figure 1 Optionally, the external electric field shielding layer 30 is electrically connected to the first polysilicon layer 10 so that the electrical signal connected to the external electric field shielding layer 30 and the second polysilicon layer 20 is the same.

[0046] Specifically, the external electric field shielding layer 30 covers the polysilicon upper plate (the second polysilicon layer 20) adjacent to the external electric field, and the external electric field shielding layer 30 is connected to the polysilicon lower plate (the first polysilicon layer 10) of the PIP capacitor, so that the electrical signal connected to the external electric field shielding layer 30 and the second polysilicon layer 20 is the same, forming a sandwich capacitor structure, which can shield the external electric field, thereby reducing the dielectric polarization and charge dispersion caused by the external electric field on the capacitor dielectric layer 40, and reducing the impact on the device performance. In addition, the external electric field shielding layer 30 is electrically connected to the first polysilicon layer 10, so that the external electric field shielding layer 30 and the second polysilicon layer 20 can share the same electrode to input the electrical signal, without the need to additionally set an electrode electrically connected to the external electric field shielding layer 30, thereby reducing the cost and thickness of the device.

[0047] Based on the above embodiments, please continue to refer to Figure 1 Optionally, the area of ​​the first polysilicon layer 10 is larger than the area of ​​the second polysilicon layer 20, and the area of ​​the external electric field shielding layer 30 is larger than the area of ​​the second polysilicon layer 20, thereby achieving the effect of suppressing the edge electric field.

[0048] The vertical projection of the second polysilicon layer 20 on the first polysilicon layer 10 is located inside the first polysilicon layer 10; the distance from the boundary of the first polysilicon layer 10 to the boundary of the vertical projection of the second polysilicon layer 20 on the first polysilicon layer 10 is greater than or equal to 1.5um. The vertical projection of the second polysilicon layer 20 on the external electric field shielding layer 30 is located inside the external electric field shielding layer 30; the distance from the boundary of the external electric field shielding layer 30 to the boundary of the vertical projection of the second polysilicon layer 20 on the external electric field shielding layer 30 is greater than or equal to 1.5um.

[0049] Based on the above embodiments, Figure 2 is a top view of a second polysilicon layer 20 provided in an embodiment of the present invention, with reference to Figure 2 Optionally, the second polysilicon layer 20 includes a plurality of second polysilicon sub-layers 201 extending along the first direction X and arranged at intervals along the second direction Y; wherein the first direction X and the second direction Y are arranged to intersect. Figure 2 It is shown that the first direction X and the second direction Y are perpendicular to each other.

[0050] Specifically, the second polysilicon layer 20 is etched into strips to form a plurality of second polysilicon sublayers 201 extending along the first direction X and arranged at intervals along the second direction Y. A PIP subcapacitor is formed between each second polysilicon sublayer 201 and the first polysilicon layer 10, thereby forming a plurality of PIP subcapacitors. The plurality of PIP subcapacitors are connected in parallel to form an overall PIP capacitor. Dividing the second polysilicon layer 20 into a plurality of second polysilicon sublayers 201 extending along the first direction X and arranged at intervals along the second direction Y can effectively reduce the parasitic resistance inside the upper and lower plates, thereby improving the performance of the capacitor device.

[0051] Based on the above embodiments, Figure 3 is a cross-sectional view of another layout of a PIP capacitor provided by an embodiment of the present invention, with reference to Figure 3 , Optionally, the layout structure of the PIP capacitor further includes a first electrode 50 and a second electrode 60;

[0052] The first electrode 50 is electrically connected to the first polysilicon layer 10, and the second electrode 60 is electrically connected to the second polysilicon layer 20; the first electrode 50 is used to provide a first electrical signal to the first polysilicon layer 10; the second electrode 60 is used to provide a second electrical signal different from the first electrical signal to the second polysilicon layer 20.

[0053] Specifically, the materials of the first electrode 50 and the second electrode 60 may be metal materials, and the first electrode 50 and the second electrode 60 may be located in the same metal electrode layer or in different metal electrode layers. Figure 3 It is exemplarily shown that the first electrode 50 and the second electrode 60 are located in different metal electrode layers.

[0054] refer to Figure 3 When the first electrode 50 and the second electrode 60 are located in different metal electrode layers, the first electrode 50 can be located on a side of the first polysilicon layer 10 away from the second polysilicon layer 20, and the second electrode 60 can be located on a side of the second polysilicon layer 20 away from the first polysilicon layer 10, thereby reducing the distance from the first electrode 50 to the first polysilicon layer 10, and reducing the distance from the second electrode 60 to the second polysilicon layer 20, thereby facilitating the electrical connection between the first electrode 50 and the first polysilicon layer 10, and facilitating the electrical connection between the second electrode 60 and the second polysilicon layer 20.

[0055] In another embodiment of the present invention, when the first electrode 50 and the second electrode 60 are located in different metal electrode layers, the first electrode 50 can be located in the same metal layer as the external electric field shielding layer 30, or the external electric field shielding layer 30 can be reused as the first electrode 50, thereby achieving the effect of reducing the cost and thickness of the capacitor device.

[0056] When the first electrode 50 and the second electrode 60 are located in the same metal electrode layer, the cost and thickness of the capacitor device can be reduced.

[0057] Based on the above embodiments, Figure 4 is a top view of an interdigital structure composed of a first electrode and a second electrode provided in an embodiment of the present invention, with reference to Figure 4 Optionally, when the first electrode 50 and the second electrode 60 are located in the same metal electrode layer, the first electrode 50 and the second electrode 60 form an interdigitated structure.

[0058] Specifically, the first electrode and the second electrode are arranged in the same layer and located in the same metal electrode layer. The first electrode includes a plurality of first electrode strips 51 extending along the first direction X and arranged at intervals along the second direction Y; the second electrode includes a plurality of second electrode strips 61 extending along the first direction X and arranged at intervals along the second direction Y; the first electrode strips 51 and the second electrode strips 61 are arranged at intervals in sequence. The layout structure of the PIP capacitor also includes a first connecting line 52 electrically connected to each first electrode strip 51, and a second connecting line 62 electrically connected to each second electrode strip 61. The first connecting line 52 and the second connecting line 62 are located on opposite sides of the layout structure of the PIP capacitor, so that the first electrode and the second electrode form an interdigitated structure.

[0059] The first connection line 52 and the second connection line 62 may be located in the same metal layer as the first electrode 50 and the second electrode 60, or may be located in different metal layers. Preferably, the first connection line 52 and the second connection line 62 and the first electrode 50 and the second electrode 60 are located in the same metal layer, so as to achieve the effect of reducing the cost and thickness of the capacitor device, and facilitate the electrical connection between the first connection line 52 and the first electrode strip 51, and facilitate the electrical connection between the second connection line 62 and the second electrode strip 61.

[0060] In the embodiment of the present invention, the first electrode 50 and the second electrode 60 are disposed on the same metal electrode layer, and the first electrode 50 and the second electrode 60 form an interdigital structure, so as to reduce the cost and thickness of the capacitor device, prevent the short circuit between the first electrode 50 and the second electrode 60, and ensure that the first electrode 50 can be distributed in the entire area above the first polysilicon layer 10, and ensure that the second electrode 60 can be distributed in the entire area above the second polysilicon layer 20. Therefore, the contact part between the first polysilicon layer 10 and the first electrode 50 can be distributed in various areas of the first polysilicon layer 10, and the contact part between the second polysilicon layer 20 and the second electrode 60 can be distributed in various areas of the second polysilicon layer 20, thereby reducing the voltage difference between different areas in the first polysilicon layer 10, and reducing the voltage difference between different areas in the second polysilicon layer 20.

[0061] Based on the above embodiments, optionally, the first electrode 50 is electrically connected to the first polysilicon layer 10 through a plurality of first connection holes; the second electrode is electrically connected to the second polysilicon layer 20 through a plurality of second connection holes. An insulating layer may be provided on the hole walls of the first connection holes and the hole walls of the second connection holes to prevent the occurrence of short circuit problems.

[0062] Furthermore, the first connection holes are evenly arranged between the first electrode strip 51 and the first polysilicon layer 10, and the second connection holes are evenly arranged between the second electrode strip 61 and the second polysilicon layer 20. Thus, the contact portion between the first polysilicon layer 10 and the first electrode 50 can be evenly distributed in the first polysilicon layer 10, and the contact portion between the second polysilicon layer 20 and the second electrode 60 can be evenly distributed in the second polysilicon layer 20, thereby further reducing the voltage difference between different regions in the first polysilicon layer 10, and reducing the voltage difference between different regions in the second polysilicon layer 20.

[0063] Based on the above embodiments, Figure 5 is a top perspective view of a layout of a PIP capacitor provided by an embodiment of the present invention, Figure 6 yes Figure 5 The structure shown is a cross-sectional view along the section line EE1, refer to Figure 5 and Figure 6, Optionally, in the case where the second polysilicon layer 20 includes a plurality of second polysilicon sublayers 201 extending along the first direction X and arranged at intervals along the second direction Y;

[0064] The vertical projection of the first electrode strip 51 on the first polysilicon layer 10 at least partially does not overlap with the vertical projection of the second polysilicon sublayer 201 on the first polysilicon layer 10; the vertical projection of the second electrode strip 61 on the first polysilicon layer 10 at least partially overlaps with the vertical projection of the second polysilicon sublayer 201 on the first polysilicon layer 10.

[0065] Specifically, the vertical projection of the first electrode strip 51 on the first polysilicon layer 10 and the vertical projection of the second polysilicon sublayer 201 on the first polysilicon layer 10 at least partially do not overlap, which can be understood as follows: the vertical projection of the first electrode strip 51 on the first polysilicon layer 10 and the vertical projection of the second polysilicon sublayer 201 on the first polysilicon layer 10 do not overlap (refer to Figure 5 and Figure 6 ), or the vertical projection of the first electrode strip 51 on the first polysilicon layer 10 partially overlaps with the vertical projection of the second polysilicon sublayer 201 on the first polysilicon layer 10 (not shown). The first connection hole 53 is located in the non-overlapping area, so that the first connection hole 53 between the first electrode strip 51 and the first polysilicon layer 10 does not need to penetrate the second polysilicon sublayer 201, and further does not need to provide an insulating layer on the hole wall of the first connection hole 53, and can also prevent the conductive material in the first connection hole 53 from being electrically connected to the second polysilicon sublayer 201 and causing a short circuit.

[0066] The vertical projection of the second electrode strip 61 on the first polysilicon layer 10 at least partially overlaps with the vertical projection of the second polysilicon sublayer 201 on the first polysilicon layer 10. It can be understood that the vertical projection of the second electrode strip 61 on the first polysilicon layer 10 is located within the vertical projection of the second polysilicon sublayer 201 on the first polysilicon layer 10 (refer to Figure 5 and Figure 6 ), or the vertical projection of the second electrode strip 61 on the first polysilicon layer 10 partially overlaps with the vertical projection of the second polysilicon sublayer 201 on the first polysilicon layer 10 (not shown). The second connection hole 63 is located in the overlapping area, so that the direction in which the second connection hole 63 extends toward the second polysilicon sublayer 201 is perpendicular to the direction of the second polysilicon layer 20 (third direction Z), reducing the difficulty of preparing the second connection hole 63. The third direction is perpendicular to the first direction X and perpendicular to the second direction Y at the same time.

[0067] The first electrode and the second electrode are located in the same metal electrode layer 56, and the metal electrode layer 56 is located between the external electric field shielding layer 30 and the second polysilicon layer 20. To avoid short circuit, a dielectric layer 40 is provided between the second polysilicon layer 20 and the metal electrode layer 56, and another dielectric layer 40 is provided between the first polysilicon layer 10 and the second polysilicon layer 20. The first electrode strip 51 is electrically connected to the first polysilicon layer 10 through a plurality of first connection holes 53; the second electrode strip 61 is electrically connected to the second polysilicon layer 20 through a plurality of second connection holes 63. The first connection holes 53 sequentially penetrate the dielectric layer 40 between the second polysilicon layer 20 and the metal electrode layer 56, the dielectric layer 40 between the adjacent second polysilicon sublayers 201, and the dielectric layer 40 between the second polysilicon layer 20 and the first polysilicon layer 10. The second connection holes 63 penetrate the dielectric layer 40 between the second polysilicon layer 20 and the metal electrode layer 56. The external electric field shielding layer 30 is electrically connected to the first polysilicon layer 10 through the third connection hole 31 .

[0068] Figure 7 is an equivalent circuit diagram of a PIP capacitor provided by an embodiment of the present invention, referring to Figure 7 , exemplarily, R0-R4 are the parasitic resistances of the lower plate of the PIP capacitor without interdigital electrode contact; R5-R9 are the parasitic resistances of the lower plate of the PIP capacitor without interdigital electrode contact; C1-C6 are PIP sub-capacitors between the upper and lower plates, which are connected in parallel to form an overall capacitor. Figure 8 is another equivalent circuit diagram of a PIP capacitor provided by an embodiment of the present invention, referring to Figure 8 , R10-R14 is the parasitic resistance of the lower plate of the capacitor with interdigital electrode contact; R15-R19 is the parasitic resistance of the lower plate of the capacitor with interdigital electrode contact; C7-C12 is the PIP sub-capacitor between the upper and lower plates, which are connected in parallel to form an overall capacitor. Port A is the second electrical signal input port, and port B is the first electrical signal input port. Comparison Figure 7 and Figure 8 It can be seen that the use of interdigital electrode contacts and dividing the upper plate of the PIP capacitor into strips can effectively reduce the parasitic resistance inside the upper and lower plates and improve the device performance.

[0069] The embodiment of the present invention further provides a PIP capacitor, which is prepared based on the layout structure of the PIP capacitor described in any embodiment of the present invention, and has the same technical effect, which will not be described in detail here.

[0070] In one embodiment of the present invention, reference Figure 1The method for forming a PIP capacitor may include: forming a shallow trench isolation structure in a substrate, forming a first polysilicon layer 10 on the shallow trench isolation structure as a lower plate of the PIP capacitor; forming an oxide layer on the first polysilicon layer 10 as a dielectric layer 40 of the PIP capacitor; forming a second polysilicon layer 20 on the oxide layer, and the second polysilicon layer 20 as an upper plate of the PIP capacitor. An oxide layer is formed on the second polysilicon layer 20 as a dielectric layer (not shown) isolating the second polysilicon layer 20 from the external electric field shielding layer 30, and the external electric field shielding layer 30 is formed on the dielectric layer. The material of the external electric field shielding layer 30 may be a metal material.

[0071] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A layout structure of a PIP capacitor, characterized in that: include: a first polysilicon layer; a second polysilicon layer, located on one side of the first polysilicon layer and spaced apart from the first polysilicon layer; an external electric field shielding layer, located on a side of the second polysilicon layer away from the first polysilicon layer; The external electric field shielding layer is electrically connected to the first polysilicon layer; The layout structure of the PIP capacitor also includes a first electrode and a second electrode; The first electrode and the second electrode are located in the same metal electrode layer, or in different metal electrode layers; When the first electrode and the second electrode are located in different metal electrode layers, the first electrode and the external electric field shielding layer are located in the same metal layer, or the external electric field shielding layer is reused as the first electrode.

2. The layout structure of the PIP capacitor according to claim 1, characterized in that: The second polysilicon layer includes a plurality of second polysilicon sub-layers extending along a first direction and arranged at intervals along a second direction; wherein the first direction is arranged to intersect with the second direction.

3. The layout structure of the PIP capacitor according to any one of claims 1 to 2, characterized in that: The first electrode is electrically connected to the first polysilicon layer, and the second electrode is electrically connected to the second polysilicon layer; the first electrode is used to provide a first electrical signal to the first polysilicon layer; the second electrode is used to provide a second electrical signal to the second polysilicon layer.

4. The layout structure of the PIP capacitor according to claim 1, characterized in that: In the case where the first electrode and the second electrode are located in the same metal electrode layer; The first electrode and the second electrode form an interdigital structure.

5. The layout structure of the PIP capacitor according to claim 4, characterized in that: The metal electrode layer is located between the external electric field shielding layer and the second polysilicon layer; The first electrode is electrically connected to the first polysilicon layer through a plurality of first connection holes; The second electrode is electrically connected to the second polysilicon layer through a plurality of second connection holes.

6. The layout structure of the PIP capacitor according to claim 4, characterized in that: In the case where the second polysilicon layer includes a plurality of second polysilicon sublayers extending along the first direction and arranged at intervals along the second direction; The first electrode comprises a plurality of first electrode strips extending along the first direction and arranged at intervals along the second direction; The second electrode comprises a plurality of second electrode strips extending along the first direction and arranged at intervals along the second direction; The first electrode strip and the second electrode strip are arranged in sequence at intervals, and a vertical projection of the first electrode strip on the first polysilicon layer and a vertical projection of the second polysilicon sublayer on the first polysilicon layer at least partially do not overlap; a vertical projection of the second electrode strip on the first polysilicon layer and a vertical projection of the second polysilicon sublayer on the first polysilicon layer at least partially overlap.

7. The layout structure of the PIP capacitor according to claim 1, characterized in that: The area of ​​the first polysilicon layer is greater than the area of ​​the second polysilicon layer, and the area of ​​the external electric field shielding layer is greater than the area of ​​the second polysilicon layer.

8. A PIP capacitor, characterized in that: Preparation of the layout structure of the PIP capacitor based on any one of claims 1-7.

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