Semiconductor Structure and Method for Manufacturing the Same

Abstract

The present application relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base region, a cathode region, a cathode electrode and at least two gate electrodes; the cathode region is located at the central position of one side of the base region; at least part of the cathode region is embedded in the base region; the cathode electrode is located on the side of the cathode region away from the base region and is electrically connected to the cathode region; the cathode electrode covers at least part of the surface of the cathode region; wherein the surface of the cathode region not covered by the cathode electrode is flush with the surface of the base region close to the cathode region; at least two gate electrodes are located on the side of the base region close to the cathode region and are distributed on both sides of the cathode region in a first direction; the gate electrode is electrically connected to the base region. The present application can effectively reduce the on-state voltage drop of the chip while ensuring the chip's shutdown capability and blocking voltage, thereby facilitating the improvement of the performance of semiconductor devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Integrated Gate Commutated Thyristor (IGCT) is a new type of semiconductor switching device, which integrates the gate drive circuit and the gate commutated thyristor (GCT) on the same chip. Among them, the gate commutated thyristor is a new type of power semiconductor device based on the gate turn-off thyristor (GTO) structure. It not only has the same high blocking capability and low on-state voltage drop as GTO, but also has the same switching performance as the insulated gate bipolar transistor (IGBT). It is an ideal megawatt-level, medium and high voltage switching device, and is widely used in high voltage and high power inverters and converters.

[0003] In the related art, in order to reduce the on-state voltage drop of the GCT chip, measures such as reducing the thickness of the voltage-resistant layer, increasing the minority carrier lifetime, or increasing the cathode region doping concentration are usually adopted. However, these commonly adopted measures to reduce the on-state voltage drop are likely to have adverse effects on the chip's blocking voltage drop, turn-off loss, and turn-off capability, thereby limiting the optimization space for the GCT chip performance. Summary of the invention

[0004] Based on this, the embodiment of the present application provides a GCT chip structure and a preparation method thereof, which can effectively reduce the on-state voltage drop of the chip while ensuring the shutdown capability and blocking voltage of the chip, thereby facilitating improving the performance of the semiconductor device.

[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes a base region, a cathode region, a cathode electrode and at least two gate electrodes; the cathode region is located at the central position of one side of the base region; at least part of the cathode region is embedded in the base region; the cathode electrode is located at the side of the cathode region away from the base region and is electrically connected to the cathode region; the cathode electrode covers at least part of the surface of the cathode region; wherein the surface of the cathode region not covered by the cathode electrode is flush with the surface of the base region close to the cathode region; at least two gate electrodes are located at the side of the base region close to the cathode region and are distributed on both sides of the cathode region in a first direction; the gate electrode is electrically connected to the base region.

[0006] In some embodiments, the cathode region includes a cathode mesa protruding outside the base region; a stepped structure is formed between the cathode mesa and the portion of the cathode region embedded in the base region; wherein, the cathode electrode covers the surface of the cathode mesa facing away from the base region.

[0007] In some embodiments, the value range of the size of the cathode mesa in the first direction includes 5μm to 15μm; wherein, the first direction intersects with the second direction.

[0008] In some embodiments, the cathode region is embedded in the base region; the surface of the cathode region facing away from the base region is flush with the surface of the base region close to the cathode region.

[0009] In some embodiments, the ratio range between the size of the base region in the second direction and the size of the cathode electrode in the second direction includes 2.2:1 to 3:1.

[0010] In some embodiments, the value range of the size of the base region in the second direction includes 100μm to 300μm.

[0011] In some embodiments, the semiconductor structure further includes an anode region and an anode electrode; the anode region is located on the side of the base region facing away from the cathode region; the anode electrode is located on the side of the anode region facing away from the base region and is electrically connected to the anode region.

[0012] In some embodiments, the base region includes a first base region, a second base region, and a third base region; the first base region is located on the side of the cathode region facing away from the cathode electrode; wherein, at least a part of the cathode region is embedded in the first base region; the second base region is located on the side of the first base region facing away from the cathode region; the third base region is located on the side of the second base region facing away from the first base region; wherein, the first base region and the second base region are of the first conduction type, and the third base region is of the second conduction type.

[0013] In some embodiments, the value range of the sum of the sizes of the first base region and the second base region in the first direction includes 50μm to 70μm.

[0014] On the other hand, the present disclosure also provides a manufacturing method of a semiconductor structure according to some embodiments; the manufacturing method of the semiconductor structure includes: providing a substrate; forming a base region in the substrate; forming a cathode region at the central position on the side away from the base region; at least a part of the cathode region is embedded in the base region; forming a cathode electrode on the side of the cathode region facing away from the base region; the cathode electrode covers at least a part of the surface of the cathode region and is electrically connected to the cathode region; wherein, the surface of the cathode region not covered by the cathode electrode is flush with the surface of the base region close to the cathode region; forming at least two gate electrodes on the surface of the base region close to the cathode region, the gate electrodes are distributed on both sides of the cathode region in the second direction; the gate electrodes are electrically connected to the base region.

[0015] In some embodiments, a cathode region is formed at a central position on one side of the base region, including: forming a first initial cathode region embedded in the base region on one side of the base region; etching the first initial cathode region to form a cathode mesa, so that the etched and remaining portion of the first initial cathode region forms a second initial cathode region; wherein, the cathode mesa protrudes outside the base region, and a stepped structure is formed between the cathode mesa and the portion of the cathode region embedded in the base region; doping is performed in the second initial cathode region to form the cathode region.

[0016] In some embodiments, a cathode region is formed at a central position on one side of the base region, including: forming a nitride layer on one side of the base region; etching the nitride layer to form a doping window; performing doping in the doping window to form the cathode region; wherein, the cathode region is embedded in the base region; the surface of the cathode region facing away from the base region is flush with the surface of the base region close to the cathode region.

[0017] In some embodiments, while forming the base region in the substrate, the method further includes: forming an anode region on the side of the base region facing away from the cathode region; forming the base region in the substrate, including: forming a second base region in the substrate; forming a first base region on the surface of the substrate close to the second base region; wherein, the anode region is formed synchronously with the first base region; the remaining portion of the substrate where the second base region, the first base region, and the anode region are not formed is the third base region.

[0018] The embodiments of the present application may / at least have the following advantages:

[0019] In the embodiments of the present application, by making the surface of the cathode region not covered by the cathode electrode flush with the surface of the base region close to the cathode region, the conventional inclined surface structure of the cathode region in the related art is replaced, which is beneficial to realizing the small-size processing of the cathode region, thereby realizing the reduction of the lateral dimension (i.e., the dimension in the second direction) of the cathode electrode; and, since the current will commutate from the cathode electrode to the gate electrode when the chip is turned off, the lateral dimension of the gate electrode needs to be slightly larger than that of the cathode electrode. Therefore, on the premise of reducing the lateral dimension of the cathode electrode, the lateral dimension of the gate electrode can also be reduced accordingly. In this way, by reducing the lateral dimensions of both the cathode electrode and the gate electrode, the lateral distance between the gate electrode and the cathode electrode is reduced, which is beneficial to realizing the reduction of the lateral dimension (i.e., the dimension in the second direction) of the semiconductor structure unit, so as to be able to reduce the overall thickness of the chip on the basis of ensuring the turn-off ability and blocking voltage of the chip, effectively reducing the on-state voltage drop of the chip, and being beneficial to improving the performance of the semiconductor device.

[0020] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the specification, drawings, and claims. Description of the Drawings

[0021] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 It is a schematic structural diagram of a semiconductor structure provided in some embodiments;

[0023] Figure 2 It is a schematic structural diagram of a semiconductor structure provided in the related art;

[0024] Figure 3 It is a schematic structural diagram of a semiconductor structure provided in some other embodiments;

[0025] Figure 4 It is a schematic flow diagram of a manufacturing method of a semiconductor structure provided in some embodiments;

[0026] Figure 5 It is a schematic flow diagram of a step S200 provided in some embodiments;

[0027] Figure 6 It is a schematic flow diagram of a step S300 provided in some embodiments;

[0028] Figure 7 It is a schematic flow diagram of a step S300 provided in some other embodiments;

[0029] Figure 8 It is a schematic flow diagram of another manufacturing method of a semiconductor structure provided in some embodiments.

[0030] Explanation of reference numerals:

[0031] 1 - base region, 11 - first base region, 12 - second base region, 13 - third base region, 2 - cathode region, 2T - cathode electrode, M - cathode mesa, 3 - anode region, 3T - anode electrode, 4T - gate electrode, J1 - first PN junction, J2 - second PN junction, J3 - third PN junction. Detailed implementation manners

[0032] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing particular embodiments only and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, under the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be denoted as the second element, component, region, layer, or portion.

[0035] As used herein, the singular forms "a," "an," and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0036] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. It is to be expected that variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances. Embodiments of the present application should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present application.

[0037] Integrated Gate Commutated Thyristor (IGCT) is a new type of semiconductor switching device that integrates the gate drive circuit and the gate commutated thyristor (GCT) on the same chip. In the related technology, the measures that can be taken to reduce the conduction voltage drop of the GCT chip mainly include the following three aspects: first, by reducing the thickness of the voltage-resistant layer to reduce the body voltage drop of the chip; second, by increasing the minority carrier lifetime to increase the bipolar diffusion length of the carrier, thereby reducing the body voltage drop of the chip; third, by increasing the doping concentration of the cathode region and using the law that the change of the body voltage drop is faster than the change of the junction voltage drop, so that the junction voltage drop increases logarithmically and the body voltage drop decreases according to the inverse of the square root, thereby achieving a reduction in the conduction voltage drop. However, these commonly used measures to reduce the on-state voltage drop have the following adverse effects on the performance of the GCT chip: the reduction in the thickness of the voltage-resistant layer can easily affect the blocking voltage of the chip; the increase in the minority carrier lifetime can easily affect the turn-off loss of the chip; the increase in the cathode region doping concentration can easily affect the turn-off capability and turn-off loss of the chip.

[0038] Therefore, it is necessary to propose a low-loss semiconductor structure that can effectively reduce the on-state voltage drop of the chip while ensuring the blocking voltage and current shutoff capabilities of the chip.

[0039] In order to achieve the above objectives, on the one hand, some embodiments of the present application provide a semiconductor structure.

[0040] By way of example, the semiconductor structure includes, but is not limited to, a reverse resistance GCT chip.

[0041] In some embodiments, see Figure 1 , the semiconductor structure includes a base region 1, a cathode region 2, a cathode electrode 2T and at least two gate electrodes 4T. The cathode region 2 is located at the central position of one side of the base region 1; at least part of the cathode region 2 is embedded in the base region 1. The cathode electrode 2T is located on the side of the cathode region 2 away from the base region 1 and is electrically connected to the cathode region 2; the cathode electrode 2T covers at least part of the surface of the cathode region 2; wherein the surface of the cathode region 2 not covered by the cathode electrode 2T is flush with the surface of the base region 1 close to the cathode region 2. At least two gate electrodes 4T are located on the side of the base region 1 close to the cathode region 2, and are distributed on both sides of the cathode region 2 in the second direction (for example, the X direction); the gate electrode 4T is electrically connected to the base region 1.

[0042] In some examples, a size of the gate electrode 4T in the second direction (eg, the X direction) is greater than a size of the cathode electrode 2T in the second direction (eg, the X direction).

[0043] Exemplarily, the second direction (e.g., the X direction) can be a horizontal direction.

[0044] Exemplarily, the material of the cathode electrode 2T includes but is not limited to conductive metals.

[0045] In some possible embodiments, please continue to refer to Figure 1 , the cathode region 2 includes a cathode mesa M protruding outside the base region 1; a stepped structure is formed between the cathode mesa M and the part of the cathode region 2 embedded in the base region 1; wherein, the cathode electrode 2T covers the surface of the cathode mesa M facing away from the base region 1.

[0046] It can be understood that both side walls of the cathode mesa M in the second direction (e.g., the X direction) are perpendicular to the surface of the base region 1 close to the cathode region 2.

[0047] In the embodiments of the present disclosure, the cathode region 2 can be formed based on a dry etching process.

[0048] Here, it should be noted that, please refer to Figure 2 , the conventional inclined surface structure S of the cathode region 2 in the related art is usually formed based on a wet etching process. Due to the isotropic property of the wet etching process, it is difficult to achieve precise control of the size of the cathode region 2. The cathode mesa M in the embodiments of the present disclosure can be formed based on a dry etching process, so that precise control of the lateral dimension W n of the cathode region 2 can be achieved through the definition of the mask plate, which is beneficial to the reduction of the lateral dimension W pitch of the semiconductor structure unit.

[0049] In some embodiments, the value range of the size of the cathode mesa M in the first direction (e.g., the Y direction) includes 5μm to 15μm. Wherein, the first direction (e.g., the Y direction) intersects with the second direction (e.g., the X direction).

[0050] Exemplarily, the size of the cathode mesa M in the first direction (e.g., the Y direction) is, for example, 5μm, 7μm, 10μm, 12μm, or 15μm, etc.

[0051] Exemplarily, the first direction (e.g., the Y direction) can be a vertical direction.

[0052] In some other possible embodiments, please refer to Figure 3 , the cathode region 2 is embedded in the base region 1; the surface of the cathode region 2 facing away from the base region 1 is flush with the surface of the base region 1 close to the cathode region 2. That is, the cathode region 2 is a planar structure embedded in the base region 1.

[0053] Here, it should be noted that the planar cathode region 2 can be formed based on a lithography process, so that precise control of the lateral dimension W nPrecise control of the semiconductor structure unit is beneficial to achieve the lateral size W pitch of reduction.

[0054] In some embodiments, the size W of the base region 1 in the second direction (eg, the X direction) is pitch The dimension W of the cathode electrode 2T in the second direction (eg, the X direction) is n2 The ratio ranges from 2.2:1 to 3:1.

[0055] For example, W pitch :W n2 It can be 2.2:1, 2.5:1, 2.7:1 or 3:1, etc.

[0056] In some embodiments, the size W of the base region 1 in the second direction (eg, the X direction) is pitch The value range includes 100μm ~300μm.

[0057] For example, the size W of the base region 1 in the second direction (eg, the X direction) is pitch For example, it may be 100 μm, 150 μm, 200 μm, 250 μm or 300 μm.

[0058] It should be noted that the size W of the base region 1 in the second direction (eg, the X direction) is pitch That is, the lateral dimension of the semiconductor structure.

[0059] In some embodiments, see Figure 1 or Figure 3 The semiconductor structure further includes an anode region 3 and an anode electrode 3T; the anode region 3 is located on a side of the base region 1 away from the cathode region 2; the anode electrode 3T is located on a side of the anode region 3 away from the base region 1 and is electrically connected to the anode region 3.

[0060] In some examples, the size of the anode region 3 in the second direction (eg, the X direction) is equal to the size of the base region 1 in the second direction (eg, the X direction).

[0061] In some examples, the size of the anode electrode 3T in the second direction (eg, the X direction) is equal to the size of the anode region 3 in the second direction (eg, the X direction).

[0062] Illustratively, the material of the anode electrode 3T includes, but is not limited to, conductive metal.

[0063] In some embodiments, see Figure 1 or Figure 3, the base region 1 includes a first base region 11, a second base region 12, and a third base region 13; the first base region 11 is located on a side of the cathode region 2 away from the cathode electrode 2T; wherein, at least a part of the cathode region 2 is embedded in the first base region 11; the second base region 12 is located on a side of the first base region 11 away from the cathode region 2; the third base region 13 is located on a side of the second base region 12 away from the first base region 11; wherein, the first base region 11 and the second base region 12 are of a first conductivity type, and the third base region 13 is of a second conductivity type.

[0064] Exemplarily, in the embodiments of the present disclosure, the first conductivity type is, for example, a P type; the second conductivity type is, for example, an N type.

[0065] It should be noted that the doping concentration of the first base region 11 is greater than the doping concentration of the second base region 12.

[0066] Exemplarily, the value range of the doping concentration of the first base region 11 includes 1E16 cm -3 ~1E20 cm -3 ; the doping concentration of the first base region 11 can be, for example, 1E16 cm -3 、1E17 cm -3 、1E18 cm -3 、1E19 cm -3 or 1E20 cm -3 etc.

[0067] In some embodiments, the conductivity type of the cathode region 2 is the second conductivity type; the conductivity type of the anode region 3 is the first conductivity type. Wherein, the doping concentration of the anode region 3 is greater than the doping concentration of the second base region 12.

[0068] Exemplarily, the value range of the doping concentration of the anode region 3 includes 1E16 cm -3 ~1E20 cm -3 ; the doping concentration of the anode region 3 can be, for example, 1E16 cm -3 、1E17 cm -3 、1E18 cm -3 、1E19 cm -3 or 1E20 cm -3 etc.

[0069] Exemplarily, the value range of the doping concentration of the cathode region 2 includes 1E18 cm -3 ~1E21 cm -3 ; the doping concentration of the anode region 3 can be, for example, 1E18 cm -3 、1E19 cm -3 、1E20 cm -3 or 1E21 cm -3 etc.

[0070] It can be understood, please refer toFigure 1 or Figure 3 The contact interface between the cathode region 2 and the first base region 11 is the third PN junction J3; the contact interface between the second base region 12 and the third base region 13 is the second PN junction J2; the contact interface between the second base region 12 and the anode region 3 is the first PN junction J1.

[0071] Exemplarily, in some embodiments of the present disclosure, in the stepped cathode region 2 as shown in Figure 1 the value range of the junction depth of the third PN junction J3 includes 10 μm to 30 μm. Among them, the junction depth of the third PN junction J3 can be, for example, 10 μm, 15 μm, 20 μm, 25 μm or 30 μm, etc.

[0072] Exemplarily, in some other embodiments of the present disclosure, in the planar cathode region 2 as shown in Figure 3 the value range of the junction depth of the third PN junction J3 includes 5 μm to 10 μm. Among them, the junction depth of the third PN junction J3 can be, for example, 5 μm, 8 μm or 10 μm, etc.

[0073] Exemplarily, the value range of the junction depth of the second PN junction J2 (that is, the sum of the dimensions of the first base region 11 and the second base region 12 in the first direction (for example, the Y direction)) includes 50 μm to 70 μm; the junction depth of the second PN junction J2 can be, for example, 50 μm, 55 μm, 60 μm, 65 μm or 70 μm, etc.

[0074] Exemplarily, the value range of the junction depth of the first PN junction J1 includes 15 μm to 50 μm; the junction depth of the first PN junction J1 can be, for example, 15 μm, 20 μm, 30 μm, 40 μm or 50 μm, etc.

[0075] It can be understood that the voltage withstand layer of the semiconductor structure includes: the base region 1 and the anode region 3.

[0076] It should be noted that, please refer to Figure 1 or Figure 3 in the embodiments of the present disclosure, by making the surface of the cathode region 2 not covered by the cathode electrode 2T flush with the surface of the base region 1 close to the cathode region 2, it replaces the conventional inclined surface structure of the cathode region 2 in the related art (as shown in Figure 2 ) to facilitate the precise control of the size of the cathode region 2 through a dry etching process, so as to realize the reduction of the lateral size of the cathode region (that is, W n ), which is beneficial to the reduction of the lateral size of the semiconductor structure unit (that is, W pitch ), so as to be able to realize the reduction of the longitudinal dimensions of the first base region 11 and the second base region 12 (that is, H P ) on the basis of ensuring the turn-off ability and blocking voltage of the chip, so as to realize the reduction of the longitudinal dimension of the voltage withstand layer in the semiconductor structure (that is, HT ), so as to effectively reduce the on-state voltage drop of the chip, which is beneficial to improving the performance of semiconductor devices.

[0077] On the other hand, according to some embodiments, the present application also provides a manufacturing method of a semiconductor structure, which can be used to prepare the semiconductor structures in the above-mentioned some embodiments. The technical advantages of the aforementioned semiconductor structures are also possessed by this manufacturing method. It should be noted that for the same or corresponding parts as those in the above embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, and details will not be elaborated below.

[0078] In some embodiments, please refer to Figure 4 , the manufacturing method of the semiconductor structure includes the following steps S100 to S500.

[0079] S100, provide a substrate.

[0080] In some examples, the conductive type of the substrate is the second conductive type.

[0081] Exemplarily, the value range of the doping concentration of the substrate includes 5E11 cm -3 ~1E14 cm -3 ; the doping concentration of the substrate can be, for example, 5E11 cm -3 , 5E12 cm -3 , 5E13 cm -3 or 1E14 cm -3 and so on.

[0082] Exemplarily, the value range of the size of the substrate in the first direction (for example, the Y direction) includes 400 μm to 1800 μm; the size of the substrate in the first direction (for example, the Y direction) can be, for example, 400 μm, 500 μm, 1000 μm, 1500 μm or 1800 μm and so on.

[0083] S200, form a base region in the substrate.

[0084] Specifically, in some embodiments, while performing step S200, this method further includes the following step S201.

[0085] S201, form an anode region on a side of the base region facing away from the cathode region.

[0086] Exemplarily, the forming process of the anode region includes, but is not limited to, ion implantation process and diffusion process.

[0087] Correspondingly, please refer to Figure 5 , step S200 includes the following steps S210 to S220.

[0088] S210, form a second base region in the substrate.

[0089] Exemplarily, the formation process of the second base region includes, but is not limited to, ion implantation process, diffusion process, and doping process.

[0090] Exemplarily, the doping elements of the second base region include, but are not limited to, aluminum (Al) or gallium (Ga).

[0091] S220, form a first base region on the surface of the substrate close to the second base region; wherein, the anode region is formed synchronously with the first base region; the remaining part of the substrate without the second base region, the first base region, and the anode region is the third base region.

[0092] Exemplarily, the formation process of the first base region includes, but is not limited to, ion implantation process and diffusion process.

[0093] It should be noted that in the embodiments of the present disclosure, the synchronous formation of the anode region and the first base region can be achieved by a double-sided doping process.

[0094] Exemplarily, the doping elements of both the first base region and the anode region include, but are not limited to, boron (B).

[0095] S300, form a cathode region at the central position on the side away from the base region; at least part of the cathode region is embedded in the base region.

[0096] Specifically, in some possible implementation manners, please refer to Figure 6 , step S300 may include the following steps S311 to S313.

[0097] It should be noted that the following steps S311 to S313 are used to prepare the cathode region with a step structure as shown in Figure 1 .

[0098] S311, form a first initial cathode region embedded in the base region on one side of the base region.

[0099] Exemplarily, the first initial cathode region can be formed based on a pre-deposition process and / or a pre-diffusion process.

[0100] Exemplarily, the value range of the diffusion junction depth of the first initial cathode region includes 3μm to 5μm. Among them, the diffusion junction depth of the first initial cathode region can be, for example, 3μm, 4μm, or 5μm, etc.

[0101] Exemplarily, the doping elements of the first initial cathode region all include, but are not limited to, boron (B).

[0102] S312, etch the first initial cathode region to form a cathode mesa, so that the etched remaining part of the first initial cathode region forms a second initial cathode region; wherein, the cathode mesa protrudes out of the base region, and the cathode mesa and the part of the cathode region embedded in the base region form a step structure.

[0103] Exemplarily, the etching process of the first initial cathode region includes, but is not limited to, a dry etching process.

[0104] In some examples, step S312 includes: forming a mask layer on a side of the first initial cathode region facing away from the base region; etching the mask layer to form a photolithography pattern; etching the first initial cathode region based on the photolithography pattern to form a second initial cathode region.

[0105] S313, doping is performed within the second initial cathode region to form a cathode region.

[0106] Exemplarily, the value range of the doping concentration of the cathode region includes 1E18 cm -3 ~1E21 cm -3 ; the doping concentration of the cathode region can be, for example, 1E18 cm -3 、1E19 cm -3 、1E20 cm -3 or 1E21 cm -3 etc.

[0107] Specifically, in some other possible implementation manners, please refer to Figure 7 , step S300 may further include the following steps S321~S323.

[0108] It should be noted that the following steps S321~S323 are used to prepare the cathode region with a planar structure as shown in Figure 3 .

[0109] S321, forming a nitride layer on one side of the base region.

[0110] Exemplarily, the formation process of the nitride layer includes, but is not limited to, a chemical vapor deposition process.

[0111] Exemplarily, the nitride layer includes, but is not limited to, a silicon nitride film.

[0112] S322, etching the nitride layer to form a doping window.

[0113] Exemplarily, the etching process of the nitride layer includes, but is not limited to, a photolithography process.

[0114] S323, doping is performed within the doping window to form a cathode region; wherein, the cathode region is embedded in the base region; the surface of the cathode region facing away from the base region is flush with the surface of the base region close to the cathode region.

[0115] In some examples, step S323 includes the following steps S3231~S3232.

[0116] S3231, locally pre-diffusing within the doping window to form an initial cathode region.

[0117] Here, the junction depth of the initial cathode region ranges from 2 μm to 3 μm; for example, the junction depth of the initial cathode region can be 2 μm, 1.5 μm, 3 μm, etc.

[0118] S3232, perform secondary diffusion on the initial cathode region to form the cathode region.

[0119] Exemplarily, the process of secondary diffusion of the cathode region includes but is not limited to the high-temperature push-junction process.

[0120] Here, the junction depth of the cathode region ranges from 5 μm to 10 μm; for example, the junction depth of the cathode region can be 5 μm, 6 μm, 8 μm, 10 μm, etc.

[0121] It should be added that before steps S400 and S500, the manufacturing method of the semiconductor structure further includes the following steps S401 - S402.

[0122] S401, form an oxide layer on the side of the cathode region facing away from the base region.

[0123] Exemplarily, the process of forming the oxide layer includes but is not limited to the chemical vapor deposition process.

[0124] S402, etch the oxide layer to form a cathode electrode contact window and a gate electrode contact window.

[0125] Exemplarily, the etching process of the oxide layer includes but is not limited to the photolithography process.

[0126] Correspondingly, the cathode electrode in the following steps is formed within the cathode electrode contact window; the gate electrode is formed within the gate electrode contact window.

[0127] S400, form a cathode electrode on the side of the cathode region facing away from the base region; the cathode electrode covers at least a part of the surface of the cathode region and is electrically connected to the cathode region; wherein, the surface of the cathode region not covered by the cathode electrode is flush with the surface of the base region close to the cathode region.

[0128] S500, form at least two gate electrodes on the surface of the base region close to the cathode region, and the gate electrodes are distributed on both sides of the cathode region in the second direction (for example, the X direction); the gate electrodes are electrically connected to the base region.

[0129] It should be noted that the cathode electrode and the gate electrode can be formed synchronously by the same process.

[0130] Exemplarily, the formation methods of the cathode electrode and / or the gate electrode both include but are not limited to using the evaporation process or the sputtering process to deposit a metal to form a material layer and performing photolithography on the material layer.

[0131] Exemplarily, the materials of the cathode electrode and / or the gate electrode include but are not limited to conductive metals, for example, it can be aluminum (Al) and its alloys.

[0132] In some embodiments, referring to Figure 8 , the method for preparing the semiconductor structure further includes the following steps S600 to S800.

[0133] S600, forming an anode electrode on the side of the anode region facing away from the base region; the anode electrode covers the surface of the anode region facing away from the base region and is electrically connected to the anode region.

[0134] Exemplarily, the method for forming the anode electrode includes but is not limited to using an evaporation process or a sputtering process to deposit a metal to form a material layer, and performing photolithography on the material layer to form it.

[0135] Exemplarily, the materials of the anode electrode include but are not limited to conductive metals, for example, it can be aluminum (Al) and its alloys.

[0136] S700, forming a passivation layer between the cathode electrode and the gate electrode.

[0137] It should be noted that the passivation layer is used to isolate the cathode electrode and the gate electrode from each other.

[0138] Exemplarily, the materials of the passivation layer include but are not limited to insulating materials, for example, it can be at least one of polyimide (abbreviated as PI), amorphous hydrogenated carbon (a-C:H, also known as diamond-like carbon DLC), inorganic-organic composite materials, parylene, or composite materials composed of phenolic resin containing polymer particles, etc.

[0139] S800, forming a terminal profile and a passivation protection structure.

[0140] Exemplarily, the forming process of the terminal profile includes chamfering, cleaning, passivation, and rounding, etc.

[0141] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0142] The above-described embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application.

Claims

1. A semiconductor structure, characterized in that: include: base area; A cathode region is located at a central position on one side of the base region; at least a portion of the cathode region is embedded in the base region; the cathode region includes a cathode table protruding out of the base region; the cathode table and a portion of the cathode region embedded in the base region form a step structure; a cathode electrode, located at a side of the cathode region away from the base region and electrically connected to the cathode region; the cathode electrode covers a surface of the cathode table away from the base region; wherein a surface of the cathode region not covered by the cathode electrode is flush with a surface of the base region close to the cathode region; At least two gate electrodes are located on a side of the base region close to the cathode region and distributed on both sides of the cathode region in a second direction; the gate electrodes are electrically connected to the base region; The side surface of the cathode electrode which is perpendicular to the base region and faces the adjacent gate electrode is flush with the side surface of the cathode mesa which is perpendicular to the base region and faces the adjacent gate electrode.

2. The semiconductor structure according to claim 1, characterized in that: The size of the cathode mesa in the first direction ranges from 5 μm to 15 μm; wherein the first direction intersects with the second direction.

3. The semiconductor structure according to any one of claims 1 to 2, characterized in that: A ratio between a size of the base region in the second direction and a size of the cathode electrode in the second direction ranges from 2.2:1 to 3:

1.

4. The semiconductor structure according to claim 1, characterized in that: The size of the base region in the second direction ranges from 100 μm to 300 μm.

5. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: an anode region, located at a side of the base region away from the cathode region; The anode electrode is located at a side of the anode region away from the base region and is electrically connected to the anode region.

6. The semiconductor structure according to claim 1, characterized in that The base region comprises: A first base region, located at a side of the cathode region away from the cathode electrode; wherein at least a portion of the cathode region is embedded in the first base region; a second base region, located at a side of the first base region away from the cathode region; a third base region, located at a side of the second base region away from the first base region; The first base region and the second base region are of the first conductivity type, and the third base region is of the second conductivity type.

7. The semiconductor structure according to claim 6, characterized in that: A value range of the sum of the sizes of the first base region and the second base region in the first direction includes 50 μm to 70 μm.

8. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a base region in the substrate; forming a cathode region at a central position of one side of the base region; At least part of the cathode region is embedded in the base region; the cathode region includes a cathode table protruding out of the base region; the cathode table and the part of the cathode region embedded in the base region form a step structure; forming a cathode electrode on a side of the cathode region away from the base region; The cathode electrode covers the surface of the cathode table away from the base region and is electrically connected to the cathode region; wherein the surface of the cathode region not covered by the cathode electrode is flush with the surface of the base region close to the cathode region; At least two gate electrodes are formed on a side surface of the base region close to the cathode region, and the gate electrodes are distributed on both sides of the cathode region in a second direction; the gate electrode is electrically connected to the base region; wherein the side surface of the cathode electrode perpendicular to the base region and facing the adjacent gate electrode is flush with the side surface of the cathode table perpendicular to the base region and facing the adjacent gate electrode.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The cathode region is formed at the central position of one side of the base region, comprising: forming a first initial cathode region embedded in the base region on one side of the base region; Etching the first initial cathode region to form the cathode mesa, so that the etched remaining portion of the first initial cathode region forms a second initial cathode region; Doping is performed in the second initial cathode region to form the cathode region.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: While forming the base region in the substrate, the method further includes: forming an anode region located on a side of the base region away from the cathode region; forming the base region in the substrate includes: forming a second base region in the substrate; A first base region is formed on the surface of the substrate close to the second base region; wherein the anode region is formed synchronously with the first base region; and the remaining portion of the substrate where the second base region, the first base region and the anode region are not formed is a third base region.

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