Method, electronic device and storage medium for designing simulation logic system

Abstract

The present application provides a method for simulating a logic system design, comprising: obtaining a description of the logic system design, the logic system design comprising a plurality of modules, the plurality of modules comprising a first module, a second module and a third module; determining a plurality of connections between the plurality of modules according to the description of the logic system design, wherein the plurality of connections comprise a first connection between the first module and the second module and a second connection between the second module and the third module; determining at least one target module according to the plurality of connections, wherein the at least one target module comprises the second module; generating a virtual module corresponding to the at least one target module according to a connection relationship of the at least one target module; and generating a gate-level netlist of the logic system design based on the virtual module.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a method, electronic device and storage medium for emulating logic system design. Background Art

[0002] A hardware simulation tool (e.g., a prototype verification board or a hardware emulator) can prototype and debug a logic system design including one or more modules. The logic system design can be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a specific application. Therefore, the logic system design tested in the simulation tool can also be called a Design Under Test (DUT). The simulation tool can simulate the design under test through one or more configurable components (e.g., a Field Programmable Gate Array (FPGA)), including executing various operations of the design under test, thereby testing and verifying the functions of each module of the design under test before manufacturing. By connecting a variety of peripheral daughter cards to the simulation tool, the effect of the design under test and various peripherals running as a complete system can also be tested.

[0003] There are many software supporting hardware simulation tools, such as compilers, synthesizers, debuggers, etc.

[0004] The compiler is used to compile the source code of the logic system design, the synthesizer is used to synthesize the logic system design into a netlist and burn it into the FPGA, and the debugger is used to implement some simple debugging functions. It can be understood that the above software runs on the host connected to the hardware simulation tool.

[0005] Usually, chip design involves multiple modules. When simulating chip design, multiple modules serially will cause the simulation time to be too long. In traditional technology, most designers choose partition technology to divide the logic system design and then process it in parallel to improve performance. However, if the partitioning is not completed correctly and adapted, the simulation performance cannot be improved. Therefore, partition technology has high requirements for segmentation and requires tedious preliminary processing to find a suitable partitioning scheme.

[0006] Based on this, the applicant of the present invention proposes a method for designing a logic system based on module parallel simulation, which does not require segmentation of the logic system design and can efficiently perform parallel processing on the logic system design. Summary of the invention

[0007] The first aspect of the present application provides a method for simulating a logic system design, the method comprising: obtaining a description of the logic system design, the logic system design comprising a plurality of modules, the plurality of modules comprising a first module, a second module and a third module; determining a plurality of connections between the plurality of modules according to the description of the logic system design, wherein the plurality of connections comprise a first connection between the first module and the second module and a second connection between the second module and the third module; determining at least one target module according to the plurality of connections, wherein the at least one target module comprises the second module; generating a virtual module corresponding to the at least one target module according to the connection relationship of the at least one target module; and generating a gate-level netlist of the logic system design based on the virtual module.

[0008] A second aspect of the present application provides an electronic device, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device executes the method described in the first aspect.

[0009] A third aspect of the present application provides a non-transitory computer-readable storage medium, which stores a set of instructions for a computer, and when the set of instructions is executed, causes the computer to perform the method as described in the first aspect.

[0010] The present application provides a method for simulating logic system design, which does not require partitioning of the logic system design. The present application completes parallel processing of the logic system design by dividing the modules, which can greatly improve the performance of the simulating logic system design. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A schematic diagram of the structure of an exemplary host according to an embodiment of the present application is shown.

[0013] Figure 2 A schematic diagram of a simulation system according to an embodiment of the present application is shown.

[0014] Figure 3 A schematic diagram showing the structure of an exemplary logic system design according to an embodiment of the present application is shown.

[0015] Figure 4A schematic diagram of an exemplary method for designing a simulation logic system according to an embodiment of the present application is shown.

[0016] Figure 5 A flow chart of a method for simulating logic system design according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0018] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0019] Synthesis is a process of converting a high-level language description of a logic system design (for example, Verilog) into a gate-level netlist. Synthesis is a necessary step to emulate a logic design using a hardware simulation tool. Usually, a chip design involves multiple modules. When synthesizing a chip design, multi-module serial synthesis will result in a long synthesis time. The prior art uses partitioning technology to partition the logic system design and then synthesize it in parallel, but the partitioning technology has high requirements for partitioning and requires cumbersome preliminary processing. The applicant of the present invention proposes a method for simulating a logic system design, which does not require the logic system design to be partitioned, and can efficiently synthesize the logic system design in parallel. At the same time, it proposes a solution to the module parallel problem caused by cross-module references.

[0020] Figure 1 FIG. 1 shows a schematic diagram of the structure of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other through the bus 110 in communication with each other inside the electronic device.

[0021] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0022] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulation test design may be a computer program stored in the memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method for locating errors of the present application) and data to be processed (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0023] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0024] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0025] The bus 110 may be configured to transmit information between various components of the host 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0026] It should be noted that, although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the electronic device architecture may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above electronic device architecture may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0027] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of the present application is shown.

[0028] like Figure 2 As shown, the simulation system 200 may include a simulation tool 202 and a host 100 connected to the simulation tool 202 .

[0029] The simulation tool 202 is a hardware system for simulating a design under test (DUT). The simulation tool 202 may be a prototype verification board or a hardware emulator. A design under test may include multiple modules. The design under test may be a combinational logic circuit, a sequential logic circuit, or a combination of the two. The simulation tool 202 may include one or more configurable circuits (e.g., FPGA) for simulating the design under test.

[0030] The simulation tool 202 may include an interface unit 2022 for communicatively coupling with the host 100 to perform communication between the host 100 and the simulation tool 202. In some embodiments, the interface unit 2022 may include one or more interfaces with electrical connection capability. For example, the interface unit 2022 may include an RS232 interface, a USB interface, a LAN port, an optical fiber interface, an IEEE1394 (FireWire interface), etc. In some embodiments, the interface unit 2022 may be a wireless network interface. For example, the interface unit 2022 may be a WIFI interface, a Bluetooth interface, etc.

[0031] The host 100 may transmit the compiled DUT, debugging instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 may also transmit simulation data, etc. to the host 100 via the interface unit 2022.

[0032] The simulation tool 202 may also include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during the simulation process. In some embodiments, the signal values ​​generated by the design under test during the simulation process may be directly read by the host 100. It is understood that the memory 2024 may also be independent of the simulation tool 202, for example, using an external memory.

[0033] The simulation tool 202 may also include an FPGA 2026 for implementing the logic system design in hardware on the FPGA. It is understandable that the simulation tool 202 may include multiple FPGAs, which are only examples in the figure.

[0034] In addition to being connected to the host 100 , the emulation tool 202 may also be connected to one or more daughter cards 204 via an interface unit 2022 .

[0035] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for prototype verification. Prototype verification refers to a verification method that restores the actual use scenario of the chip as much as possible before the chip is taped out to verify whether the chip function is accurate and complete. The daughter card 204 can include a memory daughter card (for example, providing a DDR memory interface), a communication daughter card (for example, providing multiple network interfaces or a wireless network card interface), etc.

[0036] The host 100 can be used to configure the simulation tool 202 to simulate a design to be tested. The design to be tested can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, the host 100 can be a virtual host in a cloud computing system. The logic system design (e.g., ASIC or System-On-Chip) can be designed by a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). The host 100 configuration simulation tool 202 may include configuring the simulation environment (e.g., the connection relationship between multiple simulation tools 202 or the connection relationship between the simulation tool and the daughter card), etc.

[0037] The host 100 may compile the logic system design in the form of source code into an executable file. From a design perspective, the logic system design may include a design to be tested and a test bench (Testbench) corresponding to the design to be tested.

[0038] From the perspective of synthesis, the logic system design may include a synthesizable part and a non-synthesizable part. The synthesizable part usually corresponds to the actual physical design (e.g., a chip), while the non-synthesizable part usually includes an initialization module, a test bench, etc. The executable file formed by the non-synthesizable part after compilation can usually be run by the host 100. The synthesizable part also needs to be synthesized after compilation to form a gate-level netlist and a bit file. The bit file can be used to configure the FPGA 2026 to run according to the design requirements of the synthesizable part.

[0039] The host 100 may receive a request from a user to debug the design to be tested. As described above, the design to be tested may include one or more modules. The description of the design to be tested may be completed in a hardware description language. The host 100 may perform synthesis based on the description of the design to be tested to generate, for example, a gate-level circuit netlist (not shown) of the design to be tested. The gate-level circuit netlist of the design to be tested may be loaded into the simulation tool 202 for operation, and then a circuit structure corresponding to the design to be tested may be formed in the simulation tool 202. Therefore, the circuit structure of the design to be tested may be obtained according to the description, and accordingly, the circuit structure of each block in the design to be tested may also be obtained similarly.

[0040] Usually, the simulation of the design to be tested takes a long time. The existing technology can partition the design to be tested and then process it in parallel through partitioning technology, but the partitioning technology has high requirements for segmentation and requires tedious preliminary processing.

[0041] The applicant of the present invention proposes a method for simulating logic system design, which does not require segmentation of the logic system design and can perform parallel synthesis of the logic system design according to different modules. However, during the implementation process, the inventor of the present application found that when the logic system design is partitioned according to modules, the cross-module reference relationship (Cross-Module Reference, XMR) will cause data race problems in the module-based simulation logic system design proposed in the present application.

[0042] Figure 3 A schematic diagram showing the structure of an exemplary logic system design according to an embodiment of the present application is shown.

[0043] As shown in the figure, the description of the logic system design 310 based on the System Verilog language is as follows:

[0044] module top();

[0045] dut1 d1();

[0046] dut2 d2();

[0047] dut3 d3();

[0048] endmodule

[0049] module dut1(input in1);

[0050] assign top.d3.out3 = in1;

[0051] endmodule

[0052] module dut2(output out2);

[0053] assign out2 = top.d3.out3;

[0054] endmodule

[0055] module dut3(output out3);

[0056] endmodule

[0057] Description 310 defines a top module, which includes three submodules: dut1, dut2, and dut3. Each submodule has a corresponding netlist. For ease of understanding, Figure 3 A physical layer structure 300 corresponding to description 310 is shown.

[0058] like Figure 3 As shown, the submodules dut1, dut2 and dut3 correspond to the physical layer structures DUT 1, DUT 2 and DUT 3 respectively. Each physical layer structure module has a corresponding netlist. The netlist describes the connection relationship between the physical layer structure circuit elements. In DUT 1, in1 is the input port, and i1 is an instance of type BUF. In DUT 1, i2 is also an instance of type BUF, and out2 is the output port.

[0059] Among them, n1 in DUT 1, out3 in DUT 3 and n2 in dut2 are all net signals. It can be understood that the net here corresponds to multiple modules including DUT1, DUT2 and DUT3.

[0060] Each net signal has a data portref, which is used to indicate the connection relationship between the net signal and the port. Figure 3 As shown, n1 is connected to the output port of DUT 1 through portref, out3 is connected to the input port of DUT 2 through portref, and n2 is connected to the output port of DUT 2 through portref.

[0061] Each wire network signal also includes a data wire, which is used to indicate the connection relationship between wire network signals. Figure 3 As shown, out3 and n1 are connected via a data wire.

[0062] In some embodiments, according to the method proposed by the inventor of the present application, the simulation tool 202 can perform parallel synthesis on different modules of the logic system design 310. That is, the modules dut1 and dut2 are synthesized in parallel in different threads. More specifically, the physical modules DUT 1 and DUT 2 are synthesized in parallel in different threads.

[0063] When synthesizing module dut1, simulation tool 202 finds that n1 in physical module DUT 1 and out3 in DUT 3 are connected together. In the circuit, such connected net signals are equivalent, so simulation tool 202 should delete the redundant net signals. That is, net signal n1 in DUT 1 should be deleted. At the same time, data of out3 in DUT 3 needs to be updated, including wire and portref.

[0064] Meanwhile, the thread of the simulation tool 202 synthesizing dut2 is still accessing the wire and portref data of out3 in dut3.

[0065] The inventor of the present application discovered that since dut1 and dut2 both reference the data out3 of dut3 at the same time, that is, there is a cross-module reference (Cross-Module Reference, XMR) between multiple modules, multiple threads will perform read / write operations on the same variable at the same time, which will eventually lead to data contention (data-race) in the parallel integration of multiple modules.

[0066] Therefore, how to solve the data competition problem caused by cross-module references in the design of module-based parallel simulation logic system is an urgent problem that needs to be solved.

[0067] The inventor of the present application proposes a method for synthesizing multiple modules in parallel using a virtual netlist based on modules.

[0068] Figure 4 A schematic diagram of an exemplary method for designing a simulation logic system according to an embodiment of the present application is shown.

[0069] The simulation tool 202 can create a virtual netlist for a netlist including an XMR net. The XMR net is a wire net signal referenced across multiple modules. Figure 4As shown, out3 in DUT 3 is the XMR net. Accordingly, the simulation tool 202 will also create a corresponding virtual module for the physical module including the XMR net. Figure 4 In FIG. 4 , 400 is a schematic diagram of a physical layer structure including a virtual module.

[0070] In some embodiments, Figure 4 As shown, among DUT1-3, only DUT3 contains XMR net, namely out3. Simulation tool 202 creates a Virtual DUT 3 for DUT3.

[0071] It is understood that in some embodiments, the simulation tool 202 only creates a unique virtual netlist for the netlist including the XMR net, that is, only creates a unique virtual module for the module including the XMR net. Figure 4 Although out3 is used once in dut1 and dut2 respectively, the simulation tool 202 only creates a Virtual DUT 3 for DUT 3. This can save memory and reduce the time wasted in the processing process. In other embodiments, the simulation tool 202 can create a non-unique virtual netlist for the netlist including XMRnet, that is, create a non-unique virtual module for the module including XMRnet. For example, Figure 4 In the example, out3 is used once in dut1 and once in dut2. The simulation tool can create two virtual modules for DUT 3 and connect them to dut1 and dut2 respectively.

[0072] exist Figure 4 In the illustrated embodiment, because DUT 1 accesses out3 of DUT 3, a virtual net signal (virtual net) named "out3_1" is created in Virtual DUT 3, and n1 in module dut1 is connected to "out3_1". Because dut2 also accesses out3 of DUT 3, another virtual net signal is created, which belongs to Virtual DUT 3 together with out3_1. To avoid duplication of net signal names, the virtual net signal created the second time is called "out3_2".

[0073] The architecture diagram of two virtual wire net signals, out3_1 and out3_2, and XMR net, out3 is also as follows Figure 4 More specifically, the out3_1 netlist includes at least the following information:

[0074] Portref : …

[0075] Attribute_map

[0076] attribute_key: xmr_full_path

[0077] attribute_value: top.dut3

[0078] …

[0079] char *p_out3_1 = &out3_2;

[0080] …

[0081] Virtual DUT 3

[0082] …

[0083] Among them, the variable's Attribute_map only exists in the virtual wire net signal. attribute_key is the name of the variable, and attibute_value is the value of the variable. In out3_1, attribute_key is "xmr_full_path", indicating that the virtual wire net signal is created based on the XMR net signal; attibute_value is "top.dut3", indicating that the XMR net based on the virtual wire net signal is in the top.dut3 module, which is used for subsequent printing of the netlist. "char *p_out3_1 = &out3_2" means that the address pointer of out3_2 is stored in out3_1. "Virtual DUT3" means that the virtual wire net signal exists in the virtual module.

[0084] The out3_2 netlist includes at least the following information:

[0085] Portref : …

[0086] Attribute_map

[0087] attribute_key: xmr_full_path

[0088] attribute_value: top.dut3

[0089] …

[0090] char *p_out3_2 = &out3;

[0091] …

[0092] Virtual DUT3

[0093] …

[0094] Among them, the attribute_key in out3_2 is "xmr_full_path", indicating that the virtual wire net signal is created based on the XMR net signal; the attibute_value is "top.dut3", indicating that the XMR net based on the virtual wire net signal is in the top.dut3 module, which is used for subsequent printing of the netlist. "char *p_out3_2 = &out3" means that the address pointer of out3 is stored in out3_2. "Virtual DUT3" means that the virtual wire net signal exists in the virtual module.

[0095] out3 contains at least the following information:

[0096] Portref : …

[0097] char *p_out3 = &out3_1;

[0098] …

[0099] DUT3

[0100] …

[0101] Among them, "char *p_out3 = &out3_1" means that the address pointer of out3_1 is stored in out3. "DUT3" means that the virtual wire network signal exists in module DUT3.

[0102] It can be seen that the information of the module to which each wire net signal belongs is also stored in the wire net signal. Among them, out3 stores the address pointer of out3_1, out3_1 stores the address pointer of out3_2, and out3_2 stores the address pointer of out3. A circular linked list is formed between the virtual wire net signal and the XMR net, as shown in Figure 4, and the purpose is also to save memory.

[0103] During parallel synthesis, the simulation tool 202 will ignore the processing of optimizing virtual network signals in virtual modules or virtual netlists, that is, the simulation tool 202 will not optimize and delete virtual network signals.

[0104] Based on the above method, when the simulation tool 202 performs parallel synthesis on dut1 and dut2, data competition problems caused by cross-module references will no longer occur.

[0105] When synthesizing a module including a virtual netlist, the simulation tool 202 can also trace the address of the virtual netlist and print out a gate-level netlist of the logic system design.

[0106] More specifically, the simulation tool 202 first prints the netlist of the top module, and then prints the gate-level netlists of the submodules in sequence according to the order of the submodules in the top module. When the simulation tool 202 prints the gate-level netlist of dut1, it needs to print the names of the nets connected to the input / output ports of the BUF in dut1.

[0107] It can be known that out3_1 belongs to Virtual DUT 3, therefore, the simulation tool 202 determines that out3_1 is a virtual net. When the net is a virtual net, the value of the variable attribute_map in the virtual net is obtained: "top.dut3". The simulation tool 202 first prints the string "top.d3", and then finds out3_2 according to the address pointer stored in out3_1. Since out3_2 is still a virtual net, the above steps are repeated, and the simulation tool 202 can find out3. Since out3 belongs to DUT 3, not a virtual net, the simulation tool 202 prints out3.

[0108] It can be understood that when the simulation tool 202 prints dut3, the gate-level netlist of dut3 is directly printed, and the above-mentioned Virtual DUT 3 is not involved.

[0109] Finally, the simulation tool 202 can print out the gate-level netlist 410 of the logic system design. After the simulation is completed, the simulation tool 202 can delete the virtual module or virtual netlist to release memory space.

[0110] The embodiment of the present application also provides a method for simulating logic system design.

[0111] Figure 5 A flowchart of a method 500 for simulating logic system design according to an embodiment of the present application is shown, wherein the method 500 may be performed as follows: Figure 2 The simulation system 200 shown is executed. The method 500 may include the following steps.

[0112] In step 501, the simulation tool 202 obtains the description of the logic system design (eg, Figure 3 310), wherein the logical system design includes a plurality of modules, wherein the plurality of modules include a first module (eg, Figure 3 or Figure 4 DUT1 in), the second module (for example, Figure 3 or Figure 4 DUT3 in the Figure 3 or Figure 4 DUT2 in the figure).

[0113] In step 502, the simulation tool 202 determines a plurality of connections between the plurality of modules according to the description of the logic system design, wherein the plurality of connections includes a first connection between the first module and the second module (eg, Figure 3 The connection relationship between n1 in DUT1 and out3 in DUT3 as shown) and the second connection between the second module and the third module (for example, Figure 3 ). The connection relationship between the multiple modules is a tree-like relationship diagram.

[0114] In step 503, the simulation tool 202 determines at least one target module (eg, Figure 3 or Figure 4 DUT3 in the process), wherein the at least one target module includes the second module.

[0115] In step 504, the simulation tool 202 generates a virtual module (eg, Figure 4 Virtual DUT 3).

[0116] Wherein, the virtual module includes a first virtual connection and a second virtual connection, the first virtual connection corresponds to the first connection, and the second virtual connection corresponds to the second connection, and the method further includes: according to the multiple connection relationships, determining a first virtual connection connecting the first module and the virtual module, and a second virtual connection connecting the third module and the virtual module; based on the virtual module, generating a virtual gate-level netlist of the logic system design, the virtual gate-level netlist includes the virtual module; based on the virtual gate-level netlist, generating a gate-level netlist of the logic system design.

[0117] The method further includes: replacing the first virtual connection with the first connection and the second virtual connection with the second connection; and replacing the virtual module in the virtual gate-level netlist with the at least one target module.

[0118] In step 505 , the simulation tool 202 generates a gate-level netlist of the logic system design based on the virtual module.

[0119] Wherein, generating a gate-level netlist of the logic system design based on the virtual module further includes: synthesizing the first module, the second module, the virtual module and the third module in parallel.

[0120] The inventor of this application proposes a method for designing a logic system based on module parallel simulation, which does not require partitioning of the logic system design. This application completes the parallel processing of the logic system design by dividing the modules, which can greatly improve the performance of the simulation logic system design. This application also solves the data competition problem caused by cross-module references in the parallel synthesis process of modules by using a virtual netlist.

[0121] The present application also provides an electronic device. The electronic device may be Figure 1 The host 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device executes the method 500.

[0122] The embodiment of the present application further provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores a set of instructions for a computer, and the set of instructions is used to make the computer perform the method 500 when executed.

[0123] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0124] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0125] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0126] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A method for designing a simulation logic system, comprising: Obtaining a description of the logic system design, wherein the logic system design includes a plurality of modules, and the plurality of modules include a first module, a second module, and a third module; Determine a plurality of connections between the plurality of modules according to the description of the logic system design, wherein the plurality of connections include a first connection between the first module and the second module and a second connection between the second module and the third module; determining at least one target module according to the plurality of connections, wherein the at least one target module includes the second module; Generate a virtual module corresponding to the at least one target module according to the connection relationship of the at least one target module; A gate-level netlist of the logic system design is generated based on the virtual module.

2. The method of claim 1, wherein: The virtual module includes a first virtual connection and a second virtual connection, the first virtual connection corresponds to the first connection, and the second virtual connection corresponds to the second connection, and the method further includes: Determine, according to the multiple connections, a first virtual connection connecting the first module and the virtual module, and a second virtual connection connecting the third module and the virtual module; Based on the virtual module, generating a virtual gate-level netlist of the logic system design, the virtual gate-level netlist including the virtual module; Based on the virtual gate-level netlist, a gate-level netlist of the logic system design is generated.

3. The method of claim 2, wherein: Generating a gate-level netlist of the logic system design based on the virtual gate-level netlist further includes: replacing the first virtual connection with the first connection and the second virtual connection with the second connection; The virtual module in the virtual gate-level netlist is replaced with the at least one target module.

4. The method of claim 1, wherein: The connection relationship between the multiple modules is a tree-like relationship diagram.

5. The method of claim 1, wherein: Generating a gate-level netlist of the logic system design based on the virtual module further comprises: The first module, the second module, the virtual module and the third module are synthesized in parallel.

6. An electronic device comprising a memory for storing a set of instructions; and At least one processor is configured to execute the set of instructions so that the electronic device performs the method according to any one of claims 1-5.

7. A non-transitory computer-readable storage medium storing a set of instructions for a computer, the set of instructions being used to cause the computer to perform the method according to any one of claims 1 to 5 when executed.

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