A surface subdivision device and method, an electronic device, and a storage medium

Abstract

The present disclosure relates to a curved surface subdivision device and method, an electronic device, and a storage medium. The device includes: a curved surface subdivision module, a cache module, and a vertex coordinate determination module; the curved surface subdivision module is configured to perform subdivision processing on a target subdivision domain according to target subdivision parameters, and send the index values, edge information, and loop information of the subdivided vertices obtained during the subdivision processing to the cache module; the cache module is configured to bypass and forward the received index values, edge information, and loop information of the subdivided vertices to the vertex coordinate determination module; the vertex coordinate determination module is configured to determine the UV coordinates of the subdivided vertices according to the index values, edge information, and loop information of the subdivided vertices. Embodiments of the present disclosure can reduce the processing delay, resource consumption, and power consumption in the process of determining vertex UV coordinates.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a tessellation device and method, an electronic device, and a storage medium. Background Art

[0002] Tessellation is a technique used in computer graphics. It divides a set of surfaces representing objects in a scene into many smaller and simpler pieces (referred to as primitives). These pieces are usually triangles, which are more suitable for rendering. Typically, tessellation is performed on surfaces shaped like squares or triangles. After tessellation, multiple smaller primitives and the subdivided vertices of each primitive can be generated. In practical applications, it is necessary to determine the UV coordinates of the subdivided vertices of each primitive after tessellation before subsequent rendering operations can be continued. Summary of the Invention

[0003] The present disclosure proposes a technical solution for a tessellation device and method, an electronic device, and a storage medium.

[0004] According to one aspect of the present disclosure, a tessellation device is provided, including: a tessellation module, a cache module, and a vertex coordinate determination module; the tessellation module is configured to perform a tessellation process on a target tessellation domain according to target tessellation parameters, and send the index values, edge information, and loop information of the subdivided vertices obtained during the tessellation process to the cache module for caching; the cache module is configured to bypass and forward the received index values, edge information, and loop information of the subdivided vertices to the vertex coordinate determination module; the vertex coordinate determination module is configured to determine the UV coordinates of the subdivided vertices according to the index values, edge information, and loop information of the subdivided vertices.

[0005] In a possible implementation, the device further includes: a preprocessing module; the preprocessing module is configured to preprocess the initial tessellation parameters to obtain the target tessellation parameters, and send the target tessellation parameters to the tessellation module and the vertex coordinate determination module.

[0006] In a possible implementation, the vertex coordinate determination module is specifically configured to: determine the offset value of the subdivided vertex according to the index value, edge information, and loop information of the subdivided vertex; determine the UV coordinates of the subdivided vertex according to the target tessellation parameters and the offset value of the subdivided vertex.

[0007] In a possible implementation, the tessellation module is specifically configured to: send each topology obtained during the tessellation process and the corresponding index values, edge information, and loop information of the tessellated vertices to the cache module for caching according to the output topology in the target tessellation parameters, where the output topology includes one of the following: point, line, surface.

[0008] According to one aspect of the present disclosure, a tessellation method is provided, including: using a tessellation module to perform a tessellation process on a target tessellation domain according to target tessellation parameters, and sending the index values, edge information, and loop information of the tessellated vertices obtained during the tessellation process to a cache module for caching; using the cache module to bypass and forward the index values, edge information, and loop information of the tessellated vertices to a vertex coordinate determination module; using the vertex coordinate determination module to determine the UV coordinates of the tessellated vertices according to the index values, edge information, and loop information of the tessellated vertices.

[0009] In a possible implementation, the method further includes: using a preprocessing module to preprocess the initial tessellation parameters to obtain the target tessellation parameters, and sending the target tessellation parameters to the tessellation module and the vertex coordinate determination module.

[0010] In a possible implementation, the determining the UV coordinates of the tessellated vertices according to the index values, edge information, and loop information of the tessellated vertices includes: determining the offset value of the tessellated vertices according to the index values, edge information, and loop information of the tessellated vertices; determining the UV coordinates of the tessellated vertices according to the target tessellation parameters and the offset value of the tessellated vertices.

[0011] In a possible implementation, the sending the index values, edge information, and loop information of the tessellated vertices obtained during the tessellation process to the cache module for caching includes: using the tessellation module to send each topology obtained during the tessellation process and the corresponding index values, edge information, and loop information of the tessellated vertices to the cache module for caching according to the output topology in the target tessellation parameters, where the output topology includes one of the following: point, line, surface.

[0012] According to one aspect of the present disclosure, an electronic device is provided, including: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0013] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented.

[0014] In an embodiment of the present disclosure, a surface tessellation module, a cache module, and a vertex coordinate determination module are provided in a surface tessellation device. The surface tessellation module performs a tessellation process on a target tessellation domain according to target tessellation parameters, and sends the index values, edge information, and loop information of the tessellated vertices obtained during the tessellation process to the cache module for caching. The cache module directly bypasses and forwards the received index values, edge information, and loop information of the tessellated vertices to the vertex coordinate determination module, so that the vertex coordinate determination module can directly determine the UV coordinates of the tessellated vertices according to the index values, edge information, and loop information of the tessellated vertices, thereby reducing the processing delay, resource consumption, and power consumption during the process of determining the vertex UV coordinates.

[0015] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the present disclosure. According to the following detailed description of exemplary embodiments with reference to the accompanying drawings, other features and aspects of the present disclosure will become clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0017] Figure 1 A block diagram showing a surface tessellation device according to an embodiment of the present disclosure.

[0018] Figure 2 A schematic diagram showing a triangular target tessellation domain according to an embodiment of the present disclosure.

[0019] Figure 3 A schematic diagram showing a quadrilateral target tessellation domain according to an embodiment of the present disclosure.

[0020] Figure 4 A schematic diagram showing a linear target tessellation domain according to an embodiment of the present disclosure.

[0021] Figure 5 A flowchart showing a surface tessellation device performing surface tessellation according to an embodiment of the present disclosure.

[0022] Figure 6 A flowchart showing a surface tessellation method according to an embodiment of the present disclosure.

[0023] Figure 7 A block diagram showing an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. Like reference numerals in the drawings denote functionally identical or similar elements. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0025] As used herein, the term "exemplary" means "serving as an example, embodiment, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as superior to or better than other embodiments.

[0026] As used herein, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" as used herein means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set composed of A, B, and C.

[0027] In addition, for a better illustration of the present disclosure, numerous specific details are given in the following detailed description. Those skilled in the art should understand that the present disclosure can be implemented without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0028] Tessellation is a technique used in computer graphics that divides a set of surfaces representing objects in a scene into many smaller and simpler patches (called primitives). Such patches are typically triangles, which are more suitable for rendering. Surface subdivision is usually performed on surfaces shaped like squares or triangles. After surface subdivision, multiple smaller primitives and the subdivided vertices of each primitive can be generated. In practical applications, it is necessary to determine the UV coordinates of the subdivided vertices of each primitive after surface subdivision before subsequent rendering operations can be continued. In the related art, the solutions for determining the UV coordinates of the subdivided vertices have problems such as processing delay, resource consumption, and high power consumption.

[0029] Embodiments of the present disclosure provide a tessellation device that can reduce the processing delay, resource consumption, and power consumption for determining the UV coordinates of the subdivided vertices. The tessellation device provided by the embodiments of the present disclosure will be described in detail below.

[0030] Figure 1 A block diagram showing a tessellation device according to an embodiment of the present disclosure is as follows Figure 1As shown, the surface subdivision device includes: a surface subdivision module, a cache module, and a vertex coordinate determination module; the surface subdivision module is used to perform subdivision processing on the target subdivision domain according to the target subdivision parameters, and send the index value, edge information, and ring information of the subdivided vertex obtained during the subdivision processing to the cache module for caching; the cache module is used to bypass forward the received index value, edge information, and ring information of the subdivided vertex to the vertex coordinate determination module; the vertex coordinate determination module is used to determine the UV coordinates of the subdivided vertex according to the index value, edge information, and ring information of the subdivided vertex.

[0031] The target segmentation parameter here refers to parameter information used to guide the segmentation processing of the target segmentation domain. The specific form of the target segmentation parameter can be flexibly determined according to the actual situation, and the present disclosure does not make specific limitations on this.

[0032] The target subdivision domain here is the area where the subdivision process needs to be performed. The type of the target subdivision domain can be a quadrilateral, a triangle, or a straight line, which is not specifically limited in the present disclosure.

[0033] Figure 2 A schematic diagram of a triangular target subdivision domain according to an embodiment of the present disclosure is shown. The target subdivision domain is Figure 2 The area formed by the outermost triangle in the target subdivision domain can be subdivided into multiple triangles based on the target subdivision parameters. Figure 2 The figure only shows a few subdivided triangles as examples, and does not limit the subdivision results.

[0034] Figure 3 A schematic diagram of a quadrilateral target subdivision domain according to an embodiment of the present disclosure is shown. The target subdivision domain is Figure 3 The area formed by the outermost quadrilateral in the target subdivision domain can be subdivided into multiple triangles based on the target subdivision parameters. Figure 3 The figure only shows a few subdivided triangles as examples, and does not limit the subdivision results.

[0035] Figure 4 A schematic diagram of a straight line target segmentation domain according to an embodiment of the present disclosure is shown. The target segmentation domain is Figure 4 The longest straight line in the target segmentation domain can be subdivided into multiple smaller line segments based on the target segmentation parameters. Figure 3 The figure only shows a few segmented line segments as examples, and does not limit the segmentation results.

[0036] The tessellation module can perform tessellation processing on the target tessellation domain according to the target tessellation parameters. During the tessellation process, the index values (index), edge information (edge), and ring information (ring) of the tessellated vertices are obtained. The tessellation module sends the index values, edge information, and ring information of the tessellated vertices obtained during the tessellation process to the cache module for caching.

[0037] For any one of the tessellated vertices, the index value of the tessellated vertex is used to uniquely identify the tessellated vertex.

[0038] As Figure 2 shown, the target tessellation domain is the area composed of the outermost triangles. After performing surface tessellation, the tessellated vertices from 0 to 18 are obtained, and 0 to 18 are the index values of the tessellated vertices. The index values of the tessellated vertices can be represented in other forms according to the actual application scenarios in addition to being represented by numbers. The present disclosure does not make specific limitations on this.

[0039] For any one of the tessellated vertices, the edge information of the tessellated vertex is used to indicate the edge where the tessellated vertex is located. Among them, for any one of the tessellated vertices, the edge where the tessellated vertex is located may be a newly generated edge during the tessellation process or an original edge in the target tessellation domain.

[0040] As Figure 2 shown, the edge information of the tessellated vertex 0 is used to indicate the edge where the tessellated vertex 0 is located (the edge formed by the tessellated vertices 0 to 4), which is an original edge in the target tessellation domain; the edge information of the tessellated vertex 12 is used to indicate the edge where the tessellated vertex 12 is located (the edge formed by the tessellated vertices 12 to 14), which is a newly generated edge during the tessellation process. The same applies to other tessellated vertices and will not be elaborated.

[0041] For any one of the tessellated vertices, the ring information of the tessellated vertex is used to indicate the closed ring where the edge where the tessellated vertex is located is located. Among them, for any one of the tessellated vertices, the closed ring where the tessellated vertex is located may be a newly generated closed ring during the tessellation process or an original closed ring in the target tessellation domain.

[0042] As Figure 2 shown, the ring information of the tessellated vertex 2 is used to indicate the closed ring where the tessellated vertex 2 is located (the closed ring formed by the tessellated vertices 0 to 11), which is an original closed ring in the target tessellation domain; the ring information of the tessellated vertex 15 is used to indicate the closed ring where the tessellated vertex 15 is located (the closed ring formed by the tessellated vertices 12 to 17), which is a newly generated closed ring during the tessellation process. The same applies to other tessellated vertices and will not be elaborated. Figure 3 、 Figure 4 The index values, edge information, and ring information of the tessellated vertices in

[0043] UV coordinates, also known as texture coordinates, are two-dimensional coordinates used for texture mapping. The range of UV coordinates is typically between 0 and 1, where U represents the texture coordinate in the horizontal direction and V represents the texture coordinate in the vertical direction. Each subdivided vertex has a corresponding UV coordinate in three-dimensional space, and these coordinates define the mapping method of the texture image on the surface of the three-dimensional model.

[0044] After sending the index values, edge information, and loop information of the subdivided vertices obtained during the subdivision process to the cache module, in order to reduce the latency caused by the vertex coordinate determination module reading from the cache module, the cache module can directly bypass and forward the index values, edge information, and loop information of the subdivided vertices to the vertex coordinate determination module. That is, the vertex coordinate determination module can bypass the data lookup process of the cache module and directly obtain the index values, edge information, and loop information of the subdivided vertices. Furthermore, the vertex coordinate determination module can quickly determine the UV coordinates of the subdivided vertices based on the index values, edge information, and loop information of the subdivided vertices, thereby reducing the processing latency, resource consumption, and power consumption during the vertex UV coordinate determination process.

[0045] In one example, the storage module is a Content Addressable Memory (CAM). A CAM is a special type of memory that allows lookup based on content rather than address.

[0046] The surface differentiation module sends the index values, edge information, and loop information of the subdivided vertices obtained during the surface subdivision process to the CAM, and the CAM bypasses and forwards the index values, edge information, and loop information of the subdivided vertices to the vertex coordinate determination module.

[0047] After determining the UV coordinates of the subdivided vertices, by adjusting the UV coordinates, effects such as stretching, distortion, and repetition of the texture image on the model surface can be controlled, thereby achieving a more realistic and detailed texture mapping.

[0048] In the embodiments of the present disclosure, a surface subdivision module, a cache module, and a vertex coordinate determination module are provided in the surface subdivision device. The surface subdivision module performs subdivision processing on the target subdivision domain according to the target subdivision parameters and sends the index values, edge information, and loop information of the subdivided vertices obtained during the subdivision process to the cache module for caching. The cache module directly bypasses and forwards the received index values, edge information, and loop information of the subdivided vertices to the vertex coordinate determination module, so that the vertex coordinate determination module can quickly determine the UV coordinates of the subdivided vertices based on the index values, edge information, and loop information of the subdivided vertices, thereby reducing the processing latency, resource consumption, and power consumption during the vertex UV coordinate determination process.

[0049] In a possible implementation, the tessellation device further includes: a preprocessing module; the preprocessing module is configured to preprocess the initial tessellation parameters to obtain target tessellation parameters, and send the target tessellation parameters to the tessellation module and the vertex coordinate determination module.

[0050] The initial tessellation parameters may be basic parameters input by the target user. For example, the type of the target tessellation domain (Domain type), the outside tessellation factor, the inside tessellation factor, the partitioning scheme, the output topology, etc.

[0051] By preprocessing the initial tessellation parameters, more detailed target tessellation parameters can be obtained to specifically guide the tessellation process. For example, the target tessellation parameters include: the parity of the tessellation factor, which is used to control the tessellation degree of the target tessellation domain. The specific content of the target tessellation parameters may refer to the tessellation scheme in the related art, and the present disclosure does not make specific limitations thereto.

[0052] After the preprocessing module preprocesses the initial tessellation parameters to obtain the target tessellation parameters, the tessellation module can perform a tessellation process on the target tessellation domain based on the target tessellation parameters.

[0053] Figure 5 The flowchart showing a tessellation device according to an embodiment of the present disclosure performing a tessellation process is as follows. Figure 5 As shown, the preprocessing module preprocesses the initial tessellation parameters to obtain the target tessellation parameters, and sends the target tessellation parameters to the tessellation module and the vertex coordinate determination module; the tessellation module performs a tessellation process on the target tessellation domain based on the target tessellation parameters.

[0054] In a possible implementation, the tessellation module is specifically configured to: according to the output topology in the target tessellation parameters, send each topology obtained during the tessellation process and its corresponding index values of the tessellated vertices, edge information, and loop information to the cache module for caching, where the output topology includes one of the following: point, line, surface.

[0055] The output topology obtained during the tessellation process refers to the form in which the tessellated vertices are output after performing a tessellation process on the target tessellation domain.

[0056] As Figure 2As shown, in the scenario where subdivision processing is performed on triangles: when the output topology structure is a point, the index value, edge information, and ring information of each subdivided vertex obtained during the subdivision process are cached; when the output topology structure is a line, the index value, edge information, and ring information of each line segment and its corresponding subdivided vertex obtained during the subdivision process are cached; when the output topology structure is a face, each small triangle (only two small triangles are drawn in the figure as an example, and the same applies to other small triangles) obtained during the subdivision process and its corresponding subdivided vertex are cached.

[0057] like Figure 5 As shown, the surface subdivision module sends the topological structure obtained during the surface subdivision process and the index value, edge information, and ring information of the subdivided vertex corresponding to the topological structure to the cache module for caching. The cache module bypasses the index value, edge information, and ring information of the subdivided vertex to the vertex coordinate determination module. The vertex coordinate determination module quickly determines the UV coordinates of the subdivided vertex based on the index value, edge information, and ring information of the subdivided vertex, and then combines the target subdivision parameters.

[0058] In a possible implementation, the fixed-point coordinate determination module is specifically used to: determine the offset value of the subdivided vertex according to the index value, edge information, and ring information of the subdivided vertex; determine the UV coordinate of the subdivided vertex according to the target subdivision parameter and the offset value of the subdivided vertex.

[0059] Since the cache module has bypassed and forwarded the index value, edge information, and ring information of the subdivided vertices obtained in the subdivision process to the vertex coordinate determination module, the vertex coordinate determination module can directly determine the offset value of the subdivided vertex based on the index value, edge information, and ring information of the subdivided vertex obtained in the subdivision process, and then can quickly determine the UV coordinates of the subdivided vertex based on the target subdivision parameters and the offset value of the subdivided vertex, thereby reducing the processing delay, resource consumption, and power consumption of the vertex UV coordinate determination process.

[0060] like Figure 2 As shown, the UV coordinate of vertex 4 after subdivision is (0,0), the UV coordinate of vertex 3 after subdivision is (1,1 / 4), and so on.

[0061] Finally, the topological structure and the UV coordinates of the subdivided vertices corresponding to the topological structure are output to perform subsequent rendering processing.

[0062] In an embodiment of the present disclosure, a surface tessellation module, a cache module, and a vertex coordinate determination module are provided in a surface tessellation device. The surface tessellation module performs a tessellation process on a target tessellation domain according to target tessellation parameters, and sends the index values, edge information, and loop information of the tessellated vertices obtained during the tessellation process to the cache module for caching. The cache module directly bypass-forwards the received index values, edge information, and loop information of the tessellated vertices to the vertex coordinate determination module, so that the vertex coordinate determination module can quickly determine the UV coordinates of the tessellated vertices according to the index values, edge information, and loop information of the tessellated vertices, thereby reducing the processing delay, resource consumption, and power consumption during the process of determining the vertex UV coordinates.

[0063] Figure 6 FIG. shows a flowchart of a surface tessellation method according to an embodiment of the present disclosure. This method can be executed by an electronic device such as a terminal device or a server. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. This method can be implemented by a processor calling computer-readable instructions stored in a memory. Alternatively, the server can execute this method. As Figure 6 shown, the method includes:

[0064] In step S61, the surface tessellation module is used to perform a tessellation process on the target tessellation domain according to the target tessellation parameters, and send the index values, edge information, and loop information of the tessellated vertices obtained during the tessellation process to the cache module for caching.

[0065] In step S62, the cache module is used to bypass-forward the index values, edge information, and loop information of the tessellated vertices to the vertex coordinate determination module;

[0066] In step S63, the vertex coordinate determination module is used to determine the UV coordinates of the tessellated vertices according to the index values, edge information, and loop information of the tessellated vertices.

[0067] In a possible implementation, the method further includes: using a preprocessing module to preprocess the initial tessellation parameters to obtain the target tessellation parameters, and sending the target tessellation parameters to the surface tessellation module and the vertex coordinate determination module.

[0068] In a possible implementation manner, determining the UV coordinates of the subdivided vertices according to the index values, edge information, and loop information of the subdivided vertices includes: determining the offset value of the subdivided vertices according to the index values, edge information, and loop information of the subdivided vertices; and determining the UV coordinates of the subdivided vertices according to the target subdivision parameter and the offset value of the subdivided vertices.

[0069] In a possible implementation manner, sending the index values, edge information, and loop information of the subdivided vertices obtained during the subdivision process to a cache module for caching includes: using a surface subdivision module to send each topological structure and its corresponding index values, edge information, and loop information of the subdivided vertices obtained during the subdivision process to the cache module for caching according to the output topological structure in the target subdivision parameter, where the output topological structure includes one of the following: point, line, surface.

[0070] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not elaborate further. Those skilled in the art can understand that in the above methods of the specific implementation manner, the specific execution order of each step should be determined according to its function and possible internal logic.

[0071] In addition, the present disclosure also provides an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any surface subdivision method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be elaborated here.

[0072] This method has a specific technical association with the internal structure of a computer system and can solve technical problems such as how to improve the hardware operation efficiency or execution effect (including reducing the data storage amount, reducing the data transmission amount, and improving the hardware processing speed), thereby obtaining a technical effect of improving the internal performance of the computer system that conforms to the laws of nature.

[0073] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the methods described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be elaborated here.

[0074] The embodiments of the present disclosure also propose a computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above methods are implemented. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0075] The embodiments of the present disclosure also propose an electronic device, including: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to call the instructions stored in the memory to execute the above methods.

[0076] Embodiments of the present disclosure also provide a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0077] The electronic device may be provided as a terminal, a server, or other forms of devices.

[0078] Figure 7 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Referring to Figure 7 , the electronic device 1900 may be provided as a server or a terminal device. Referring to Figure 7 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by a memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in the memory 1932 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute instructions to perform the above method.

[0079] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as the Microsoft server operating system (Windows Server TM ), the graphical user interface-based operating system launched by Apple Inc. (Mac OS X TM ), the multi-user and multi-process computer operating system (Unix TM ), the free and open-source Unix-like operating system (Linux TM ), the open-source Unix-like operating system (FreeBSD TM ), or the like.

[0080] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as the memory 1932 including computer program instructions. The above computer program instructions may be executed by the processing component 1922 of the electronic device 1900 to complete the above method.

[0081] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0082] A computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, (but is not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium as used herein is not construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0083] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include a copper transmission cable, an optical fiber transmission, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0084] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine - related instructions, microcode, firmware instructions, state - setting data, or source code or object code written in any combination of one or more programming languages, including object - oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer - readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand - alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer - readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field - programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer - readable program instructions to implement various aspects of the present disclosure.

[0085] Aspects of the present disclosure are described herein with reference to the flowchart and / or block diagram of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowchart and / or block diagram, and combinations of blocks in the flowchart and / or block diagram, can be implemented by computer - readable program instructions.

[0086] These computer - readable program instructions can be provided to a processor of a general - purpose computer, a special - purpose computer, or other programmable data - processing apparatus to produce a machine such that the instructions, when executed by the processor of the computer or other programmable data - processing apparatus, create a means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer - readable program instructions can also be stored in a computer - readable storage medium, which causes a computer, a programmable data - processing apparatus, and / or other devices to operate in a particular manner, so that the computer - readable medium storing the instructions includes a manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0087] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices, causing a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other devices to produce a computer-implemented process, so that the instructions executed on the computer, other programmable data processing apparatus, or other devices implement the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0088] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a portion of an instruction, which contains one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two consecutive blocks may in fact be executed substantially in parallel, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or by a combination of dedicated hardware and computer instructions.

[0089] The computer program product may be implemented specifically by means of hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium. In another alternative embodiment, the computer program product is embodied as a software product, such as a Software Development Kit (SDK), etc.

[0090] The above descriptions of the various embodiments tend to emphasize the differences between the various embodiments. Their similarities or resemblances can be referred to each other. For the sake of brevity, they will not be elaborated herein.

[0091] Those skilled in the art can understand that in the above methods of the specific implementation manners, the writing order of the steps does not mean a strict execution order and impose any limitation on the implementation process. The specific execution order of each step should be determined according to its function and possible internal logic.

[0092] If the technical solution of this application involves personal information, the product using the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using the technical solution of this application has obtained the individual's separate consent before processing the sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, clear and prominent signs are set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that he or she agrees to the collection of his or her personal information; or on the device that processes personal information, the personal information processing rules are notified by obvious signs / information, and the individual's authorization is obtained through pop-up information or by asking the individual to upload his or her personal information; among them, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0093] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A surface subdivision device, characterized in that: include: Surface subdivision module, cache module, vertex coordinate determination module; The surface subdivision module is used to perform subdivision processing on the target subdivision domain according to the target subdivision parameters, and send the index value, edge information, and ring information of the subdivided vertices obtained during the subdivision processing to the cache module for caching; The cache module is used to directly bypass and forward the received index value, edge information, and ring information of the subdivided vertex to the vertex coordinate determination module; The vertex coordinate determination module is used to bypass the data search process of the cache module, directly obtain the index value, edge information, and ring information of the subdivided vertex, and determine the UV coordinates of the subdivided vertex based on the index value, edge information, and ring information of the subdivided vertex.

2. The device according to claim 1, characterized in that The device also includes: a pre-processing module; The preprocessing module is used to preprocess the initial subdivision parameters to obtain the target subdivision parameters, and send the target subdivision parameters to the surface subdivision module and the vertex coordinate determination module.

3. The device according to claim 1 or 2, characterized in that: The vertex coordinate determination module is specifically used for: Determine the offset value of the subdivided vertex according to the index value, edge information, and ring information of the subdivided vertex; The UV coordinates of the subdivided vertices are determined according to the target subdivision parameters and the offset values ​​of the subdivided vertices.

4. The device according to claim 1, characterized in that The surface subdivision module is specifically used for: According to the output topological structure in the target subdivision parameters, each topological structure obtained during the subdivision process and its corresponding index value of the subdivided vertex, edge information, and ring information are sent to the cache module for caching, wherein the output topological structure includes one of the following: point, line, and surface.

5. A surface subdivision method, characterized in that: include: Using the surface subdivision module, performing subdivision processing on the target subdivision domain according to the target subdivision parameters, and sending the index value, edge information, and ring information of the subdivided vertices obtained during the subdivision processing to the cache module for caching; By utilizing the cache module, the index value, edge information, and ring information of the subdivided vertex are directly forwarded to the vertex coordinate determination module by bypassing; By utilizing the vertex coordinate determination module, the data search process of the cache module is bypassed, and the index value, edge information, and ring information of the subdivided vertex are directly obtained, and the UV coordinates of the subdivided vertex are determined according to the index value, edge information, and ring information of the subdivided vertex.

6. The method according to claim 5, characterized in that The method further comprises: The initial subdivision parameters are preprocessed by using a preprocessing module to obtain the target subdivision parameters, and the target subdivision parameters are sent to the surface subdivision module and the vertex coordinate determination module.

7. The method according to claim 5 or 6, characterized in that: The step of determining the UV coordinates of the subdivided vertices according to the index values, edge information, and ring information of the subdivided vertices includes: Determine the offset value of the subdivided vertex according to the index value, edge information, and ring information of the subdivided vertex; The UV coordinates of the subdivided vertices are determined according to the target subdivision parameters and the offset values ​​of the subdivided vertices.

8. The method according to claim 5, characterized in that The step of sending the index value, edge information, and ring information of the subdivided vertices obtained in the subdivision process to the cache module for caching includes: Utilizing the surface subdivision module, according to the output topological structure in the target subdivision parameters, each topological structure obtained during the subdivision process and its corresponding index value of the subdivided vertex, edge information, and ring information are sent to the cache module for caching, wherein the output topological structure includes one of the following: point, line, and surface.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 5 to 8.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 5 to 8 is implemented.

Images