A cache control method and device, electronic equipment and readable storage medium

Abstract

Embodiments of the present application provide a cache control method and device, electronic equipment and readable storage medium, the method comprising: in the case of receiving a memory access request of a memory access module, recording request information of the memory access request into a memory access register of a control module, waiting for arbitration of an arbitration unit and then sending to a cache pipeline unit; using the cache pipeline unit to query whether the memory access request hits the cache; in the case of the memory access request hitting the cache, executing the memory access request; in the case of the memory access request not hitting the cache, adjusting the state of the memory access register to a dormant state and sending a first request to a master node; the first request is used to obtain cache data required by the memory access request. Embodiments of the present application can guarantee cache consistency in a multi-core processor system without excessive hardware overhead and bus overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a cache control method and device, electronic equipment and readable storage medium. BACKGROUND

[0002] With the continuous development of processor technology, many-core processors have become mainstream, and each processor core can independently execute instructions and access memory. However, such parallel processing also brings the problem of data consistency. In many-core processors, each processor core has its own local cache (Cache) to store recently accessed data and instructions to improve access speed.

[0003] Therefore, when multiple processor cores need to access and modify the same data at the same time, it may cause data inconsistency. To solve this problem, cache coherence technology is usually used to ensure consistency between different processor cores. Directory-Based Coherence Protocol is a technology used in early multi-processor systems, and its core idea is to record the state and location information of each data block in the system through a centralized directory structure, so that the consistency of the data can be ensured when processors access and update data. This approach has obvious disadvantages. First, the directory structure is large in many-core structure, and the hardware overhead is unacceptable. Second, the way to maintain cache coherence is single, and there is often a problem of low data access efficiency under large-scale processor structure. Bus Snooping coherence protocol is a more widely used coherence protocol. In bus snooping technology, each processor's cache controller records the state of updated cache data and monitors the communication on the system bus to track and respond to the operations of other processors on the memory data block. Common protocols include MESI, MOESI, etc. Bus snooping requires each processor core to monitor the bus state in real time, which consumes a lot of bus and affects system performance. SUMMARY

[0004] The embodiments of the present application provide a cache control method, device, electronic equipment and readable storage medium, which can solve the problems of large hardware overhead and large bus consumption of cache coherence technology in related technologies.

[0005] To solve the above problems, the embodiments of the present application disclose a cache control method applied to a local cache controller, wherein the local cache controller comprises a bus interface module, a control module and a cache pipeline unit; the method comprises:

[0006] In a case that a memory access request of the memory access module is received, record request information of the memory access request into a memory access register of the control module, and send the memory access request to the cache pipeline unit after arbitration of an arbitration unit;

[0007] Query whether the memory access request hits the cache by using the cache pipeline unit;

[0008] In a case that the memory access request hits the cache, execute the memory access request;

[0009] In a case that the memory access request does not hit the cache, adjust a state of the memory access register to a dormant state, and send a first request to a master node; the first request is used to acquire cache data required by the memory access request.

[0010] Optionally, the memory access request comprises a memory read request; and in the case that the memory access request does not hit the cache, adjusting the state of the memory access register to the dormant state and sending the first request to the master node comprises:

[0011] In a case that the memory read request does not hit the cache, adjusting the state of the memory access register to the dormant state and setting a read transaction register in the control module, and sending a first read request to the master node; the first read request is used to request first target data required by the memory read request;

[0012] After reading the first target data returned by the master node from the read transaction register, activating the memory access register and setting a first flag bit of the read transaction register; the first flag bit is used to indicate sending a response message;

[0013] Sending a first response message to the master node; the first response message is used to indicate receiving a response of the master node to the first read request.

[0014] Optionally, in the case that the memory access request hits the cache, executing the memory access request comprises:

[0015] In a case that the memory read request hits the cache, writing first target data corresponding to a first request address of the memory read request back to the memory access register.

[0016] Optionally, the memory access request comprises a memory write request; and in the case that the memory access request hits the cache, executing the memory access request comprises:

[0017] In a case that the memory write request hits the cache, querying a second cache line state corresponding to a second request address of the memory write request;

[0018] If the second cache line state is the modified state or the exclusive state, write the second target data carried by the memory access write request back to the cache.

[0019] Optionally, the method further comprises:

[0020] If the second cache line state is the shared state, adjust the state of the core register to the sleep state, set a non-data transaction register, and send a second request to the master node; the second request is used to adjust the second cache line state to the exclusive state.

[0021] In a case where the second response message of the master node for the second request is received, send a third response message to the master node; the third response message is used to indicate that the second response message has been received.

[0022] Optionally, in a case where the memory access request misses the cache, adjusting the state of the memory register to the sleep state and sending a first request to the master node comprises:

[0023] In a case where the memory access write request misses the cache, adjusting the state of the memory register to the sleep state, writing the resolution result of the memory access request into a second flag bit of a read transaction register through the cache pipeline unit, setting the second flag bit, and initiating a second read request to the master node; the second read request is used to read the cache data corresponding to the second request address and set the cache data corresponding to the second request address in other processor cores to invalid data.

[0024] Receiving the cache data returned by the master node and replacing the cache data with the second target data carried in the memory access write request;

[0025] Setting a first flag bit of the read transaction register and sending a fourth response message to the master node; the fourth response message is used to indicate that the response of the master node for the second read request is received.

[0026] Optionally, the method further comprises:

[0027] In a case where the third request sent by the master node is received, judging whether there is an address item same as a third request address of the third request in the memory register of the control module;

[0028] If there is an address item same as the third request address in the memory register, setting the priority of the third request to the lowest priority, and sending the cache pipeline unit after arbitration by an arbitration unit;

[0029] If there is no address item in the access register that is the same as the third request address, the priority of the third request is set to the highest priority.

[0030] In another aspect, the embodiment of the present application discloses a cache control device applied to a local cache controller, wherein the local cache controller comprises a bus interface module, a control module and a cache pipeline unit; the device comprises:

[0031] A request receiving module is configured to record request information of an access request of an access module into an access register of the control module in a case where the access request is received, and send the access request to the cache pipeline unit after arbitration by an arbitration unit;

[0032] A query module is configured to query whether the access request hits a cache by using the cache pipeline unit;

[0033] An execution module is configured to execute the access request in a case where the access request hits the cache;

[0034] An adjustment module is configured to adjust a state of the access register to a dormant state and send a first request to a master node in a case where the access request does not hit the cache; the first request is used to acquire cache data required by the access request.

[0035] In another aspect, the embodiment of the present application further discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the cache control method.

[0036] The embodiment of the present application further discloses a readable storage medium, when instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the cache control method.

[0037] The embodiment of the present application has the following advantages:

[0038] The embodiment of the present application provides a cache control method, and the bus interface module, the controller and the cache pipeline unit in the local cache controller are cooperatively used to realize non-blocking pipeline processing of an access request; and in a case where cache misses, the state of the access register is adjusted to a dormant state, and a first request is sent to a master node, the master node processes requests from various nodes, and cache consistency and memory management are maintained, so that cache consistency in a multi-core processor system is ensured without excessive hardware cost and bus cost. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0040] Figure 1 is a step flow chart of a cache control method embodiment of the present application;

[0041] Figure 2 is an architecture schematic diagram of a local cache controller of the present application;

[0042] Figure 3 is a processing flow schematic diagram of a processor read request of the present application;

[0043] Figure 4 is a processing flow schematic diagram of a processor write request of the present application;

[0044] Figure 5 is a structure block diagram of a cache control device embodiment of the present application;

[0045] Figure 6 is a structure block diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the protection scope of the present application.

[0047] The terms "first", "second" and the like in the specification and claims of the present application are used to distinguish similar objects, not to describe a particular order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second" and the like are generally a class, not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0048] Method embodiments

[0049] First, some professional terms that may be involved in the present application are explained and described:

[0050] Coherent Hub Interface (CHI) protocol is a protocol for building high-performance, low-power multi-processor systems. It provides an efficient, low-latency method to connect multiple processors, accelerators, memories and other system components to achieve shared memory access and cache coherence. CHI protocol is an evolution of AXI Coherent Extension (ACE) protocol, which is part of Arm's AMBA bus, designed to solve cache coherence problems in multi-core processor systems.

[0051] MESI (Modified, Exclusive, Shared, Invalid) protocol: a common cache coherence protocol used in multi-processor systems for cache coherence management. It ensures that the contents of multiple processors' caches remain consistent by attaching state information to each cache line.

[0052] Cache: a high-speed memory with faster access speed than system memory, comparable to CPU processing speed, but much smaller capacity than system memory. Cache is based on the principle of "locality of program execution and data access" in memory, that is, within a certain program execution time and space, the accessed code and data will concentrate in a part.

[0053] Network-on-Chip (NoC): a communication network structure implemented on an integrated circuit chip, used to connect various functional modules, processor cores, memory units and other important components on the chip. With the increasing integration of chips and the rise of multi-core processors, NoC has become increasingly important as it provides an efficient, low-latency communication method within the chip.

[0054] Request Node (RN): refers to the node responsible for generating transaction requests and sending these requests to other nodes in the system. In the ARM AMBA CHI protocol, RN is the key component responsible for initiating transaction requests and interacting with other system nodes. Its main functions include generating transaction requests, address translation and routing, transaction management, and maintaining cache coherence. Through these functions, RN ensures the efficiency and consistency of data transmission in high-performance computing systems.

[0055] Cache Pipeline (CPL): When a processor accesses data, if the data hits in the cache, it can be read directly from the cache, while using pipeline technology to handle other tasks in parallel; if the data does not hit in the cache, it needs to be read from the main memory and stored in the cache for subsequent access. In this process, pipeline technology can help improve the efficiency of data transmission from the main memory to the cache.

[0056] Home Node (HN): is responsible for managing and storing data within a certain address range, and processing requests from other nodes. HN plays a crucial role in maintaining cache consistency and managing memory access.

[0057] Direct Cache Transfer (DCT): refers to the behavior of RN sending cache data directly to the requester in the CHI protocol, which belongs to RN-to-RN data transmission.

[0058] Load Exclusive (LE, also known as Load-Reserved or LR) is a special instruction provided in processor architectures such as RISC-V and ARMv8, used for atomic operations and memory synchronization. Load Exclusive instruction reads a value from memory and stores it in a register. Unlike ordinary read instructions, it also marks the memory address as "reserved" or "exclusive", meaning that other processors or threads should not modify the value of this memory address before the subsequent Store Exclusive instruction is executed.

[0059] Store Exclusive (SE, also known as Store-Conditional or SC) is a special instruction used together with Load Exclusive (LE) instruction, commonly found in ARMv8 (also known as AArch64) architecture and RISC-V processors, for implementing atomic operations in lock-free programming. Store Exclusive instruction attempts to store a value to a memory address previously marked as "exclusive" or "reserved" by a Load Exclusive instruction. If the memory address has not been modified by other processors or threads since the execution of the Load Exclusive instruction (i.e., still in the "exclusive" state), the Store Exclusive instruction will successfully store the value to the address and clear its "exclusive" state. If the state of the memory address has changed (i.e., no longer in the "exclusive" state), the Store Exclusive instruction will fail.

[0060] Snoop message: plays an important role in multi-processor systems, used to maintain the consistency of shared data. It informs other processors of the modification of shared data, ensuring that the cache state of each processor remains consistent, thereby improving the reliability and performance of the system. In the system design and optimization process, the delivery method, type and application scenario of the Snoop message need to be considered to achieve efficient cache consistency management.

[0061] In-order processor: also known as an ordered processor, is a processor that executes instructions in the order specified by the program.

[0062] Out-of-order processor: also known as an out-of-order processor, dynamically adjusts the execution order of instructions by detecting data dependencies and other potential conflicts between instructions to maximize processor throughput and efficiency.

[0063] Miss Status Handling Register (MSHR) is a hardware structure used to handle cache misses. The main function of MSHR is to track and manage the status of cache misses, ensuring that when data is returned from higher-level caches or main memory, these outstanding requests can be properly handled and restored.

[0064] Reference Figure 1 , shows a step flowchart of an embodiment of a cache control method of the application, which can specifically include the following steps:

[0065] Step 101, in the case of receiving a memory access request of a memory access module, record the request information of the memory access request to the memory register of the control module, and send it to the cache pipeline unit after arbitration by the arbitration unit;

[0066] Step 102, using the cache pipeline unit to query whether the memory access request hits the cache;

[0067] Step 103, in the case of the memory access request hitting the cache, execute the memory access request;

[0068] Step 104, in the case of the memory access request not hitting the cache, adjust the state of the memory register to a dormant state, and send a first request to the master node; the first request is used to obtain the cache data required by the memory access request.

[0069] The cache control method provided by the embodiment of the application can be applied to a local cache controller, and the local cache controller includes a bus interface module, a control module and a cache pipeline unit.

[0070] It should be noted that the local cache controller of the multi-core processor system based on the CHI protocol can be applied to an in-order processor. The local cache controller and the processor core constitute an RN node, which exists in a NoC system based on the CHI protocol. There is one or more HN nodes in the NoC system, the RN initiates a request to the HN, and the reading and writing back of data and the change of the cache state are realized. At the same time, the RN receives a Snoop message from the HN and responds.

[0071] Referring to Figure 2 , a schematic diagram of the architecture of the local cache controller provided by the application is shown. As Figure 2 shown, the local cache controller includes three main modules: a bus interface module, a control module, and a cache pipeline (CPL) unit.

[0072] The bus interface module is used to send and receive CHI messages, and the interaction with the HN is realized through the module. It includes six channels: 1, RXSNP, received Snoop message; 2, RXRSP: received Response message; 3, RXDAT, received Data message; 4, TXREQ, sent Request message; 5, TXDAT, sent Data message; 6, TXRSP, sent Response message. The bus interface module can be regarded as a bridge between the CHI bus interface and the MSHR, and the data transfer between the two is realized in a non-blocking manner. In addition, the module also has two functions: 1, link confidence management, realizing link handshake and activation; 2, port arbitration, when there are multiple transactions to be transmitted in a single sending channel, arbitration is performed, and the arbitration strategy adopted is fixed arbitration priority: the priority of transactions with snoop attribute is the highest, followed by exclusive access transactions, and finally normal transactions.

[0073] The control module, also called MSHR controller, is the core control module of the local cache controller, used to coordinate and complete requests from the processor and HN. In the present application, there is a series of MSHRs for storing the requests of the processor core and CHI messages, and the MSHR controller is realized by setting the contents of these MSHRs. The MSHRs in the present application can be divided into five categories: 1. Memory access register (LSU req entry), used to record the read and write requests of the processor core; 2. Monitoring register (Snp entry), used to record the snoop requests from the HN; 3. Read transaction register (Read entry), used to record the read transaction requests sent to the HN; 4. Write transaction register (Write entry), used to record the write transaction requests sent to the HN; 5. Non-data transaction register (Dataless entry), used to record the non-data transaction requests sent to the HN. Each MSHR contains multiple entries to support concurrent processing. Each MSHR stores two parts of contents: data part (request content) and control part (used for flow control). The data parts of each category of MSHRs are different, but the control parts are the same, realizing a unified control framework. The data parts of them are defined as follows:

[0074] 1. Read and write requests of the processor core, containing the following fields:

[0075] Rd_data: read data

[0076] Wr_data: write data

[0077] Addr: address of the read and write request

[0078] Wr_en: write enable with strobe function

[0079] Rd_en: read enable

[0080] Excl_flag: whether it is exclusive access

[0081] 2. Snoop requests from the HN

[0082] RxSnp: received snoop message

[0083] TxRsp: sent response message

[0084] TxDat: data for DCT

[0085] 3. Read transaction requests sent to the HN

[0086] TxReq: sent request message

[0087] RxRsp: received response message

[0088] TxRsp: sent response message

[0089] RxDat: received data message

[0090] 4. Write transaction request sent to HN

[0091] TxReq: sent request message

[0092] RxRsp: received response message

[0093] TxDat: sent data message

[0094] 5. Non-data transaction request sent to HN

[0095] TxReq: sent request message

[0096] RxRsp: received response message

[0097] TxRsp: sent response message

[0098] The MSHR control part is defined as follows:

[0099] Valid: indicates that the content of this item is valid when set (pulled high)

[0100] busy: indicates that the content of this item has been processed when set (pulled high)

[0101] done: indicates that the content of this item has been processed when set (pulled high)

[0102] The MSHR control part has strong robustness using the above Valid-busy-done control mechanism.

[0103] The cache pipeline module is a module that pipelined processes tasks from the MSHR item controller, responsible for recording and updating the state and data of the cache, and the pipeline processing improves the data access efficiency in concurrent scenarios.

[0104] It should be noted that the memory access module in the embodiment of the application can include a processor core and a next level cache (LLC) controller, and the memory access request can include a read request and a write request.

[0105] The local cache controller, upon receiving a memory access request from the memory access module, records the request information in the memory access register of the MSHR controller, at the same time, sets the MSHR control bit valid of the LSU register, and then enters the arbitration unit to wait for the CPL module to process. Once the arbitration is passed, the MSHR control bit busy is set. The arbitration unit (Arb) is used to process concurrent request messages from the memory access register, read transaction register, write transaction register, monitoring register and non-data register. The request information recorded in the memory access register can include the request address of the memory access request, the exclusive identifier, etc. The exclusive identifier is used to indicate whether it is an exclusive access. When the exclusive identifier indicates that the memory access request is an exclusive access, the Excl_flag of the data part of the memory access register can be set (for example, set to "1") or pulled high. In the case of a read request, the Rd_en of the data part of the memory access register can be set or pulled high to indicate that the request is a read request. Similarly, in the case of a write request, the Wr_en of the data part of the memory access register can be set or pulled high to indicate that the request is a write request.

[0106] The MSHR controller sends the request to the CPL unit for processing according to the arbitration priority of the request. In one possible application scenario, the priority of the memory access request from the memory access module is the lowest, that is, the priority of the request recorded in the memory access register is the lowest.

[0107] After the CPL unit receives the memory access request, it will query whether the memory access request hits the cache. If it hits, it will directly execute the memory access request. Exemplarily, if the memory access request is a read request and hits the cache, the CPL will directly return the data of the request to the memory access register and write it to the Rd_data part. If the memory access request is a write request and hits the cache, the CPL will directly write the data carried in the write request to the cache and end the request.

[0108] If the memory access request does not hit the cache, the memory access register in the MSHR controller is set to a sleep state, for example, the busy in the control part of the memory access register is set or the level is maintained high, and the done is cleared or the level is maintained low (busy is high, indicating that the transaction in the LSU register is waiting for the CPL to complete processing, so it will not initiate a new request to the arbitration unit, and done is low, indicating that the transaction in the LSU register has not completed processing). Then, a first request is initiated to the HN node to obtain the required cache data.

[0109] It can be understood that the CPL unit can query the cache according to the request address of the access request, and if the cache has the data corresponding to the request address, it can be determined that the access request hits the cache; otherwise, if the cache does not have the data corresponding to the request address, it can be determined that the access request does not hit the cache.

[0110] Of course, it can also be judged whether the access read request hits the cache according to the cache line state.

[0111] Optionally, the method further comprises:

[0112] Step S11, in the case of receiving the access request of the access module, querying the cache line state corresponding to the request address of the access request;

[0113] Step S12, in the case that the cache line state is any one of the modified state, the exclusive state and the shared state, determining that the access request hits the cache;

[0114] Step S13, in the case that the cache line state is the invalid state, determining that the access request does not hit the cache.

[0115] The cache line state in the embodiment of the application conforms to the MESI-based coherence protocol. In the MESI protocol, each cache line has four states, which are exclusive state (E), modified state (M), shared state (S) and invalid state (I).

[0116] The M state represents that the content in the cache line is modified, and the cache line is only cached in the CPU. The data in the cache line of this state is different from that in the memory, and it will be written into the memory at a future time (when other CPUs read the content of the cache line, or other CPUs modify the content of the cache line corresponding to the memory).

[0117] The E state represents that the content of the cache line corresponding to the memory is only cached by the CPU, and other CPUs do not cache the content of the cache line corresponding to the memory line. The content in the cache line of this state is consistent with that in the memory. The cache line can become an S state when any other CPU reads the content of the cache line corresponding to the memory line, or the local processor writes the cache line, and the state of the cache line will become an M state.

[0118] The S state means that the data exists not only in the local CPU cache but also in the cache of other CPUs. The data in the cache line of this state is consistent with that in the memory. When a CPU modifies the content of the cache line corresponding to the memory line, the state of the cache line will become an I state.

[0119] I state represents that the content in the cache line is invalid.

[0120] In the embodiment of the application, if the cache line state corresponding to the request address of the memory access request is any one of M, E and S, it can be determined that the memory access request hits the cache; if the cache line state is I state, it can be determined that the memory access request misses the cache.

[0121] In the case that the memory access request misses the cache, the local cache controller sets the state of the memory register to the sleep state, and sends a first request to the HN node. After receiving the first request, the HN node feeds back the cache data corresponding to the memory access request to the local cache controller. Exemplarily, if the read request misses the cache, after receiving the first request, the HN node feeds back the cache data corresponding to the request address of the read request to the local cache controller, the local cache controller writes the cache data to the Rd_data part of the memory register, and feeds back to the memory module; if the write request misses the cache, after receiving the first request, the HN node modifies the cache data corresponding to the request address of the write request to a state that can be accessed by the local cache controller, and then the local cache controller writes the data carried in the write request to the cache to replace the cache data corresponding to the request address.

[0122] The cache control method provided by the embodiment of the application cooperatively realizes the non-blocking pipeline processing of the memory access request through the bus interface module, the controller and the cache pipeline unit in the local cache controller; and in the case that the cache misses, the state of the memory register is adjusted to the sleep state, and a first request is sent to the master node, the master node processes the requests from each node, maintains the cache consistency and the memory management, so as to ensure the cache consistency in the multi-core processor system.

[0123] In an optional embodiment of the application, the memory access request comprises a memory read request; and the step of adjusting the state of the memory register to the sleep state and sending a first request to the master node in the case that the memory access request misses the cache comprises:

[0124] Step S21: in the case that the memory read request misses the cache, adjusting the state of the memory register to the sleep state, setting a read transaction register in the control module, and sending a first read request to the master node; the first read request is used to request a first target data required by the memory read request;

[0125] Step S22: after reading the first target data returned by the master node from the read transaction register, activating the memory register, and setting a first flag bit of the read transaction register; the first flag bit is used to indicate that a response message is sent.

[0126] Step S23, sending a first response message to the master node; the first response message is used to indicate that the response of the master node to the first read request is received.

[0127] The read request in the embodiment of the application can be a memory access read request, for example, a Load-Exclusive instruction. When the memory access module initiates the memory access read request, the local cache controller stores the memory access read request in a memory access register in the MSHR controller, waits for arbitration to send to the CPL unit, and the request priority of the memory access register is the lowest. The CPL queries whether the cache is hit. If the cache is missed, the memory access register in the MSHR controller enters a dormant state (for example, the busy of the memory access register control part is pulled high), and the read transaction (READ) register in the MSHR is set, ready to initiate a first read request to the master node (HNF), for example, the first read request can be a ReadNotSharedDirty request, used to request the first target data required by the memory access read request.

[0128] After the HNF receives the first read request, the first target data is returned and sent to the RxDat item in the read transaction register in the MSHR, and the RxDat item is set (that is, the valid of the RxDat item is pulled high or maintained high), and arbitration is waited to send to the CPL unit. After the CPL reads the first target data from the read transaction register and stores it in the cache, the memory access register in the MSHR is activated (for example, the busy of the memory access register control part is pulled low or maintained low), and the read request in the reactivated memory access register enters the CPL unit again. At this time, it should be a cache hit, and the CPL unit returns the read cache data to the memory access register, that is, writes the data in the Rd_data of the data part of the memory access register. Then, the TxRSP item of the read transaction register is set, and the result of the CPL analysis is written into the TxRsp item of the read transaction. The TxRSP item is used to indicate that a response message is sent, and when the TxRSP is set, the local cache controller sends a first response message, for example, a CompAck, to the HNF, to inform the master node that the response to the first read request has been received.

[0129] Optionally, in the case that the memory access request hits the cache, the memory access request is executed, comprising:

[0130] In the case that the memory access read request hits the cache, the first target data corresponding to the first request address of the memory access read request is written back to the memory access register.

[0131] In the embodiment of the present application, if the memory read request hits the cache, the CPL unit directly returns the first target data in the first request address of the memory read request to the memory register, that is, writes the data into the Rd_data in the data part of the memory register. The local cache controller returns the data in the Rd_data to the memory module at a suitable time.

[0132] Referring to Figure 3 , a flowchart of a processing procedure for a processor read request provided by an embodiment of the present application is shown. As shown in Figure 3 , after receiving the read request of the processor core, the local cache controller first sets the memory register of the MSHR, and then judges whether the request arbitration of the memory register is passed. After the request of the memory register is passed, the CPL unit is sent for processing. Specifically, the CPL unit judges the request type. If the request type is RxDat reception (that is, the RxDat item of the read transaction is sent to the RxDat item of the target data response message returned by the master node, and the RxDat item is set), the cache line data in the received RxDat item is written into the Cache. If the memory register is in a dormant state, the memory register is activated, that is, the busy bit of the control part of the memory register is pulled down or maintained low, and the activated memory register reinitiates the request to the arbitration unit. The memory register request is successfully executed by the cache pipeline, the target data is provided to the local processor, that is, written into the Rd_data in the data part of the memory register, and the processing procedure is completed.

[0133] If the request type is processor read and the Cache does not hit, the analysis result of the cache pipeline is written into the TxReq item in the read transaction register, and the TxReq item is set. The TxReq is initiated to the master node to request the master node to send the cache data. After receiving the cache data returned by the master node, that is, RxDat, the cache data is sent to the cache pipeline and saved in the local cache. At the same time, the memory register in the dormant state is activated, and the request of the activated memory register is arbitrated. After the arbitration is passed, the CPL unit is processed. At this time, it can be ensured that the Cache hits, and the CPL unit returns the read cache data to the memory register.

[0134] In another optional embodiment of the present application, the memory request includes a memory write request; and the step 103 of executing the memory request in the case that the memory request hits the cache includes:

[0135] In the case that the memory write request hits the cache, the second cache line state corresponding to the second request address of the memory write request is queried in step S31.

[0136] Step S32, if the second cache line state is the shared state, adjusting the state of the memory access register to the sleep state, setting the non-data transaction register, and sending a second request to the master node; the second request is used to adjust the second cache line state to the exclusive state.

[0137] Step S33, in the case that the second response message of the master node for the second request is received, sending a third response message to the master node; the third response message is used to indicate that the second response message is received.

[0138] Step S34, if the second cache line state is the modified state or the exclusive state, writing the second target data carried by the memory access write request back to the cache.

[0139] The write request in the embodiment of the application can be a memory access write request, for example, a Store-Exclusive instruction. When the memory access module initiates the memory access write request, the local cache controller stores the memory access write request into the memory access register in the MSHR, waits for arbitration to send to the CPL unit, and the priority of the memory access register request is the lowest. The CPL queries whether the cache is hit, if hit and the second request address of the memory access write request corresponds to the cache state (i.e. the second cache line state) is M / E, the data is directly written to the cache, and the request is ended. Otherwise, the memory access register in the MSHR enters the sleep state, if the cache state is S, the second request needs to be initiated, for example, a CleaUnique. After the master node receives the CleaUnique request, the master node sends a Snoop message-SnpCleanUnique to other cores to clear the cache line copy of other processor cores, changes the cache state to E, and returns a second response message to the local cache controller which initiates the second request, to inform that the cache state has been changed. After the local cache controller receives the second response message, the local cache controller returns a third response message to the master node to inform the master node that the second response message of the master node for the second request has been received.

[0140] Optionally, the step 104 comprises:

[0141] Step S41, in the case that the memory access write request does not hit the cache, adjusting the state of the memory access register to the sleep state, and writing the analysis result of the memory access request into the second flag bit of the read transaction register through the cache pipeline unit, setting the second flag bit, and initiating a second read request to the master node; the second read request is used to read the cache data corresponding to the second request address, and set the cache data corresponding to the second request address in other processor cores to invalid data.

[0142] Step S42, receiving the cache data returned by the master node, and replacing the cache data with the second target data carried in the memory access write request;

[0143] Step S43, setting the first flag bit of the read transaction register, and sending a fourth response message to the master node; the fourth response message is used to indicate that the response of the master node to the second read request is received.

[0144] In the embodiment of the application, if the cache is not hit, the local cache controller adjusts the state of the memory access register to the dormant state, and sends a second read request, for example, initiates ReadUnique, to the master node to obtain the cache data with the M / E state. After receiving the ReadUnique request, the master node reads the cache data corresponding to the second request address, and sets the cache data corresponding to the second request address in other processor cores to invalid data, for example, clears the cache line copy corresponding to the second request address in other processor cores. Next, the local cache controller can execute the memory access write request: replacing the current cache data of the second request address with the second target data carried in the memory access write request. At the same time, the MSHR controller sets the first flag bit TxRsp of the read transaction register, and sends a fourth response message to the master node; the fourth response message is used to indicate that the response of the master node to the second read request is received.

[0145] Specifically, in the case that the memory access write request does not hit the cache, the MSHR controller adjusts the state of the memory access register to the dormant state, and the cache pipeline writes the analysis result of the memory access register request to the second flag bit TxReq of the read transaction register, sets the TxReq, initiates a second read request to the master node; the second read request is used to read the cache data corresponding to the second request address, and set the cache data corresponding to the second request address in other processor cores to invalid data;

[0146] The MSHR controller writes the cache data returned by the master node received into the RxDat item of the corresponding read transaction register, and sets the RxDat item. The set RxDat item initiates a request to the arbitration unit. After the arbitration passes, the RxDat request enters the cache pipeline, and the received cache line data in the exclusive state is written into the local cache. After the RxDat request is successfully executed by the cache pipeline, the execution result is written into the TxRsp item in the read transaction register. At the same time, the memory register in the sleep state is activated, and the activated memory register request is arbitrated. After the arbitration passes, the CPL unit processes it. At this time, it should be a cache hit and in the exclusive state. The CPL unit replaces the second target data carried in the memory write request with the cache data, and releases the memory register, completing the memory request.

[0147] Subsequently, the TxRsp item is set. The TxRsp item is used to indicate a response message. When the TxRsp is set, the local cache controller sends a fourth response message, for example, CompAck, to the HNF, indicating that the master node has received the response to the second read request, thereby ending the read transaction and releasing the read transaction register, for example, pulling the done bit of the read transaction register high in a pulse manner.

[0148] Referring to Figure 4 , a processing flow diagram of a processor write request provided by an embodiment of the application is shown. As Figure 4 shown, after the local cache controller receives the write request of the processor core, the memory register of the MSHR is first set. Then, it is determined whether the write request arbitration passes. After the write request passes the arbitration, it is sent to the CPL unit for processing. Specifically, the CPL unit determines the request type. If the request type is CompAck (that is, the response message returned by the master node is sent to the RxRsp item of the non-data transaction, and the RxRsp item is set), the cache state is changed to the exclusive state, and the execution result of the cache pipeline on the request is written into the TxRsp item in the non-data register. If the memory register is in the sleep state, the memory register is activated, that is, the busy bit of the control part of the memory register is pulled low or maintained low. The activated memory register reinitiates a request to the arbitration unit. The memory register request is successfully executed by the cache pipeline, and the target data carried by the memory request is written into the local cache. The processing flow is completed

[0149] After the cache pipeline successfully executes the memory request, the memory register is released, and the TxRsp item in the read transaction register is set, a TxRsp, such as a CompAck, is initiated to the master node to end the CleanUnique, and the non-data transaction register of the MSHR is released.

[0150] If the request type is a memory write request and the memory register of the MSHR is in a sleep state, no processing is performed.

[0151] If the request type is a memory write request, the cache is hit, and the cache state is M / E, the data is written to the cache, and the cache line state is changed to M. At this time, the MSHR register does not need to be triggered.

[0152] If the request type is a memory write request, the cache is hit, and the cache state is S, the cache pipeline adjusts the state of the memory register to a sleep state, writes the analysis result of the memory register request to the TxReq item of the non-data transaction register, sets the TxReq item, initiates a second request to the master node, the second request is used to adjust the state of the second cache line to an exclusive state, and sets the cache data corresponding to the second request address in other processor cores to invalid data; the MSHR controller writes the response message of the second request returned by the master node into the RxRsp item of the corresponding non-data transaction register, sets the RxRsp item, and the set RxRsp item initiates a request to the arbitration unit. After the arbitration passes, the RxRsp request enters the cache pipeline, and the target cache line state of the memory request is modified to an exclusive state. After the RxRsp request is successfully executed by the cache pipeline, the execution result is written to the TxRsp item in the non-data transaction register, and the TxRsp item is set. The TxRsp item is used to indicate to send a response message. When the TxRsp is set, the local cache controller sends a first response message, such as a CompAck, to the HNF to inform the master node that the response to the second request has been received, thereby ending the transaction and releasing the non-data transaction register (pulling up the done bit of the data transaction register in a pulse manner).

[0153] If the request type is a memory write request and the cache is not hit, the MSHR read transaction register is set, a TxReq is initiated, and after the TxDat is received, it is re-judged whether the arbitration of the request is passed. After the arbitration passes, the data carried by the memory write request is written to the local cache.

[0154] In addition, the local cache controller can also receive a snoop message. When the local cache controller receives a snoop message request, the snoop message is sent into a snoop register queue, and a first-in-first-out queue is used to request to enter the CPL unit for pipelining processing. When the snoop register request is arbitrated, it is first determined whether the snoop address in the snoop register matches an item in the MSHR memory register. If the match exists, the priority of the snoop register request is set to the lowest. The snoop request can be divided into three categories: cache invalidation request, forwarding other processor core read data\instruction request, and write-back master node request.

[0155] If a cache invalidation request is received, the local cache state can be ignored, and the invalidation is directly discarded.

[0156] If a read data\instruction request of forwarding other processor core is received, if the local cache exists a copy of the address, the data is directly sent to the RN.

[0157] If a snoop request of write-back master node is received, if the local cache exists a copy of the address and the cache state is M, the data is sent back to the master node, otherwise the cache data is directly invalidated.

[0158] Optionally, the method further comprises:

[0159] Step S51, in a case where a third request sent by the master node is received, it is judged whether an address item same as a third request address of the third request exists in a memory register of the control module;

[0160] Step S52, if the address item same as the third request address exists in the memory register, a priority of the third request is set to a lowest priority, and after arbitration of an arbitration unit, the third request is sent into the cache pipelining unit;

[0161] Step S53, if the address item same as the third request address does not exist in the memory register, the priority of the third request is set to a highest priority.

[0162] It should be noted that the third request in the embodiment of the application is a snoop request.

[0163] In the embodiment of the application, the arbitration priorities of various requests can be divided into three levels. The processor request has the lowest priority, the request from the processor has the same priority, and the processor request has the highest priority after the CPL secondary activation. Multiple processor requests have the same priority after the CPL secondary activation.

[0164] The read-write request received by the local cache controller has higher priority than the processor request, and the request priority of the monitoring register is the highest. When the address of the monitoring request is equal to one of the addresses in the MSHR memory access register, the request priority of the monitoring register is set to the lowest. Until there is no matching address in the current MSHR memory access register, the priority is adjusted to the highest level again.

[0165] In conclusion, the embodiment of the present application provides a cache control method, which realizes the non-blocking pipeline processing of the memory access request through the bus interface module, the controller and the cache pipeline unit in the local cache controller. In addition, in the case of cache miss, the state of the memory access register is adjusted to the dormant state, and the first request is sent to the master node. The master node processes the requests from each node, maintains the cache consistency and the memory management, thereby ensuring the cache consistency in the multi-core processor system.

[0166] It should be noted that, for the method embodiment, in order to simply describe, it is expressed as a series of action combinations, but those skilled in the art should know that the embodiment of the present application is not limited by the described action sequence, because according to the embodiment of the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the involved actions are not necessarily required by the embodiment of the present application.

[0167] Device embodiment

[0168] Reference Figure 5 , a structure block diagram of a cache control device of the present application is shown, which is applied to a local cache controller, the local cache controller includes a bus interface module, a control module and a cache pipeline unit; the device can specifically include:

[0169] The request receiving module 501 is used for recording the request information of the memory access request into the memory access register of the control module in the case of receiving the memory access request of the memory access module, and sending the cache pipeline unit after arbitration by the arbitration unit;

[0170] The query module 502 is used for querying whether the memory access request hits the cache by using the cache pipeline unit;

[0171] The execution module 503 is used for executing the memory access request in the case of cache hit of the memory access request;

[0172] The adjustment module 504 is used for adjusting the state of the memory access register to the dormant state in the case of cache miss of the memory access request, and sending a first request to the master node; the first request is used for obtaining the cache data required by the memory access request.

[0173] Optionally, the memory access request comprises a memory access read request; and the adjusting module comprises:

[0174] a first adjusting submodule, configured to adjust a state of the memory access register to a dormant state and set a read transaction register in the control module in a case where the memory access read request misses a cache, and initiate a first read request to the master node; the first read request is used to request first target data required by the memory access read request;

[0175] a second adjusting submodule, configured to activate the memory access register and set a first flag bit of the read transaction register after reading the first target data returned by the master node from the read transaction register; the first flag bit is used to indicate sending a response message;

[0176] a first sending submodule, configured to send a first response message to the master node; the first response message is used to indicate receiving a response of the master node to the first read request.

[0177] Optionally, the executing module comprises:

[0178] a read request processing submodule, configured to write first target data corresponding to a first request address of the memory access read request back to the memory access register in a case where the memory access read request hits a cache.

[0179] Optionally, the memory access request comprises a memory access write request; and the executing module comprises:

[0180] a first querying submodule, configured to query a second cache line state corresponding to a second request address of the memory access write request in a case where the memory access write request hits a cache;

[0181] a first write request processing submodule, configured to write second target data carried by the memory access write request back to the cache if the second cache line state is a modified state or an exclusive state.

[0182] Optionally, the executing module further comprises:

[0183] a second write request processing submodule, configured to adjust a state of the core register to a dormant state and set a non-data transaction register in a case where the second cache line state is a shared state, and send a second request to the master node; the second request is used to adjust the second cache line state to an exclusive state;

[0184] a second sending submodule, configured to send a third response message to the master node in a case where a second response message of the master node to the second request is received; the third response message is used to indicate that the second response message has been received.

[0185] Optionally, the adjusting module comprises:

[0186] a third adjusting sub-module, configured to adjust the state of the memory register to a dormant state in the case that the memory write request misses the cache, and write the resolution result of the memory request into a second flag bit of a read transaction register and set the second flag bit in the read transaction register, and initiate a second read request to the master node; the second read request is used to read the cache data corresponding to the second request address, and set the cache data corresponding to the second request address in other processor cores as invalid data;

[0187] a third write request processing sub-module, configured to receive the cache data returned by the master node, and replace the cache data with the second target data carried in the memory write request;

[0188] a third sending sub-module, configured to set the first flag bit of the read transaction register and send a fourth response message to the master node; the fourth response message is used to indicate that the response of the master node to the second read request is received.

[0189] Optionally, the device further comprises:

[0190] a judging module, configured to judge whether there is an address item identical to a third request address of a third request in a memory register of the control module in the case that the third request sent by the master node is received;

[0191] a first setting module, configured to set a priority of the third request to a lowest priority if there is an address item identical to the third request address in the memory register, and send the third request to the cache pipeline unit after arbitration by an arbitration unit;

[0192] a second setting module, configured to set the priority of the third request to a highest priority if there is no address item identical to the third request address in the memory register.

[0193] In summary, the embodiment of the application provides a cache control device, which realizes non-blocking pipeline processing of a memory request through a bus interface module, a controller and a cache pipeline unit in a local cache controller; and in the case of cache miss, the state of a memory register is adjusted to a dormant state, and a first request is sent to a master node, the master node processes the requests from various nodes, and maintains cache consistency and memory management, so that cache consistency in a multi-core processor system is ensured without excessive hardware and bus overheads.

[0194] For the apparatus embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts are described in the part of the method embodiment.

[0195] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between each embodiment can be referred to each other.

[0196] For the processor in the above embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be described in detail here.

[0197] Reference Figure 6 is a structural block diagram of an electronic device for memory access provided by an embodiment of the application. As shown in Figure 6 , the electronic device includes a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions make the processor execute the cache control method of the foregoing embodiment.

[0198] The processor can be a CPU (Central Processing Unit, central processor), a general-purpose processor, a DSP (Digital Signal Processor, digital signal processor), an ASIC (Application Specific Integrated Circuit, application specific integrated circuit), an FPGA (Field Programmable Gate Array, field programmable gate array) or other programmable device, transistor logic device, hardware component or any combination thereof. The processor can also be a combination that realizes computing functions, such as one or more microprocessor combinations, combinations of DSP and microprocessor, etc.

[0199] The communication bus can include a channel for transmitting information between the memory and the communication interface. The communication bus can be a PCI (Peripheral Component Interconnect, peripheral component interconnect) bus or an EISA (Extended Industry Standard Architecture, extended industry standard architecture) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 6 only one line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0200] The memory can be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, and the like.

[0201] The embodiment of the present application also provides a non-transitory computer readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device (a server or a terminal), the processor can execute the method of controlling cache shown in the figure. Figure 1 The method of controlling cache shown in the figure.

[0202] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between each embodiment can be referred to each other.

[0203] Those skilled in the art should understand that the embodiments of the embodiment of the present application can be provided as a method, device or computer program product. Therefore, the embodiments of the present application can adopt a completely hardware embodiment, a completely software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can adopt the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0204] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams according to the method, terminal device (system) and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams can be realized by computer program instructions, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device realize the functions specified in the flowcharts and / or block diagrams. Figure 1 The device for realizing the functions specified in one flow or multiple flows and / or blocks Figure 1 The device for realizing the functions specified in one flow or multiple flows and / or blocks

[0205] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a predetennined manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the function specified in the flowchart or flowsheets and / or block or blocks. Figure 1 of the flowchart or flowsheets and / or block or blocks. Figure 1 of the flowchart or flowsheets and / or block or blocks.

[0206] These program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the function specified in the flowchart or flowsheets and / or block or blocks. Figure 1 of the flowchart or flowsheets and / or block or blocks. ​ of the flowchart or flowsheets and / or block or blocks.

[0207] While preferred embodiments of the application have been described, modifications and alterations thereto can occur to those skilled in the art upon reading the preceding description. It is intended to include all such modifications and alterations insofar as they come within the scope of the embodiments of the application. Accordingly, the following claims are intended to cover all such modifications and alterations.

[0208] Finally, it should be noted that the terms "first", "second", and the like, herein do not denote any order, quantity, combination, or importance, but rather are used to distinguish one element from another, and are not intended to denote a particular order, quantity, combination, or importance of, or between, the elements so designated. Also, the use of the terms "including", "containing", or "comprising" and variations thereof, is meant to encompass the inclusion of zero, one, or more steps, elements, or components, and is not meant to exclude or require the presence of any of these items. The use of the term "about" in conjunction with a quantity is intended to mean that the quantity is within a degree of error acceptable by one of ordinary skill in the art.

[0209] The above provides a cache control method, device, electronic equipment and readable storage medium, the principle and implementation mode of the application are described by applying specific examples in the text, and the above embodiment is only used to help understand the method and core idea of the application; meanwhile, for those skilled in the art, according to the idea of the application, the specific implementation mode and application range can be changed, and the above description of the specification should not be understood as the limitation of the application.

Claims

1. A cache control method, characterized in that, The method is applied to a local cache controller, which includes a bus interface module, a control module, and a cache pipeline unit; the method includes: Upon receiving a memory access request from the memory access module, the request information of the memory access request is recorded in the memory access register of the control module, and then sent to the cache pipeline unit after arbitration by the arbitration unit. The cache pipeline unit is used to query whether the memory access request has hit the cache; If the memory access request hits the cache, the memory access request is executed, including: If a write request hits the cache, query the status of the second cache line corresponding to the second request address of the write request. If the memory access request misses the cache, the state of the memory access register is adjusted to a sleep state, and the requesting node sends a first request to the master node; the first request is used to obtain the cached data required by the memory access request; the master node is used to manage and store data within a specific address range and process the first request from other nodes, including: If the memory access write request misses the cache, the state of the memory access register is adjusted to a sleep state, and the parsing result of the memory access request is written to the second flag bit of the read transaction register through the cache pipeline unit. The second flag bit is set, and a second read request is initiated to the master node. The second read request is used to read the cached data corresponding to the second request address and set the cached data corresponding to the second request address in other processor cores to invalid data. Receive the cached data returned by the master node, and replace the cached data with the second target data carried in the memory access write request; The first flag of the read transaction register is set, and a fourth response message is sent to the master node; the fourth response message is used to indicate that the master node's response to the second read request has been received.

2. The method according to claim 1, characterized in that, The memory access request includes a memory read request; the step of adjusting the state of the memory access register to a sleep state and sending a first request to the master node when the memory access request misses the cache includes: If the memory access read request misses the cache, the state of the memory access register is adjusted to a sleep state, and the read transaction register in the control module is set to initiate a first read request to the master node; the first read request is used to request the first target data required by the memory access read request. After reading the first target data returned by the master node from the read transaction register, the memory access register is activated, and the first flag bit of the read transaction register is set; the first flag bit is used to indicate the sending of a response message; Send a first response message to the master node; the first response message is used to indicate that the master node's response to the first read request has been received.

3. The method according to claim 2, characterized in that, When the memory access request hits the cache, executing the memory access request includes: If the memory access read request hits the cache, the first target data corresponding to the first request address of the memory access read request is written back to the memory access register.

4. The method according to claim 1, characterized in that, The memory access request includes a memory write request; the step of executing the memory access request when the memory access request hits the cache further includes: If the second cache line is in a modified or exclusive state, the second target data carried by the memory access write request is written back to the cache.

5. The method according to claim 4, characterized in that, The method further includes: If the second cache line is in a shared state, the state of the core register is adjusted to a dormant state, the non-data transaction register is set, and a second request is sent to the master node; the second request is used to adjust the state of the second cache line to an exclusive state. Upon receiving a second response message from the master node in response to the second request, a third response message is sent to the master node; the third response message is used to indicate that the second response message has been received.

6. The method according to claim 1, characterized in that, The method further includes: Upon receiving a third request from the master node, determine whether there is an address entry in the memory access register of the control module that is the same as the address of the third request. If the memory access register contains an address entry that is the same as the address of the third request, then the priority of the third request is set to the lowest priority, and it is sent to the cache pipeline unit after arbitration by the arbitration unit. If there is no address entry in the memory access register that is the same as the address of the third request, then the priority of the third request is set to the highest priority.

7. A cache control device, characterized in that, An application is made to a local cache controller, the local cache controller including a bus interface module, a control module, and a cache pipeline unit; the device includes: The request receiving module is used to record the request information of the memory access request into the memory access register of the control module when it receives the memory access request from the memory access module, and send it into the cache pipeline unit after arbitration by the arbitration unit. The query module is used to query whether the memory access request has hit the cache using the cache pipeline unit; An execution module, configured to execute the memory access request if the memory access request hits the cache, includes: If a write request hits the cache, query the status of the second cache line corresponding to the second request address of the write request. An adjustment module is used to adjust the state of the memory access register to a dormant state when the memory access request misses the cache, and to send a first request from the requesting node to the master node; the first request is used to obtain the cached data required by the memory access request; the master node is used to manage and store data within a specific address range and to process the first request from other nodes, including: If the memory access write request misses the cache, the state of the memory access register is adjusted to a sleep state, and the parsing result of the memory access request is written to the second flag bit of the read transaction register through the cache pipeline unit. The second flag bit is set, and a second read request is initiated to the master node. The second read request is used to read the cached data corresponding to the second request address and set the cached data corresponding to the second request address in other processor cores to invalid data. Receive the cached data returned by the master node, and replace the cached data with the second target data carried in the memory access write request; The first flag of the read transaction register is set, and a fourth response message is sent to the master node; the fourth response message is used to indicate that the master node's response to the second read request has been received.

8. An electronic device, characterized in that, The electronic device includes a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; The memory is used to store executable instructions that cause the processor to perform the cache control method as described in any one of claims 1 to 6.

9. A readable storage medium, characterized in that, When the instructions in the readable storage medium are executed by the processor of the electronic device, the processor is enabled to perform the cache control method as described in any one of claims 1 to 6.

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