A method for layout of analog integrated circuit macro modules supporting polygons

Abstract

The application discloses a method for supporting polygon simulation integrated circuit macro module layout, which comprises the following steps: 1) dividing macro modules; 2) assigning corresponding weights to the macro modules according to the number of connections and the area of each macro module, and sorting the macro modules according to the weights; 3) selecting the macro modules in sequence, and adopting a polygon edge search layout algorithm to perform layout; 4) disturbing the macro module sorting, performing layout according to the new macro module sorting, comparing the scores of the current layout and the previous layout, retaining the optimal layout result and outputting. The polygon edge search layout algorithm is adopted, and it is specified that the newly added module must be placed close to the original module, the module is expanded to reserve the wiring space between the modules, the layout of the polygon simulation circuit macro module is supported, and the layout compactness is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation (EDA) integrated circuit layout, and in particular to an optimization method for analog integrated circuit macromodule layout. Background Art

[0002] A large-scale analog circuit, such as an analog-to-digital converter (ADC), a low-dropout linear regulator (LDO), or a phase-locked loop (PLL), often consists of multiple functional modules. These modules are divided into specific layers according to their function, with each functional circuit being implemented separately. Examples include a reference power supply module, an amplifier module, a capacitor sampling module, and a digital logic module. Therefore, the high-level layout of analog circuits involves not processing constrained devices but rather circuit modules that can be viewed as macromodules.

[0003] Due to the various constraints of the underlying circuit, the placement of its internal devices often cannot form a rectangle. In order to save the area of ​​the total layout, when extracting the shape of the macro module, the polygon boundary is extracted for the upper-level layout, which is more conducive to improving the area utilization of the chip and thus saving production costs.

[0004] Existing methods for analog circuit macromodule layout can generally be divided into two categories: absolute coordinate representation and topological representation. Absolute coordinate representation typically employs nonlinear optimization to solve the layout, making it easy to express multiple constraints and optimization objectives. However, in pursuit of comprehensive performance, the resulting layout solutions may not be compact enough to meet industrial-grade requirements, and the presence of polygonal modules further complicates the representation and solution of the problem.

[0005] Topological representations construct specific data structures to represent the actual layout, often combined with heuristic algorithms for optimization to ensure a compact layout. However, some topological structures offer limited freedom in the placement of modules. Furthermore, as circuit size increases, the dimensionality of the heuristic algorithm's solution space also increases, resulting in higher computational costs for obtaining a satisfactory solution. Furthermore, when dealing with polygons, topological representations tend to decompose them into rectangles. Therefore, they are primarily suitable for simple polygonal modules, such as L- or T-shaped ones, but not for complex ones. Summary of the Invention

[0006] In order to solve the defects of the prior art, the purpose of the present invention is to provide a polygon-supporting analog integrated circuit macro module layout method, which supports polygon-supporting analog circuit macro module layout and ensures layout compactness.

[0007] To achieve the above-mentioned object, the present invention provides a polygon-supporting analog integrated circuit macromodule layout method, comprising:

[0008] 1) Divide macro modules;

[0009] 2) assigning corresponding weights to each macromodule according to the number of connections and area of ​​each macromodule, and sorting the macromodules according to the weights;

[0010] 3) Select macro modules in order and use polygon edge search layout algorithm for layout;

[0011] 4) Perturb the macromodule order and perform layout according to the new macromodule order, compare the scores of this layout with the previous layout, retain the optimal layout result and output it.

[0012] Furthermore, the polygon edge search layout algorithm includes: placing modules from the center outward in sorted order, extracting the common outer contour of the placed modules during the placement process, combining all the laid-out modules into a whole polygon, and performing an edge search outside the combined polygon based on the edge type of the next module to be placed to determine the possible placement position of the module to be placed;

[0013] The score of each macro module placement position is calculated according to the evaluation criteria, and the position with the best score is selected as the final placement position of the current macro module in this layout.

[0014] Furthermore, the step of extracting the common outer contour of the modules placed together further includes: detecting the gaps between the modules, and if the width of the gaps is smaller than a preset minimum size, filling the gaps to simplify the polygonal boundaries and reduce the search space when placing the next module.

[0015] Furthermore, the step of performing an edge search outside the synthesized polygon according to the type of the edge of the next module to be placed to determine the possible placement position of the module to be placed further includes:

[0016] The direction of the polygon's edges is specified as clockwise or counterclockwise, and the edges are divided into four types according to their direction;

[0017] Enumerate all possible placements of the next module to be placed based on edge type classification: If the number of edges of type k (k = 1, 2, 3, 4) in the polygon of the already laid out modules is m, and the number of edges of type f(k) in the next module to be placed is n, the total number of searches required is 2mn; assuming the number of edges of all types is the same, the total number of searches is Where M is the total number of sides of the overall polygon, N is the total number of sides of the modules to be placed, and the expression of f(k) is as follows:

[0018]

[0019] Based on the current placement position, check whether there is overlap after the modules are placed. If so, discard the placement position.

[0020] Furthermore, the step of calculating the score of the placement position of each macromodule according to the evaluation criteria further includes: the evaluation criteria including: the total connection length, area utilization and signal flow order of the current layout;

[0021] Based on the currently searched placement position, the weighted sum of each evaluation criterion is calculated as the score of the current placement position.

[0022] Furthermore, the method further includes: for each newly added macro module, selecting a pin with the shortest Manhattan distance to the pins of the newly added macro module from all laid out macro modules, and calculating the shortest distance between the two pins.

[0023] Furthermore, it also includes: filling the depressions on the polygonal boundary of the laid out macromodules synthesized into a whole, converting the polygon into a convex polygon, calculating the area utilization within the convex polygon boundary and the area utilization within the rectangular boundary, and assigning corresponding weights to the area utilization within the two boundaries, which are jointly used to measure the total area utilization.

[0024] Furthermore, the method further includes: in a macro module composed entirely of MOS transistors, extracting the signal flow sequence in the macro module according to the current direction, obtaining the type of the IO pin of the macro module, and determining the type of the IO pin of the macro module connected thereto;

[0025] If the inflow pin of a MOS is not connected to the outflow pin of any MOS in the same macromodule, the inflow pin can be regarded as the input pin of the entire macromodule, and the signal flow sequence in the entire macromodule can be analyzed based on this pin.

[0026] If there is a signal flow relationship between two MOSs, and there is a drain-to-source or drain-to-drain connection, and it is also connected to an IO pin, it can be regarded as a special output. Once this output is connected to the gate of a MOS in another macro module, it constitutes a signal flow sequence;

[0027] After obtaining the signal flow of the macro module, if the output pin of a macro module is connected to an unknown pin, it can be determined that the unknown pin is an input pin. The signal flow sequence of each layer layout is generated into a directed graph. If there is a feedback loop, the edges connected to the output pin can be used as loop-breaking points to generate a directed acyclic graph to guide the macro module layout.

[0028] Furthermore, it also includes: randomly exchanging any two modules, or using simulated annealing or machine learning methods to perturb the initial macro module sequence and generate a new macro module sequence.

[0029] To achieve the above-mentioned purpose, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein the processor is configured to execute the computer program stored in the memory to implement the above-mentioned polygon-supporting analog integrated circuit macro module layout method.

[0030] To achieve the above objectives, the present invention further provides a computer-readable storage medium, wherein the storage medium stores at least one instruction, which is loaded and executed by a processor to implement the above-mentioned polygon-supporting analog integrated circuit macro module layout method.

[0031] The polygon-supporting analog integrated circuit macromodule layout method provided by the present invention has the following beneficial effects compared with the prior art:

[0032] A polygonal edge-fitting search layout algorithm is used to layout macro modules in the order of module sorting. The polygonal edge-fitting search layout algorithm stipulates that newly added modules must be placed close to the original modules. Through module expansion, wiring space between modules can be reserved, ensuring that all placed modules are clustered together during the layout stage. It supports polygonal analog circuit macro module layout and improves layout compactness.

[0033] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0035] Figure 1 A flow chart of a polygon-supporting analog integrated circuit macro module layout method according to an embodiment of the present invention;

[0036] Figure 2 A schematic diagram of sequentially arranging macro modules according to an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of a polygon for dividing edge types according to an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of the placement position of each edge according to an embodiment of the present invention;

[0039] Figure 5 Schematic diagram of two placement schemes of the same macro module according to an embodiment of the present invention;

[0040] Figure 6A schematic diagram of a signal flow sequence according to an embodiment of the present invention;

[0041] Figure 7 FIG. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0043] Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0044] As used herein, the term "including" and its variations are open-ended, i.e., "including but not limited to." The term "based on" means "based, at least in part, on." The term "one embodiment" means "at least one embodiment," the term "another embodiment" means "at least one additional embodiment," and the term "some embodiments" means "at least some embodiments." Other terms are defined in the following description.

[0045] It should be noted that the concepts of "first" and "second" may be mentioned in the present invention only to distinguish different devices, components or parts, and are not used to limit the order or interdependence of the functions performed by these devices, components or parts.

[0046] It should be noted that the modifications of "one" and "plurality" mentioned in the present invention are illustrative and non-restrictive. Those skilled in the art will understand that unless the context clearly indicates otherwise, they should be understood as "one or more". "Plurality" should be understood as two or more.

[0047] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0048] Figure 1 The following is a flow chart of a method for placing a polygon-supported analog integrated circuit macro module according to an embodiment of the present invention. Figure 1 The polygon-supporting analog integrated circuit macromodule layout method of the present invention is described in detail.

[0049] In step 101, the macro modules are divided. According to the input constraint type, the bottom layer devices are divided into constraint groups. The constraint groups can be nested in multiple layers. The topmost constraint group is the macro module.

[0050] The constraint types include: common centroid constraint, symmetry constraint, and proximity constraint, etc.

[0051] In step 102, an initial macroblock ranking is generated based on the number and area of ​​connections of each macroblock.

[0052] In the embodiment of the present invention, each time a macromodule ordering scheme is generated, a corresponding layout is performed, and each layout selects modules in a given order. This process is repeated multiple times until the termination condition is reached. Before the loop begins, an initial macromodule ordering needs to be generated.

[0053] During layout, since each newly added module sticks to the outside edge of an existing module, modules tend to be placed sequentially from the center outward. To reduce the total length of connections and ease the difficulty of connecting modules, one layout idea is to place modules with a large number of connections in the center and modules with a small number of connections around the perimeter based on their connection structure. Therefore, the first idea is to generate an initial module order based on the number of connections.

[0054] Figure 2 FIG. 1 is a schematic diagram of placing macro modules in sequence according to an embodiment of the present invention, as shown in FIG. Figure 2 As shown, since the macro modules with larger areas often have the greatest impact on the total area, if the macro modules are placed in order and macro module 5 is placed last, the total size of the previously placed macro modules after merging may not be compatible with the size of the newly added macro module, resulting in a problem of area waste.

[0055] Taking the above two points into consideration, the initial macromodule sorting should take into account both the number of connections and the area. The macromodules should be assigned corresponding weights based on the number of connections and the area of ​​each macromodule. The macromodules should be sorted from large to small or from small to large according to the weights, thereby generating a better initial solution.

[0056] In embodiments of the present invention, after generating an initial macroblock sequence, the macroblock sequence can be randomly perturbed to more comprehensively search for a possible optimal solution, and the resulting layout can then be observed. This random perturbation can involve randomly swapping any two macroblocks, or using methods such as simulated annealing or machine learning to generate a new macroblock sequence.

[0057] In step 103, macro modules are selected in sequence and are laid out using a polygon edge-matching search layout algorithm.

[0058] The polygon edge-matching search layout algorithm includes: placing modules from the center outward in sorted order, extracting the common outer contour of the placed modules during the placement process, merging all the laid-out modules into a whole polygon, and performing an edge-matching search outside the merged polygon based on the type of the edge of the module to be placed to determine the optimal placement position of the module to be placed.

[0059] In an embodiment of the present invention, in order to avoid the movement of a large number of modules, the polygons that have been placed remain in the same position. In order to ensure the compactness of the modules and to compress the search space corresponding to the newly added modules, it can be stipulated that an added module must be placed close to the original module. Through module expansion, wiring space between modules can be reserved, ensuring that all placed modules are gathered together during the layout stage.

[0060] In step 1031, the modules are placed from the center outward in the sorting order, and the available placement positions of the macro modules to be placed are searched along the edges.

[0061] Extracting the common outline of placed modules involves merging all laid-out modules into a single polygon. This polygon can be complex and contain narrow gaps. These gaps are detected, and if they are smaller than the minimum size that no module can fit into, they are filled. This simplifies the polygon boundary and reduces the search space for the next module to be placed.

[0062] In an embodiment of the present invention, positions where new modules can be placed are divided according to the type of edges. Based on the type of edges of the new modules (i.e., the modules to be laid out), positions where new modules can be placed are searched on the edges of the merged overall polygons.

[0063] Figure 3 Schematic diagram of polygons dividing edge types according to an embodiment of the present invention, such as Figure 3 As shown in Figure 2, given a module sequence, the already placed modules will be merged into an overall polygon α, where each edge of α has an area that allows the next module β to be placed outward. At this point, the final placement of β can be determined by searching all these edges and greedily selecting the best position from them.

[0064] Figure 4 Schematic diagram of the placement position of each edge according to an embodiment of the present invention. Figure 3 and Figure 4 As shown in the figure, the direction of the polygon's edges is specified in a counterclockwise direction, and the edges are divided into four types according to the direction: left, right, upward, and downward. According to the inherent characteristics of polygons, when two polygons are adjacent, the adjacent edges must be parallel and opposite. For example, in Figure 3In the example, only edges d and e are allowed to be adjacent to edge a, and the same applies to edges b and c. When placing the current module, the remaining space is kept intact to facilitate the placement of new modules. Therefore, when a module is placed next to an edge, it is preferred to align it with both ends of the edge (e.g. Figure 4 (a) in the figure), rather than being placed somewhere in the middle (as shown in the figure). Figure 4 (b) in the figure), as shown in Figure 4 As shown, this will not affect the current total area.

[0065] Therefore, for each edge, only two layout methods are considered, where both sides of the edge are aligned. All possible placements of the module β are enumerated according to the edge type. If there are m edges of type k (k = 1, 2, 3, 4) in the overall polygon α, and n edges of type f(k) in the module β to be laid out, the total number of searches required is 2 × m × n. Assuming that the number of edges of all types is the same, the total number of searches can be estimated to be Where M is the total number of edges of the overall polygon α, N is the total number of edges of the module β to be laid out, and the expression of f(k) is as follows:

[0066]

[0067] In an embodiment of the present invention, during the layout process, due to the limitations of signal flow within each module, the modules cannot be rotated arbitrarily. However, for some special modules, such as capacitors and resistors, which may have large size and aspect ratio differences, different rotation angles will have a significant impact on the connection length and area. In addition, there are no internal signal flow limitations. Therefore, four rotation directions can be supported: 0° (no rotation), 90°, 180°, and 270°. These modules will additionally search for different rotation angles at each position and compare the advantages and disadvantages of the placement positions at different rotation angles.

[0068] In step 1032, the score of each placement position is calculated, and the position with the best score is selected as the final placement position of the current module in this layout.

[0069] In an embodiment of the present invention, each placement position of the current macromodule found is scored according to evaluation criteria, including the total wire length, area utilization, and signal flow order of the current layout. The impact of the current macromodule placement position on the total wire length, area, and signal flow order of the layout composed of all currently placed macromodules can be comprehensively considered, and the weighted sum of these objectives is calculated as the score for the current placement position. Wire length is measured based on the half-perimeter length (HPWL), and compactness is measured based on area utilization. Furthermore, if overlap between macromodules is detected, the placement position is immediately discarded.

[0070] Calculate the length of the connection:

[0071] During each layout process, the positions of the already placed macro modules are fixed and will not change. Therefore, we only need to consider the connection relationship between the newly added macro modules to be placed and each already placed macro module, without having to recalculate the connection lengths between all the already placed macro modules.

[0072] When actually connecting wires, to minimize overall wire length, a pin is connected to an existing wire using the shortest path principle. However, solving the shortest path problem each time when estimating wire length is time-consuming. Therefore, when calculating HPWL, for each pin on a newly added macro module, the pin with the closest Manhattan distance to that pin is selected from all existing macro modules connected to it, and this distance is calculated.

[0073] Figure 5 Schematic diagram of two placement schemes for the same macro module according to an embodiment of the present invention, such as Figure 5 As shown, macro modules a and b have been placed, and a new macro module c has been added. The dark blocks in each macro module represent the pins of the macro module. Two placement schemes are considered: the first scheme places c above a, and the nearest pin is the pin on the left of a; the second scheme places c below b, and the nearest pin is the pin of b. According to the strategy proposed by the present invention, the line length scores of the two schemes are the same, and in the actual layout, the connection situation is consistent with the estimate. However, if the distance between all interconnected pins is calculated, the total HPWL length of the first scheme is less than the total HPWL length of the second scheme, which is inconsistent with the actual situation. Compared with calculating the distance from all connected pins to the newly added pin, the method of the present invention can more accurately estimate the actual wiring requirements without solving the shortest path problem.

[0074] Calculate area utilization:

[0075] Area utilization is the ratio of the total area of ​​all macroblocks to the area within their boundaries. For non-top-level circuits, extracting their boundaries as polygons rather than rectangles helps save area for upper-level circuits. To facilitate upper-level utilization, polygon boundaries should be as straight as possible, minimizing concavities. Therefore, when measuring area utilization, we first fill in the concavities on the polygon boundaries, converting them into convex polygons. We then calculate the area utilization within the convex polygon boundaries and the area utilization within the rectangular boundaries. We assign corresponding weights to the area utilization within these two boundaries and use them together to measure the overall area utilization.

[0076] Extract signal flow order:

[0077] Inspired by the schematic diagram, pin types are divided into input, output, and unknown. Within a macromodule composed entirely of MOS transistors, the direction of signal flow should be determined based on the direction of current flow. The signal flow sequence within the macromodule is extracted based on the current direction to obtain the type of the macromodule's IO pin, and then the IO pin type of the connected macromodule is determined. Specifically, if the inflow pin of a MOS within a macromodule is not connected to the outflow pin of any MOS within the same macromodule, this pin can be considered the input pin of the entire macromodule. Using this as the source point, the signal flow sequence within the entire macromodule can be analyzed. A macromodule can have multiple source points. In addition, if there is a signal flow relationship between two MOS transistors, and there is a drain-to-source or drain-to-drain connection, and this line is also connected to an IO pin, it can be considered a special output. Once connected to the gate of a MOS in another macromodule, the signal flow sequence can be established.

[0078] After obtaining the signal flow of a macromodule, if a macromodule output pin is connected to an unknown pin, it can be determined that the unknown pin is an input pin. The signal flow of each layer is sequentially generated into a directed graph. If feedback loops exist, the edges connected to the output pins are used as loop break points to ensure the generation of a directed acyclic graph, which is used to guide the macromodule layout.

[0079] Figure 6 Schematic diagram of signal flow sequence according to an embodiment of the present invention. Figure 6 As shown, first find the pin where the current flows into. Taking PMOS as an example, if its drain is not connected to the source of any other PMOS, then this pin can be regarded as the input pin of the macro module. This MOS tube is the starting MOS tube of the signal flow, as shown in the figure. Figure 6 The current flows from the drain of PM0 and out of the source. Find all PMOSs whose drain is connected to the source of PM0, such as Figure 6 Then, in the same way, we search for the sources of PM1 and PM2, and finally form two signal flows: PM0->PM1 and PM0->PM2.

[0080] In addition to the longitudinal signal flow consistent with the direction of current, there is also a lateral signal flow between different current paths. If the source and drain of two transistors are connected, such as PM0 and PM1, if the line connecting the two is connected to the gate of the other transistor, it can be regarded as an output, and the corresponding gate is regarded as an input.

[0081] In the embodiments of the present invention, after extracting the signal flow within the underlying module, the corresponding IO pin types of the underlying module can be obtained to guide the upper-layer layout. Based on the obtained IO pin types, unknown pins can be supplemented. In analog circuits, if one pin on a line is typed as an output, the other pins must be typed as inputs.

[0082] At this point, a directed graph can be constructed with macromodules as nodes and signal flow directions as edges. This directly describes the signal flow relationships within the circuit layer and serves as a guide for layout. It's important to note that when feedback elements are present in the circuit, loops can be created in the signal path graph. In this case, edges from the nodes belonging to the output pins of the circuit layer can be used as locations to break the loop, converting the directed graph with cycles into an acyclic graph.

[0083] In an embodiment of the present invention, if there is a pointing relationship between two macromodules in a directed graph, for example, macromodule A points to macromodule B, then the maximum coordinate of A in the x-direction shall not be greater than the maximum coordinate of B in the x-direction, and the minimum coordinate of A in the y-direction shall not be smaller than the minimum coordinate of B in the y-direction.

[0084] In step 104, the scores of the current layout and the previous layout are compared, and the optimal layout result is retained.

[0085] In an embodiment of the present invention, the total connection length, area utilization, and signal flow order of this layout are comprehensively considered, and the weighted sum of these three objectives is calculated as the score of this layout.

[0086] In step 105, it is determined whether the optimal layout result meets the preset termination condition. If so, the layout result is output; otherwise, the order of the two macro modules is randomly swapped, and steps 103 to 105 are repeated.

[0087] The polygon-supporting analog integrated circuit macromodule layout method provided by the present invention has the following advantages:

[0088] (1) A polygonal edge search method is used to generate macromodule layouts. It is stipulated that a newly added macromodule must be placed close to the original macromodule. Through module expansion, wiring space between modules can be reserved, ensuring that all placed macromodules are clustered together during the layout phase.

[0089] (2) All the laid-out macroblocks are merged into a single polygon. Its outline can be a very complex shape with narrow gaps. These gaps are detected. If the width is smaller than the minimum size so that no macroblock can fit into the gap, the gap is filled to simplify the polygon boundary, thereby reducing the search space for the next macroblock to be placed.

[0090] (3) The direction of the polygon's sides is specified as clockwise or counterclockwise, and the sides are divided into four types according to their direction; according to the inherent characteristics of polygons, when two polygons are adjacent, the adjacent sides must be parallel and opposite;

[0091] (4) A method for estimating the wiring length between pins is used to calculate the distance between the pin on the newly added macro module and the nearest pin on the already connected macro module. The wiring length is estimated more accurately while ensuring time efficiency, which is used to evaluate the macro module layout.

[0092] (5) A method for evaluating area utilization is adopted. Area utilization is the ratio of the total area of ​​all macro modules to the area within the boundary. For non-top-level circuits, the area utilization within polygonal boundaries and rectangular boundaries is measured at the same time. Polygonal boundaries are beneficial to saving the area of ​​upper-level circuits.

[0093] (6) A method for extracting the signal flow sequence is proposed. Starting from a macro module composed entirely of MOS tubes, the signal flow sequence within the macro module is extracted according to the current direction, thereby obtaining the type of the macro module IO pin, and then determining the IO pin type of the macro module connected to it; after obtaining the signal flow of the macro module, if the output pin of a macro module is connected to an unknown pin, it can be determined that the unknown pin is an input pin; the signal flow sequence of each layer layout is generated into a directed graph. If there is a feedback loop, the edge connected to the output pin can be used as a loop removal point to ensure the generation of a directed acyclic graph to guide the macro module layout.

[0094] In an embodiment of the present invention, an electronic device is further provided. Figure 7 FIG. 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Figure 7 As shown, the electronic device of the present invention includes a processor 701 and a memory 702, wherein:

[0095] The memory 702 stores a computer program. When the computer program is read and executed by the processor 701 , the computer program executes the steps in the embodiment of the polygon-supporting analog integrated circuit macro module layout method.

[0096] In an embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the steps in the embodiment of the polygon-supporting analog integrated circuit macro module layout method described above when running.

[0097] In this embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0098] Those skilled in the art will understand that the foregoing descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will be able to modify the technical solutions described in the foregoing embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A polygon-supporting analog integrated circuit macromodule layout method, characterized in that: include: 1) Divide macro modules; 2) assigning corresponding weights to each macromodule according to the number of connections and area of ​​each macromodule, and sorting the macromodules according to the weights; 3) Select macro modules in order and use polygon edge search layout algorithm for layout; 4) Perturb the macromodule order and perform layout based on the new macromodule order, compare the scores of this layout with the previous layout, retain the optimal layout result and output it; The polygon edge search layout algorithm includes: placing modules from the center outward in sorted order, extracting the common outer contour of the placed modules during the placement process, combining all the placed modules into a whole polygon, and performing an edge search outside the combined polygon based on the edge type of the next module to be placed to determine the possible placement position of the module to be placed; The score of each macro module placement position is calculated according to the evaluation criteria, and the position with the best score is selected as the final placement position of the current macro module in this layout.

2. The polygon-supporting analog integrated circuit macromodule layout method according to claim 1, wherein: The step of extracting the common outer contour of the modules placed together further includes: detecting the gaps between the modules, and if the width of the gaps is less than a preset minimum size, filling the gaps to simplify the polygonal boundaries and reduce the search space when placing the next module.

3. The polygon-supporting analog integrated circuit macromodule layout method according to claim 1, wherein: The step of performing an edge search outside the synthesized polygon according to the type of the edge of the next module to be placed to determine the possible placement position of the module to be placed further includes: The direction of the polygon's edges is specified as clockwise or counterclockwise, and the edges are divided into four types according to their direction; Enumerate all possible placements of the next module to be placed based on edge type classification: If the polygon of the already laid out modules is composed of m edges of type k (k=1,2,3,4), and the next module to be placed has n edges of type f(k), the total number of searches required is 2mn; assuming the number of edges of all types is the same, the total number of searches is , where M is the total number of sides of the overall polygon, N is the total number of sides of the modules to be placed, and the expression of f(k) is as follows, ； Based on the current placement position, check whether there is overlap after the modules are placed. If so, discard the placement position.

4. The polygon-supporting analog integrated circuit macromodule layout method according to claim 1, wherein: The step of calculating the score of the placement position of each macromodule according to the evaluation criteria further includes: the evaluation criteria including: the total connection length, area utilization and signal flow order of the current layout; Based on the currently searched placement position, the weighted sum of each evaluation criterion is calculated as the score of the current placement position.

5. The polygon-supporting analog integrated circuit macromodule layout method according to claim 4, wherein: The method further includes: for each newly added macromodule, selecting a pin having the shortest Manhattan distance to the pins of the newly added macromodule from all laid out macromodules, and calculating the shortest distance between the two pins.

6. The polygon-supporting analog integrated circuit macromodule layout method according to claim 4, wherein: Also includes: Fill in the depressions on the polygonal boundary of the laid-out macromodules, convert the polygon into a convex polygon, calculate the area utilization within the convex polygon boundary and the area utilization within the rectangular boundary, assign corresponding weights to the area utilization within the two boundaries, and use them together to measure the total area utilization.

7. The polygon-supporting analog integrated circuit macromodule layout method according to claim 4, wherein: Also includes: In a macromodule composed entirely of MOS transistors, extract the signal flow sequence within the macromodule according to the current direction, obtain the type of the macromodule IO pin, and determine the IO pin type of the connected macromodule: If the inflow pin of a MOS is not connected to the outflow pin of any MOS in the same macromodule, the inflow pin can be regarded as the input pin of the entire macromodule to analyze the signal flow sequence in the entire macromodule; If there is a signal flow relationship between two MOSs, and there is a drain-to-source or drain-to-drain connection, and it is also connected to an IO pin, it can be regarded as a special output. Once this output is connected to the gate of a MOS in another macro module, it constitutes a signal flow sequence; After obtaining the signal flow of the macro module, if the output pin of a macro module is connected to an unknown pin, it can be determined that the unknown pin is an input pin. The signal flow sequence of each layer layout is generated into a directed graph. If there is a feedback loop, the edges connected to the output pin can be used as loop-breaking points to generate a directed acyclic graph to guide the macro module layout.

8. The polygon-supporting analog integrated circuit macromodule layout method according to claim 1, wherein: Also includes: By randomly exchanging any two macromodules, or using simulated annealing or machine learning methods, the initial macromodule order is disturbed to generate a new macromodule order.

9. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, which is loaded and executed by the processor to implement the polygon-supporting analog integrated circuit macro module layout method according to any one of claims 1 to 7.

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