A semiconductor device and a method of fabricating the same

Abstract

The present application provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a semiconductor layer, the semiconductor layer having a source / drain contact region; forming an initial contact layer on the semiconductor layer, the initial contact layer being connected with the source / drain contact region; forming a source / drain contact metal on the initial contact layer and performing annealing so that metal elements in the source / drain contact metal diffuse into a portion of the initial contact layer under the source / drain contact metal to obtain an auxiliary contact layer. The manufacturing method additionally forms the auxiliary contact layer to improve the contact characteristics between the source / drain contact metal and the semiconductor layer, reduces the contact resistance and improves the working performance of the device. The device has the auxiliary contact layer under the source / drain contact metal, the contact characteristics between the source / drain contact metal and the contact region of the device are improved, and the on-current characteristics, stability and reliability of the device are effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit devices and fabrication technology, and relates to a semiconductor device and its fabrication method. Background Technology

[0002] A High Electron Mobility Transistor (HEMT) is a microelectronic device that typically has a heterostructure layer composed of two semiconductor materials with different band gaps. The material with the smaller band gap (e.g., GaN or GaAs) serves as the channel layer, while the material with the larger band gap serves as the barrier layer (e.g., AlGaN or AlGaAs). At the interface of the heterostructure, a high-density electron accumulation layer (i.e., a two-dimensional electron gas, also known as 2DEG) is formed due to the discontinuity of the valence band. Furthermore, the electric field built based on the barrier layer confines the 2DEG within the channel layer, utilizing the high electron mobility of the 2DEG to achieve high-speed, high-frequency, and high-power applications. Based on this, HEMTs are widely used in power amplifiers, wireless communication, radar systems, and satellite communication.

[0003] Currently, HEMT devices employ relatively thick barrier layers. A thicker barrier layer disperses the electric field, reducing field concentration and thus improving breakdown voltage. Simultaneously, a thicker barrier layer reduces the adverse effects of interface states and traps at the channel-gate interface on device performance, mitigating current collapse. It also optimizes transfer and output characteristics. However, increasing the barrier layer thickness can alter the electric field distribution and weaken gate control, leading to reduced resistance concentration in the source / drain regions or decreased injection efficiency at the source / drain contacts. This indirectly results in an undesirable increase in source / drain contact resistance, impacting device performance and long-term reliability. For example, please refer to [link to relevant documentation]. Figure 1 The diagram shows a cross-sectional view of a HEMT device. When the thickness of the barrier layer 101 is relatively large, it leads to a larger contact resistance (i.e., Figure 1 The resistance R1 between the drain contact metal 102 and the area of ​​the barrier layer 101 and the channel layer 103 below it is a problem. If the barrier layer 101 is etched, it will cause a loss of 2DEG concentration, which will reduce the resistance between the barrier layer 101 and the channel layer 103. Figure 1 An increase in R2 (as shown in the figure) affects the device's performance.

[0004] Therefore, how to provide a semiconductor device and its fabrication method to improve the source-drain contact resistance characteristics and reliability of the device has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application and facilitating the understanding of those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art only because it is described in the part of the background of the present application. SUMMARY

[0006] In view of the above-mentioned defects of the prior art, the purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, which are used to solve the problem that the device contact characteristics need to be improved due to the design of a thicker barrier layer for improving the breakdown characteristics of the HEMT device in the prior art.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a manufacturing method of a semiconductor device, comprising the following steps:

[0008] providing a semiconductor layer, wherein the semiconductor layer has a source contact region and a drain contact region;

[0009] forming an initial contact layer on the semiconductor layer, wherein the initial contact layer is also connected with the source contact region and the drain contact region;

[0010] forming a source contact metal and a drain contact metal on the initial contact layer, and performing annealing to make the metal elements in the source contact metal and the drain contact metal diffuse into the part of the initial contact layer below the source contact metal and the drain contact metal to obtain an auxiliary contact layer.

[0011] Optionally, the material of the initial contact layer comprises aluminum nitride.

[0012] Optionally, the thickness of the initial contact layer is less than or equal to 5 nm, and the method for forming the initial contact layer comprises at least one of an atomic layer deposition method and a chemical vapor deposition method.

[0013] Optionally, the semiconductor layer comprises a substrate, a channel layer and a barrier layer stacked from bottom to top, and the side of the channel layer facing the barrier layer has a two-dimensional electron gas.

[0014] Optionally, the source contact metal is connected with the side of the barrier layer away from the channel layer, or the source contact metal at least extends into the barrier layer, or the source contact metal penetrates through the barrier layer and extends into the channel layer; and / or, the drain contact metal is connected with the side of the barrier layer away from the channel layer, or the drain contact metal at least extends into the barrier layer, or the drain contact metal penetrates through the barrier layer and extends into the channel layer.

[0015] Optionally, the method comprises the following steps:

[0016] forming a first dielectric layer over the semiconductor layer and patterning the first dielectric layer to form a source contact hole and a drain contact hole, the source contact hole exposing the source contact region, the drain contact hole exposing the drain contact region;

[0017] forming a contact metal layer over the first dielectric layer, the contact metal layer also filling into the source contact hole and the drain contact hole;

[0018] patterning the contact metal layer to obtain the source contact metal and the drain contact metal.

[0019] Optionally, a width of a portion of the source contact metal outside the source contact hole is greater than a width of a portion of the source contact metal in the source contact hole, and / or a width of a portion of the drain contact metal outside the drain contact hole is greater than a width of a portion of the drain contact metal in the drain contact hole.

[0020] The application also provides a semiconductor device, comprising:

[0021] a semiconductor layer having a source contact region and a drain contact region;

[0022] an auxiliary contact layer on the semiconductor layer, the auxiliary contact layer being connected to the source contact region and the drain contact region;

[0023] a source contact metal and a drain contact metal on the auxiliary contact layer, the auxiliary contact layer containing a metal element diffused from the source contact metal and the drain contact metal.

[0024] Optionally, a material of the auxiliary contact layer comprises aluminum nitride.

[0025] Optionally, a thickness of the auxiliary contact layer is less than or equal to 5 nm, and a forming method of the auxiliary contact layer comprises at least one of atomic layer deposition and chemical vapor deposition.

[0026] Optionally, the semiconductor layer comprises, from bottom to top, a substrate, a channel layer, and a barrier layer, a side of the channel layer facing the barrier layer having a two-dimensional electron gas.

[0027] Optionally, the source contact metal is connected to a side of the barrier layer facing away from the channel layer, or the source contact metal extends at least into the barrier layer, or the source contact metal extends through the barrier layer and into the channel layer; and / or, the drain contact metal is connected to a side of the barrier layer facing away from the channel layer, or the drain contact metal extends at least into the barrier layer, or the drain contact metal extends through the barrier layer and into the channel layer.

[0028] As described above, the semiconductor device manufacturing method of the present application, by making an initial contact layer on the surface of the source / drain contact region and annealing after making the source / drain contact metal to diffuse the metal elements into the initial contact layer to obtain an auxiliary contact layer, by the additional making of the auxiliary contact layer to improve the contact characteristics between the source / drain contact metal and the semiconductor layer, the contact resistance of the semiconductor device is improved to improve the device performance (such as on-state current characteristics, long-term stability and reliability, etc.), and the manufacturing process is simple and easy to realize mass production. The semiconductor device of the present application, since the auxiliary contact layer is provided below the source / drain contact metal, the contact characteristics between the source / drain contact metal and the contact region of the device are improved, so that the on-state current characteristics, stability and reliability of the device are effectively improved, and the overall structure of the device and the manufacturing process are simple, suitable for popularization and application. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A cross-sectional schematic diagram of a HEMT device is shown.

[0030] Figure 2 A flow chart of the manufacturing method steps of the semiconductor device of the present application is shown.

[0031] Figure 3 A cross-sectional schematic diagram of the structure obtained after performing step S1 in the manufacturing method of the semiconductor device of the present application is shown.

[0032] Figure 4 A cross-sectional schematic diagram of the structure obtained after forming the first dielectric layer in the manufacturing method of the semiconductor device of the present application is shown.

[0033] Figure 5 A first cross-sectional schematic diagram of the structure obtained after forming the source contact hole and the drain contact hole in the manufacturing method of the semiconductor device of the present application is shown.

[0034] Figure 6 A second cross-sectional schematic diagram of the structure obtained after forming the source contact hole and the drain contact hole in the manufacturing method of the semiconductor device of the present application is shown.

[0035] Figure 7Fig. 3 shows a third cross-sectional view of the structure after forming the source and drain contact holes in the method of fabricating the semiconductor device of the present application.

[0036] Figure 8 Fig. 4 shows a cross-sectional view of the structure after performing step S2 in the method of fabricating the semiconductor device of the present application.

[0037] Figure 9 Fig. 5 shows a cross-sectional view of the structure after forming the electrode contact layer in the method of fabricating the semiconductor device of the present application.

[0038] Figure 10 Fig. 6 shows a cross-sectional view of the structure after performing step S3 in the method of fabricating the semiconductor device of the present application.

[0039] Figure 11 Fig. 7 shows a cross-sectional view of the structure after forming the second dielectric layer in the method of fabricating the semiconductor device of the present application.

[0040] Figure 12 Fig. 8 shows a cross-sectional view of the structure after forming the gate in the method of fabricating the semiconductor device of the present application.

[0041] Figure 13 Fig. 9 shows a cross-sectional view of the structure after forming the third dielectric layer in the method of fabricating the semiconductor device of the present application.

[0042] Figure 14 Fig. 10 shows a cross-sectional view of the structure after forming the electrode lead-out layer in the method of fabricating the semiconductor device of the present application.

[0043] BRIEF DESCRIPTION OF DRAWINGS

[0044] 10 semiconductor layer

[0045] 11 substrate

[0046] 12 channel layer

[0047] 13 potential barrier layer

[0048] 14 buffer layer

[0049] 20 first dielectric layer

[0050] 20a source contact hole

[0051] 20b drain contact hole

[0052] 30 initial contact layer

[0053] 40 contact metal layer

[0054] 40a source contact metal

[0055] 40b drain contact metal

[0056] 50 auxiliary contact layer

[0057] 60 second dielectric layer

[0058] 70 gate

[0059] 80 third dielectric layer

[0060] 90a gate metal

[0061] 90b source metal

[0062] 90c drain metal

[0063] S1-S3 steps DETAILED DESCRIPTION

[0064] The present application is herein described, by way of example only, with reference to embodiments thereof. It is to be understood that variations and modifications will be apparent to those skilled in the art and that the scope of the application encompasses all such variations and modifications as fall within the spirit and scope of the application. Therefore, the application should not be limited to the embodiments described herein but should be given the full scope defined by the language of the claims.

[0065] Reference will now be made to the drawings, wherein Figures 2 to 14 It is to be understood that the above-mentioned embodiments are only to illustrate the basic idea of the present application, and thus the drawings only show the components related to the present application, rather than the components number, shape and size in actual implementation. The actual implementation of each component type, number and proportion can be arbitrarily changed, and the component layout type can be more complex.

[0066] Embodiment One

[0067] The present embodiment provides a method for manufacturing a semiconductor device, please refer to Figure 2 , which is shown as a step flow chart of the manufacturing method, including the following steps:

[0068] S1: providing a semiconductor layer, the semiconductor layer having a source contact region and a drain contact region;

[0069] S2: forming an initial contact layer on the semiconductor layer, the initial contact layer also connected with the source contact region and the drain contact region;

[0070] S3: forming a source contact metal and a drain contact metal on the initial contact layer, and performing annealing to diffuse the metal elements in the source contact metal and the drain contact metal into the part of the initial contact layer below the source contact metal and the drain contact metal to obtain an auxiliary contact layer.

[0071] Firstly, referring to Figure 3 , a semiconductor layer 10 is provided, the semiconductor layer 10 has a source contact area and a drain contact area, which can be regarded as the surface or area of the semiconductor layer directly contacting the initial contact layer to achieve the electrical lead-out of the source / drain area.

[0072] As an example, the semiconductor layer 10 includes a substrate 11, a channel layer 12 and a barrier layer 13 stacked from bottom to top, the channel layer 12 has a two-dimensional electron gas on the side facing the barrier layer 13, that is, the manufacturing method of the embodiment is applied to the manufacturing of HEMT devices, and in other embodiments, the manufacturing method can also be applied to the manufacturing of other device structures that need to improve the contact resistance of the source / drain electrode.

[0073] As an example, the substrate 11 includes at least one of a silicon substrate 11 and a silicon carbide substrate 11, the material of the channel layer 12 includes at least one of gallium nitride and gallium arsenide, and the material of the barrier layer 13 includes at least one of aluminum gallium nitride and aluminum gallium arsenide. In the embodiment, the substrate is a silicon carbide substrate, and the materials of the channel layer and the barrier layer are gallium nitride and aluminum gallium nitride, respectively.

[0074] Further, the semiconductor layer 10 further includes a buffer layer 14 between the substrate 11 and the channel layer 12, the buffer layer 14 includes gallium nitride. The buffer layer is used to reduce the lattice mismatch between the substrate and the channel layer when the channel layer is directly epitaxially grown on the substrate, thereby reducing the density of dislocations and other crystal defects, improving the film quality of the channel layer to ensure the working performance of the device.

[0075] Again, referring to Figures 4 to 10 , steps S2 and S3 are performed to form an initial contact layer 30 on the semiconductor layer 10, the initial contact layer 30 is also connected with the source contact area and the drain contact area; a source contact metal 40a and a drain contact metal 40b are formed on the initial contact layer 30, and annealing is performed to diffuse the metal elements in the source contact metal 40a and the drain contact metal 40b into the part of the initial contact layer 30 below the source contact metal 40a and the drain contact metal 40b to obtain an auxiliary contact layer 50.

[0076] In an example, before step S2 is performed, the following steps are further included:

[0077] As shown in Figure 4 , a first dielectric layer 20 is formed above the semiconductor layer 10, the material of the first dielectric layer 20 includes at least one of silicon nitride and silicon oxide, and in the embodiment, the first dielectric layer is made of silicon nitride.

[0078] like Figures 5 to 7 As shown, the first dielectric layer 20 is patterned to form a source contact hole 20a and a drain contact hole 20b, wherein the source contact hole 20a exposes the source contact area, and the drain contact hole 20b exposes the drain contact area. Figures 5 to 7 The three diagrams correspond to three scenarios where the extension degrees of the source and drain contact holes differ. For example... Figure 8 As shown, after forming the source contact hole 20a and the drain contact hole 20b, the initial contact layer 30 is formed so that the initial contact layer 30 fills the bottom of the source contact hole 20a and the drain contact hole 20b to connect with the corresponding contact areas.

[0079] Specifically, the portion of the initial dielectric layer filling the source / drain contact holes serves as the main structure of the auxiliary contact layer. The portion of the initial dielectric layer above the patterned first dielectric layer serves as part of the interlayer dielectric layer. Therefore, in this embodiment, the initial contact layer must at least be an insulating material to prevent electrical connection between the source contact metal and the drain contact metal. Of course, in other embodiments, if certain metal materials can also play the same role or effect as the initial contact layer in this embodiment, then the portion of the initial contact layer above the first dielectric layer needs to be processed to avoid the above situation (e.g., etching or stripping). Besides electrically isolating the subsequently formed source and drain contact metals, the first dielectric layer also serves as a mask layer. In this embodiment, by forming contact holes first and then the initial contact layer, good control over the extension depth of the source and drain contact holes can be achieved (correspondingly, control over the extension degree of the subsequently formed contact metals), thereby enabling flexible design of the device structure and performance.

[0080] Further, step S3 includes the following steps:

[0081] like Figure 9 As shown, a contact metal layer 40 is formed above the first dielectric layer 20. The contact metal layer 40 also fills the source contact hole 20a and the drain contact hole 20b. The contact metal layer 40 is connected to the initial contact layer 30.

[0082] like Figure 10 As shown, the contact metal layer 40 is graphically represented to obtain the source contact metal 40a and the drain contact metal 40b, wherein the source contact metal 40a and the drain contact metal 40b are electrically isolated from each other. Figure 10As shown, after the source contact metal 40a and the drain contact metal 40b are made, an annealing step is performed to diffuse the metal elements in the contact metal into the initial contact layer 30 to obtain the auxiliary contact layer 50.

[0083] For example, the source contact metal 40a is connected to the side of the barrier layer 13 facing away from the channel layer 12, or the source contact metal 40a extends at least into the barrier layer 13, or the source contact metal 40a extends through the barrier layer 13 and into the channel layer 12; and / or, the drain contact metal 40b is connected to the side of the barrier layer 13 facing away from the channel layer 12, or the drain contact metal 40b extends at least into the barrier layer 13, or the drain contact metal 40b extends through the barrier layer 13 and into the channel layer 12. That is, based on Figures 5 to 7 In the contact hole structure of different depths, the contact metal filled in the contact hole has different extension degrees.

[0084] It should be noted that, although Figures 5 to 7 In the embodiment, the depths of the source contact hole and the drain contact hole are the same, but in actual application, the depths of the two contact holes can be designed to be different based on actual needs, and the structures of the source contact metal and the drain contact metal formed correspondingly can be the same or different. In the subsequent drawings, the structure shown in Figure 5 is taken as the basis for the structure obtained in the subsequent process steps. In addition, it is found through actual verification that the comprehensive performance of the device obtained when the source contact metal and the drain contact metal both partially extend into the barrier layer (i.e., the device made based on the contact hole depth shown in Figure 6 ) is the best. After analysis, it is considered that the partial extension of the source / drain contact metal into the barrier layer means that a part of the barrier layer needs to be etched away when the corresponding contact hole is made, so that the thickness of the part of the barrier layer located below the source / drain contact metal is reduced. This can reduce the injection barrier thickness between the channel layer-metal contact, thereby reducing the contact resistance to improve the conductivity of the device. In addition, in order to ensure that the concentration of the two-dimensional electron gas below the remaining part of the barrier layer meets the preset requirements, the thickness range of the remaining part of the barrier layer (i.e., the thickness of the part of the barrier layer located below the source / drain contact metal, as shown in Figure 6 ) after removing a part of the barrier layer is 5-20 nm, including but not limited to 5 nm, 10 nm, 15 nm, and 20 nm.

[0085] As an example, a width of the portion of the source contact metal 40a outside the source contact hole 20a is greater than a width of the portion of the source contact metal 40a in the source contact hole 20a, and / or a width of the portion of the drain contact metal 40b outside the drain contact hole 20b is greater than a width of the portion of the drain contact metal 40b in the drain contact hole 20b. That is, generally, after forming the contact metal layer, a planarization process is performed on the contact metal layer to obtain the source contact metal and the drain contact metal separated from each other. However, in the embodiment, the source / drain contact metal is formed in a patterned manner such that the width of the portion of the source / drain contact metal outside the source / drain contact hole is greater than the width of the portion of the source / drain contact metal in the source / drain contact hole, which can reduce the difficulty of the photolithography alignment process in subsequent manufacturing of the electrode lead-out structure, and thus avoid the situation that the poor contact between the electrode lead-out structure and the contact metal due to the poor alignment degree causes the working performance of the device.

[0086] As an example, the material of the initial contact layer 30 includes aluminum nitride, and of course, in other embodiments, the material of the initial contact layer can also be other materials capable of achieving the same effect without being limited to aluminum nitride.

[0087] As an example, the thickness of the initial contact layer 30 is less than or equal to 5 nm, including but not limited to 4 nm, 3 nm, 2 nm, etc.

[0088] Further, the method for forming the initial contact layer 30 includes at least one of an atomic layer deposition method and a chemical vapor deposition method, and is preferably a plasma-enhanced atomic layer deposition method, so as to obtain an initial contact film layer structure that is beneficial to the subsequent controllable diffusion of metal elements.

[0089] As an example, the annealing temperature range for annealing to diffuse metal elements into the initial contact layer to obtain the auxiliary contact layer is 750–950°C, including but not limited to 800°C, 850°C, and 900°C; the annealing time is 20–40 seconds, including but not limited to 25 seconds, 30 seconds, and 35 seconds. It is important to note that the process parameters for annealing need to be reasonably adjusted based on the thickness and material type of the initial contact layer to avoid situations where insufficient metal element content or uneven distribution in the subsequent auxiliary contact layer may cause adverse effects (e.g., poor contact), or cause some metal elements to diffuse into the source and drain regions, resulting in irreversible damage to the device's electrical performance. For the initial contact layer made of AlN, it is more preferable that the annealing temperature is 825-875℃ (e.g., 850℃) and the annealing time is 28-32s (e.g., 30s). At this time, the auxiliary contact layer and the barrier layer obtained by the diffusion of the source metal and the drain metal form a good ohmic contact and at the same time suppress the further diffusion of metal elements into the structural layer (i.e., the barrier layer) below the auxiliary contact layer (that is, the annealing treatment under this process condition makes the degree of metal element diffusion optimal, that is, it can achieve good ohmic contact and avoid excessive diffusion of metal elements), thus avoiding damage to the barrier layer, thereby maintaining a high level of two-dimensional electron gas concentration below the source metal and the drain metal.

[0090] As an example, the production method also includes the following steps:

[0091] like Figure 11 As shown, a second dielectric layer 60 is formed, which covers the source contact metal 40a and the drain contact metal 40b.

[0092] like Figure 12 As shown, a gate 70 is formed, which penetrates the second dielectric layer 60 and is connected to the semiconductor layer 10. The source contact metal 40a and the drain contact metal 40b are respectively arranged on both sides of the gate 70. In one example, a gate contact hole can be formed first, which penetrates the second contact layer, an initial contact layer located between the source contact metal and the drain contact metal, and the first dielectric layer. Then, a gate metal layer that at least fills the gate contact hole is deposited on the second dielectric layer and patterned to obtain the gate.

[0093] like Figure 13 As shown, a third dielectric layer 80 is formed, which further covers the gate 70 and the second dielectric layer 60;

[0094] like Figure 14As shown, an electrode lead-out layer is formed, which includes gate 70 metal connected with the gate 70, source metal 90b connected with the source contact metal 40a, and drain metal 90c connected with the drain contact metal 40b.

[0095] Specifically, the method for manufacturing the semiconductor device of the present embodiment forms an initial contact layer before forming the source contact metal and the drain contact metal on the source contact region and the drain contact region, and performs annealing treatment after forming the source contact metal and the drain contact metal to diffuse the metal elements in the source / drain contact metal into the initial contact layer to form an auxiliary contact layer. On one hand, the auxiliary contact layer itself reduces the contact resistance between the source / drain contact metal and the source / drain contact region, thereby achieving good contact resistance characteristics even when the barrier layer is relatively thick. On the other hand, the auxiliary contact layer induces an increase in the two-dimensional electron gas density near (e.g., below) the auxiliary contact layer, thereby further improving the contact resistance characteristics and effectively improving the performance of the device. When AlN is used to form the initial auxiliary layer, since AlN is a polar material, when AlN is grown on the barrier layer, the two-dimensional electron gas density at the channel below the auxiliary contact layer is increased under the effects of spontaneous polarization and piezoelectric polarization.

[0096] The manufacturing method of the present embodiment forms an initial contact layer on the surface of the source / drain contact region and performs annealing after forming the source / drain contact metal to diffuse the metal elements into the initial contact layer to obtain an auxiliary contact layer. The auxiliary contact layer is additionally formed to improve the contact characteristics between the source / drain contact metal and the semiconductor layer, improve the contact resistance of the semiconductor device, and improve the working performance of the device (such as the on-state current characteristics, long-term stability, and reliability). Moreover, the manufacturing process is simple and easy to implement in mass production.

[0097] Embodiment Two

[0098] The present embodiment provides a semiconductor device that can be obtained by using the manufacturing method described in Embodiment One or other suitable manufacturing methods. Please refer to Figure 14 , which shows a partial cross-sectional schematic view of the semiconductor device, including a semiconductor layer 10, an auxiliary contact layer 50, a source contact metal 40a, and a drain contact metal 40b.

[0099] Specifically, the semiconductor layer 10 has a source contact region and a drain contact region, the auxiliary contact layer 50 is located on the semiconductor layer 10, and the auxiliary contact layer 50 is connected with the source contact region and the drain contact region, the source contact metal 40a and the drain contact metal 40b are both located on the auxiliary contact layer 50, and the auxiliary contact layer 50 contains metal elements diffused from the source contact metal 40a and the drain contact metal 40b.

[0100] As an example, the material of the auxiliary contact layer 50 includes aluminum nitride.

[0101] As an example, the thickness of the auxiliary contact layer 50 is less than or equal to 5 nm, including but not limited to 4 nm, 3 nm, and 2 nm; further, the forming method of the auxiliary contact layer 50 includes at least one of a plasma-enhanced atomic layer deposition method and a chemical vapor deposition method.

[0102] As an example, the semiconductor layer 10 includes, from bottom to top, a substrate 11, a channel layer 12, and a barrier layer 13, and the channel layer 12 has a two-dimensional electron gas on the side facing the barrier layer 13. That is, the semiconductor device of the present embodiment is a HEMT device, but in other embodiments, the semiconductor device can also be other suitable device structures.

[0103] As an example, the source contact metal 40a is connected with the side of the barrier layer 13 facing away from the channel layer 12, or the source contact metal 40a at least extends into the barrier layer 13, or the source contact metal 40a penetrates through the barrier layer 13 and extends into the channel layer 12; and / or, the drain contact metal 40b is connected with the side of the barrier layer 13 facing away from the channel layer 12, or the drain contact metal 40b at least extends into the barrier layer 13, or the drain contact metal 40b penetrates through the barrier layer 13 and extends into the channel layer 12.

[0104] The semiconductor device of the present embodiment, because of the auxiliary contact layer arranged below the source / drain contact metal, the contact characteristics between the source / drain contact metal and the contact region of the device are improved, so that the on-current characteristics, stability and reliability of the device are effectively improved, and the overall structure of the device and the manufacturing process are simple, suitable for popularization and application.

[0105] In summary, the semiconductor device manufacturing method of the present application, by making an initial contact layer on the surface of the source / drain contact area and annealing after making the source / drain contact metal to diffuse the metal elements into the initial contact layer to obtain an auxiliary contact layer, the additional making of the auxiliary contact layer improves the contact characteristics between the source / drain contact metal and the semiconductor layer, improves the contact resistance of the semiconductor device to improve the device performance, and the manufacturing process is simple and easy to realize mass production. The semiconductor device of the present application, because the auxiliary contact layer is arranged below the source / drain contact metal, the contact characteristics between the source / drain contact metal and the contact area of the device are improved, so that the on-current characteristics, stability and reliability of the device are effectively improved, and the overall structure of the device and the manufacturing process are simple, suitable for popularization and application. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.

[0106] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor layer is provided, the semiconductor layer including a substrate, a channel layer and a barrier layer stacked from bottom to top, the channel layer having a two-dimensional electron gas on the side facing the barrier layer, and a source contact region and a drain contact region formed on the barrier layer. An initial contact layer is formed on the semiconductor layer, and the initial contact layer is also connected to the source contact region and the drain contact region. The material of the initial contact layer includes aluminum nitride. Source contact metal and drain contact metal are formed on the initial contact layer. Annealing is performed to allow the metal elements in the source contact metal and drain contact metal to diffuse into the portion of the initial contact layer located below the source contact metal and drain contact metal to obtain an auxiliary contact layer. The auxiliary contact layer includes aluminum nitride and metal elements diffused from the source contact metal and drain contact metal. While improving the contact resistance characteristics, the concentration of two-dimensional electron gas in the channel below the auxiliary contact layer is induced to increase under the action of spontaneous polarization and piezoelectric polarization.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that: The thickness of the initial contact layer is less than or equal to 5 nm, and the method for forming the initial contact layer includes at least one of atomic layer deposition and chemical vapor deposition.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that: The source contact metal is connected to the side of the barrier layer opposite to the channel layer, or the source contact metal extends at least into the barrier layer, or the source contact metal penetrates the barrier layer and extends into the channel layer. And / or, the drain contact metal is connected to the side of the barrier layer opposite to the channel layer, or, the drain contact metal extends at least into the barrier layer, or, the drain contact metal penetrates the barrier layer and extends into the channel layer.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, Includes the following steps: A first dielectric layer is formed over the semiconductor layer and the first dielectric layer is patterned to form source contact holes and drain contact holes, wherein the source contact holes expose the source contact area and the drain contact holes expose the drain contact area; A contact metal layer is formed above the first dielectric layer, and the contact metal layer further fills the source contact hole and the drain contact hole; The contact metal layer is graphically represented to obtain the source contact metal and the drain contact metal.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that: The width of the portion of the source contact metal located outside the source contact hole is greater than the width of the portion of the source contact metal located inside the source contact hole, and / or, the width of the portion of the drain contact metal located outside the drain contact hole is greater than the width of the portion of the drain contact metal located inside the drain contact hole.

6. A semiconductor device, characterized in that, include: A semiconductor layer, comprising a substrate, a channel layer and a barrier layer stacked from bottom to top, wherein the channel layer has a two-dimensional electron gas on the side facing the barrier layer, and a source contact region and a drain contact region are provided on the barrier layer. An auxiliary contact layer is located on the semiconductor layer, and the auxiliary contact layer is connected to the source contact region and the drain contact region; The source contact metal and drain contact metal are located on the auxiliary contact layer. The auxiliary contact layer contains metal elements diffused from the source contact metal and drain contact metal, as well as aluminum nitride. While improving the contact resistance characteristics, the auxiliary contact layer induces an increase in the concentration of two-dimensional electron gas in the channel below the auxiliary contact layer under the action of spontaneous polarization and piezoelectric polarization.

7. The semiconductor device according to claim 6, characterized in that: The thickness of the auxiliary contact layer is less than or equal to 5 nm, and the method for forming the auxiliary contact layer includes at least one of atomic layer deposition and chemical vapor deposition.

8. The semiconductor device according to claim 6, characterized in that: The source contact metal is connected to the side of the barrier layer opposite to the channel layer, or the source contact metal extends at least into the barrier layer, or the source contact metal penetrates the barrier layer and extends into the channel layer. And / or, the drain contact metal is connected to the side of the barrier layer opposite to the channel layer, or, the drain contact metal extends at least into the barrier layer, or, the drain contact metal penetrates the barrier layer and extends into the channel layer.

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