Dual gain column structure for column power area efficiency

Abstract

The present disclosure relates to a dual gain column structure for column power area efficiency. A pixel cell sense circuit includes a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and is configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and is configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bit line and selectively coupled to a second bit line. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bit line and selectively coupled to the second bit line.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to high dynamic range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensors. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, and the like of the image sensors in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design as well as image acquisition processing. The technology for manufacturing image sensors has continued to progress rapidly. For example, the demand for higher resolution and lower power consumption has prompted further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having a light-sensitive element (e.g., a photodiode) that absorbs a portion of the incident image light and generates image charge upon absorbing the image light. The image charge photo-generated by the pixels can be measured as an analog output image signal on a column bit line that varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bit line as an analog image signal and converted to a digital value to produce a digital image (e.g., image data) representing the external scene. The analog image signal on the bit line is coupled to a readout circuit that includes an input stage having an analog-to-digital (ADC) circuit to convert those analog image signals from the pixel array to digital image signals. SUMMARY

[0004] According to one aspect of the disclosure, a pixel cell readout circuit is provided. The pixel cell readout circuit includes a ramp generator having a ramp generator output, a first gain network coupled to the ramp generator output and configured to provide a first variable comparator gain, a second gain network coupled to the ramp generator output and configured to provide a second variable comparator gain, a first comparator having a first input coupled to the first gain network, the first comparator further having a second input selectively coupled to a first bit line and selectively coupled to a second bit line, and a second comparator having a first input coupled to the second gain network, the second comparator further having a second input selectively coupled to the first bit line and selectively coupled to the second bit line, wherein during a first readout period, the first variable comparator gain is configured to be different than the second variable comparator gain, and the second inputs of the first and second comparators are selectively coupled to the first bit line and selectively decoupled from the second bit line; and wherein during a second readout period, the first variable comparator gain is configured to be different than the second variable comparator gain, and the second inputs of the first and second comparators are selectively coupled to the second bit line and selectively decoupled from the first bit line.

[0005] According to another aspect of the disclosure, a method of operating a pixel cell readout circuit is provided. The method includes coupling a first gain network between a ramp generator and a first comparator, wherein the first gain network is configured to provide a first variable comparator gain, coupling a second gain network between the ramp generator and a second comparator, wherein the second gain network is configured to provide a second variable comparator gain, during a first readout period— selectively coupling the first and second comparators to a first bit line, setting the first and second variable comparator gains to different values, and reading out an image signal from the first bit line, and during a second readout period— selectively coupling the first and second comparators to a second bit line, setting the first and second variable comparator gains to different values, and reading out an image signal from the second bit line. BRIEF DESCRIPTION OF DRAWINGS

[0006] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0007] Figure 1 FIG. illustrates one example of an imaging system including a pixel array in accordance with the teachings of the present disclosure.

[0008] Figure 2FIG. 2A illustrates a schematic diagram of one example of a readout circuit including two comparators in accordance with the teachings of this disclosure.

[0009] Figure 3A 3B FIG. 3A illustrates a timing diagram of the two comparators in an example readout circuit coupled to a pixel in a double conversion gain mode in accordance with the teachings of this disclosure.

[0010] Figure 4A 4B FIGs. 4A and 4B illustrate a schematic diagram of one example of a readout circuit including two comparators during two double analog gain readout periods and two linear mode readout periods in accordance with the teachings of this disclosure.

[0011] Figure 5 FIG. 5A illustrates a schematic diagram of another example of a readout circuit including four comparators in accordance with the teachings of this disclosure.

[0012] Figure 6 FIG. 6A illustrates a timing diagram of the four comparators in an example readout circuit during two double analog gain readout periods and two linear mode readout periods in accordance with the teachings of this disclosure.

[0013] Figure 7A 7B FIGs. 7A and 7B illustrate a schematic diagram of one example of a readout circuit including four comparators during two double analog gain readout periods and two linear mode readout periods in accordance with the teachings of this disclosure.

[0014] Throughout the drawings, like reference numbers indicate corresponding parts throughout the several views. One skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in each of the figures can be exaggerated relative to other elements for improving the DETAILED DESCRIPTION

[0015] Examples are described herein directed to imaging systems having pixel cell readout circuits that provide double analog gain. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or ​​​

[0016] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present disclosure. Thus, the appearances of the phrase "in one example" or "in an example" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0017] Spatially relative terms (such as "beneath", "below", "lower", "above", "upper", "top", "bottom", "left", "right", "center", "intermediate", and the like) can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will also be understood that when an element is referred to as being "between" two other elements, it can be the only element between the two other elements or one or more intervening elements can also be present.

[0018] Throughout this specification, several technical terms are used. Such terms are presented herein with their ordinary meanings unless specifically defined herein or the context of their use clearly dictates otherwise. It is noted that in this document, element names and symbols can be used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0019] As will be discussed, various examples of imaging systems having readout circuits that provide dual analog gain are disclosed. In various examples, each of a pair of ADC comparators is configured to selectively couple to one of two bit lines on a first input and to a slope gain network on a second input. In various examples, switch control is used to implement bit line selection logic.

[0020] Image sensors can implement dual conversion gain to obtain a high dynamic range. A high dynamic range can be obtained by reading from a pixel at a low gain, then reading from the pixel at a high gain, and then combining the two readouts. However, dual conversion gain operation typically requires two structures, such as two comparators and / or two slope gain capacitor networks, for each bit line. This can result in an undesirable large column area.

[0021] In various examples of the disclosure, each pair of bit lines is selectively coupled to a pair of ADC comparators, and the same comparators are used for dual analog gain readout and for non-dual conversion gain readout.

[0022] To illustrate, Figure 1 An example of an imaging system 100 having a readout circuit 106 providing dual analog gain (DAG) in accordance with the teachings of this disclosure is shown. In particular, Figure 1 The example depicted in FIG. 1 illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuit 110, readout circuit 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., PI, P2,..., Pn) arranged in a number of rows (e.g., Rl to Ry) and a number of columns (e.g., CI to Cx) to acquire image data of a person, place, object, etc. that can then be used to present an image of the person, place, object, etc.

[0023] In various examples, the readout circuit 106 can be configured to read out image signals through the column bit lines 112. As will be discussed, in various examples, the readout circuit 106 can include an analog-to-digital converter (ADC) having DAG in accordance with the teachings of this disclosure. In various examples, the ADC includes a ramp generator 114 and a comparator circuit 116. The ramp generator 114 has a ramp generator output from which a ramp signal 120 is provided to the comparator circuit 116. In an example, digital image data values generated by the comparator circuit 116 can then be received by the functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying post-image effects (e.g., cropping, rotating, red-eye removal, adjusting brightness, adjusting contrast, or otherwise).

[0024] In one example, the control circuit 110 is coupled to the pixel array 102 to control operation of the plurality of photodiodes in the pixel array 102. For example, the control circuit 110 can generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with an illumination effect such as a flash.

[0025] In one example, imaging system 100 may be included in a digital, mobile phone, laptop computer, endoscope, security camera, or imaging device for automobiles. Additionally, imaging system 100 may be coupled to other hardware components, such as processors (general purpose or other), memory elements, outputs (USB ports, wireless transmitters, HDMI ports, etc.), lighting / flash, electrical inputs (keyboards, touch displays, tracking pads, mice, microphones, etc.), and / or displays. These other hardware components can deliver instructions to imaging system 100, retrieve image data from imaging system 100, or manipulate image data supplied by imaging system 100.

[0026] Figure 2 The diagram illustrates an example of the readout circuit 206 according to the teachings of this disclosure. It should be understood that... Figure 2 The readout circuit 206 can be included in, for example Figure 1 The example shown is the readout circuit 106 in the imaging system 100, and similarly named and numbered elements described above are similarly coupled and function in the following text.

[0027] The readout circuit 206 includes a first comparator 216a having a first input coupled to a bit-line switching network 222 and a second input coupled to a first ramp gain network 228a. In the depicted example, it should be understood that the first input of the first comparator 216a is the gate of transistor 242a, and the second input of the first comparator 216a is the gate of transistor 244a. The readout circuit 206 also includes a second comparator 216b having a first input coupled to a bit-line switching network 222 and a second input coupled to a second ramp gain network 228b. In the depicted example, it should be understood that the first input of the second comparator 216b is the gate of transistor 242b, and the second input of the second comparator 216b is the gate of transistor 244b. As can be understood in the depicted example, the first comparator 216a and the second comparator 216b share many similarities. Therefore, for the sake of brevity, the following description may be applied to both the first comparator 216a and the second comparator 216b where applicable. As shown, each of the comparators 216 includes transistors 238 and 240 coupled as current mirrors. A first input transistor 242 is coupled to transistor 238, and a second input transistor 244 is coupled to transistor 240. As shown, a tail current source 252 is coupled to transistors 242 and 244. In one example, the gate node of transistor 242 is coupled to a line switch network 222 via capacitor 250, which is coupled to the comparator output VOUT 254 via switch 246. In one example, the gate node of transistor 244 is coupled to a ramp gain network 228. The ramp gain network 228 is also coupled to transistor 240 via switch 248.

[0028] In the illustrated example, the bit line switch network 222 includes a first switch 224a configured to selectively couple the first comparator 216a to the first bit line BL0 212a and decouple from the first bit line, a second switch 226a configured to selectively couple the first comparator 216a to the second bit line BL1 212b and decouple from the second bit line, a third switch 224b configured to selectively couple the second comparator 216b to the first bit line BL0 212a and decouple from the first bit line, and a fourth switch 226b configured to selectively couple the second comparator 216b to the second bit line BL1 212b and decouple from the second bit line. In various examples, the bit line switch network 222 includes two switches, each configured to selectively couple one of the comparators 216 to both the first bit line BL0 212a and the second bit line BL1 212b. In the depicted example, the first bit line BL0 212a is coupled to the first pixel circuit 204a and the second pixel circuit 204b, and the second bit line BL1 212b is coupled to the third pixel circuit 204c and the fourth pixel circuit 204d. The pixel circuits 204 are part of a pixel array 202, which can be an example or an example portion of the pixel array 102 as shown in Figure 1

[0029] ​According to the teachings of this disclosure, the first and second ramp gain networks 228a, 228b are configured to provide a variable comparator gain by controlling the slope of the ramp signal generated by the ramp generator output VRAMP 214. As the slope of the ramp signal becomes lower, the variable comparator gain becomes higher. As can be appreciated in the depicted example, the first and second ramp gain networks 228a, 228b share many similarities. Thus, for the sake of brevity, the following description can apply to both the first and second ramp gain networks 228a, 228b where applicable. As shown, in the illustrated example, each of the first and second ramp gain networks 228a, 228b includes a first gain capacitor 234 and a second gain capacitor 236. The first gain capacitor 234 can be coupled between the second input of the comparator 216 and the ramp generator output VRAMP 214. The second gain capacitor 236 can be selectively coupled between the second input of the comparator 216 and either the ramp generator output VRAMP 214 (via switch 230) or ground (via switch 232). Only one of the switches 230 and 232 is on at a time, allowing the first and second gain capacitors 234, 236 to act as voltage dividers when it is desired to reduce the slope of the ramp signal. In various examples, it should be appreciated that other examples of the first and second ramp gain networks 228a, 228b can have different components and / or configurations that provide a variable comparator gain according to the teachings of this disclosure. For example, the number of gain capacitors in each of the first and second ramp gain networks 228a, 228b can depend on the number of desired comparator gain settings. For example, in various examples, the first and second ramp gain networks 228a, 228b can each include one gain capacitor 234 and one or more second gain capacitors 236 and one or more sets of corresponding switches 230 and 232 that selectively couple the respective second gain capacitors 236 between the second input of the comparator 216 and either the ramp generator output VRAMP 214 (via switch 230) or ground (via switch 232), as Figure 2 shown in the depicted example.

[0030] Figure 3A FIG. 6 illustrates a timing diagram of two ADC comparators 316a, 316b in an example readout circuit during a first dual-analog-gain (DAG) long readout period Tl, a second DAG long readout period T2, a first linear single-analog-gain mode short readout period T3, and a second linear single-analog-gain mode very short readout period T4, according to the teachings of this disclosure. Figure 4A , 4BThe 4C and 4D diagrams illustrate an example of a readout circuit including a first comparator 416a and a second comparator 416b during four readout cycles T1, T2, T3, and T4, in accordance with the teachings of this disclosure. It should be understood that... Figure 4A , 4B The first comparator 416a and the second comparator 416b, as well as the first ramp gain network 428a and the second ramp gain network 428b depicted in 4C and 4D, can be Figure 2 Examples of the first comparator 216a and the second comparator 216b, as well as the first ramp gain network 228a and the second ramp gain network 228b, are depicted herein, and similarly named and numbered elements described above are similarly coupled and function in the following text. The first readout period T1 and the second readout period T2 correspond to DAG readout, during which the comparators simultaneously read out one half-row of pixel circuitry at a time through one bit line. In various examples, if pixels operating in dual conversion gain (DCG) mode are used, the readout circuitry is configured to operate in high conversion gain (HCG) mode during the first readout period T1 and the second readout period T2, and in low conversion gain (LCG) mode during the third readout period T3 and the fourth readout period T4. In the depicted example, the third readout period T3 and the fourth readout period T4 correspond to interleaved linear mode readout, during which the comparators simultaneously read out two half-rows of pixel circuitry through two bit lines.

[0031] Figure 3B and 3C The diagram illustrates a timing example of a comparator in an exemplary readout circuit coupled to a pixel operating in a single-conversion-gain mode (HCG mode or LCG mode, respectively) during four readout cycles T1, T2, T3, and T4. While pixels operating in single-conversion-gain mode are more feasible for small-pitch pixels, they typically have a lower dynamic range. For example, while a DCG pixel can produce an image with a dynamic range of approximately 120 dB, an HCG pixel only can produce an image with a dynamic range of approximately 108 dB, and an LCG pixel only can produce an image with a dynamic range of approximately 111 dB. The LCG pixel only has a slightly higher dynamic range than the HCG pixel only because the readout noise ratio of the LCG pixel only is lower than its conversion-gain ratio.

[0032] Discuss together Figure 3ATo C and 4A to D, the first comparator 416a has a first input selectively coupled to the first bit line BLO 412a or the second bit line BL1 412b depending on the switch configuration (e.g., 222), and a second input coupled to the first ramp gain network 428a. The second comparator 416b has a first input selectively coupled to the first bit line BLO 412a or the second bit line BL1 412b depending on the switch configuration (e.g., 222), and a second input coupled to the second ramp gain network 428b. In the illustrated example, each ramp gain network 428 includes a first gain capacitor 434 and a second gain capacitor 436. The first gain capacitor 434 can be coupled between the second input of the comparator 416 and the ramp generator output VRAMP 414. The second gain capacitor 436 can be selectively coupled between the second input of the comparator 416 and the ramp generator output VRAMP 414 (via switch 430) or ground (via switch 432). Only one of switches 430 and 432 is on at a time, allowing the first gain capacitor 434 and the second gain capacitor 436 to act as voltage dividers when needed to reduce the slope of the ramp signal.

[0033] In the depicted example, during the first DAG long readout period T1, the second gain capacitor 436a of the first ramp gain network 428a is grounded via switch 432a. The first ramp gain network 428a can be configured to provide 16x or 8x comparator gain to the first comparator 416a. The second gain capacitor 436b of the second ramp gain network 428b is coupled to the ramp generator output VRAMP 414 via switch 430b. The second ramp gain network 428b can be configured to provide lx comparator gain to the first comparator 416a. In various examples, both the first comparator 416a and the second comparator 416b are selectively coupled to the first bit line BLO 412a and selectively decoupled from the second bit line BL1 412b, such that a DAG readout of the first bit line can be performed.

[0034] In the depicted example, during the second DAG long readout period T2, the first and second slew rate gain networks 428a, 428b can remain in the same configuration as in the first DAG long readout period Tl. The first slew rate gain network 428a can continue to provide a comparator gain of 16x or 8x, while the second slew rate gain network 428b can continue to provide a comparator gain of lx. In other words, in the depicted example, the first slew rate gain network 428a is configured to provide a greater comparator gain (e.g., 16x or 8x) than the comparator gain (e.g., lx) provided by the second slew rate gain network 428b during the first and second DAG long readout periods Tl, T2. In various examples, both the first and second comparators 416a, 416b are selectively coupled to the second bit line BLl 412b and selectively decoupled from the first bit line BLO 412a, such that a DAG readout of the second bit line can be performed.

[0035] In various examples, it should be appreciated that during the first and second DAG long readout periods Tl, T2, the decoupled (i.e., unselected floating) bit line (e.g., the second bit line BLl 412b for the first readout period Tl, the first bit line BLO 412a for the second readout period T2) can be configured to reduce horizontal fixed pattern noise associated with the bit line. One example of this configuration is to clamp the bit line.

[0036] In the depicted example, during the first linear mode short readout period T3, the second gain capacitor 436a of the first slew rate gain network 428a is coupled to the ramp generator output VRAMP 414 via the switch 430a. The second gain capacitor 436b of the second slew rate gain network 428b can remain coupled to the ramp generator output VRAMP 414 via the switch 430b. Both the first and second slew rate gain networks 428a, 428b can be configured to each provide an equal comparator gain of 2x. The first comparator 416a is now coupled to the first bit line BLO 412a, while the second comparator 416b is now coupled to the second bit line BLl 412b, such that a linear mode readout of both the first and second bit lines 412a, 412b can be performed by the respective first and second comparators 416a, 416b.

[0037] During the second linear mode very short readout period T4, the switches remain in the same configuration as in the first linear mode very short readout period T3. However, both the first and second ramp gain networks 428a and 428b can now each be configured to provide equal lx comparator gain. In other words, the first and second variable comparator gains (e.g., 2x) during the third readout period T3 are configured to be greater than the first and second variable comparator gains (e.g., lx) during the fourth readout period T4. Linear mode readout of both the first and second bit lines is then performed.

[0038] In various examples, it should be appreciated that the first and second ramp gain networks 428a and 428b can provide any variable comparator gain (e.g., lx, 2x, 4x, 8x, 16x, etc.) to the first and second comparators 416a and 416b. For example, during the first readout period Tl, the variable comparator gain provided to the first comparator 416a can be configured to be greater than the variable comparator gain provided to the second comparator 416b. It should be appreciated that the same comparators 416a and 416b are used to perform the DAG and linear mode readout, which allows for a reduced number of components and column area required.

[0039] Figure 5 A schematic diagram illustrating another example of a readout circuit 506 in accordance with the teachings of this disclosure is illustrated. It should be appreciated that the readout circuit 506 can be an example of the readout circuit 106 included in the imaging system 100 as shown in Figure 5 Figure 1 The readout circuit 506 can be an example of the readout circuit 106 included in the imaging system 100 as shown in

[0040] The readout circuit 506 includes a first comparator 516a having a first input coupled to the first bit line switch network 522a and a second input coupled to a first ramp gain network 528a, and a second comparator 516b having a first input coupled to the first bit line switch network 522a and a second input coupled to a second ramp gain network 528b. The readout circuit 506 further includes a third comparator 516c having a first input coupled to a second bit line switch network 522b and a second input coupled to a third ramp gain network 528c, and a fourth comparator 516d having a first input coupled to the second bit line switch network 522b and a second input coupled to a fourth ramp gain network 528d. Details regarding each of the capacitors 516, the first bit line switch network 522a, and the ramp gain networks 528 are generally similar to the capacitors 216, the bit line switch network 222, and the ramp gain networks 228 shown in Figure 2 Figure 2 discussed with respect to the capacitors 216, the bit line switch network 222, and the ramp gain networks 228 shown in and discussed with respect to the imaging system 100 shown in​​

[0041] The second bit line switch network 522b includes a first switch 524c configured to selectively couple the third comparator 516c to and decouple from the third bit line BL2 512c, a second switch 526c configured to selectively couple the third comparator 516c to and decouple from the fourth bit line BL3 512d, a third switch 524d configured to selectively couple the fourth comparator 516d to and decouple from the third bit line BL2 512c, and a fourth switch 526d configured to selectively couple the fourth comparator 516d to and decouple from the fourth bit line BL3 512d.

[0042] The first bit line BL0 512a is coupled to the first pixel circuit 504a and the second pixel circuit 504b, the second bit line BL1 512b is coupled to the third pixel circuit 504c and the fourth pixel circuit 504d, the third bit line BL2 512c is coupled to the fifth pixel circuit 504e and the sixth pixel circuit 504f, and the fourth bit line BL3 512d is coupled to the seventh pixel circuit 504g and the eighth pixel circuit 504h. The pixel circuits 504 are part of a pixel array 502, which can be an example or an example portion of the pixel array 102 illustrated in FIG. 1. Figure 1

[0043] As will be discussed below, this four bit line configuration allows the readout circuit 506 to read out twice as many pixel circuits 504 in the same amount of time as the readout circuit 206 illustrated in FIG. 2. Figure 2 However, this advantage should be balanced against the need for more circuit components and column area.

[0044] Figure 6 A timing diagram illustrating four ADC comparators 616a, 616b, 616c, and 616d in an example readout circuit during a first double analog gain (DAG) long readout period Tl, a second DAG long readout period T2, a first linear mode short readout period T3, and a second linear mode very short readout period T4, in accordance with the teachings of this disclosure is illustrated. Figure 7A 、 7B ​FIGS. 7C and 7D illustrate timing diagrams of one example of a readout circuit including four comparators 716a, 716b, 716c, and 716d during four readout periods Tl, T2, T3, and T4, in accordance with the teachings of this disclosure. The first readout period Tl and the second readout period T2 correspond to a DAG readout, during which time 2x1 half-rows of pixel circuits are read out by the four comparators at a time. In various examples, if pixels operating in a double conversion gain (DCG) mode are used, the readout circuit is configured to operate in a high conversion gain (HCG) mode during the first readout period Tl and the second readout period T2, and in a low conversion gain (LCG) mode during the third readout period T3 and the fourth readout period T4. In the depicted example, the third readout period T3 and the fourth readout period T4 correspond to an interleaved linear mode readout, during which time 2x2 half-rows of pixel circuits are read out by the four comparators at a time.

[0045] As discussed above, Figure 3B and 3C FIGS. 7C and 7D illustrate timing diagrams of one example of a readout circuit including four comparators 716a, 716b, 716c, and 716d during four readout periods Tl, T2, T3, and T4, in accordance with the teachings of this disclosure. The first readout period Tl and the second readout period T2 correspond to a DAG readout, during which time 2x1 half-rows of pixel circuits are read out by the four comparators at a time. In various examples, if pixels operating in a double conversion gain (DCG) mode are used, the readout circuit is configured to operate in a high conversion gain (HCG) mode during the first readout period Tl and the second readout period T2, and in a low conversion gain (LCG) mode during the third readout period T3 and the fourth readout period T4. In the depicted example, the third readout period T3 and the fourth readout period T4 correspond to an interleaved linear mode readout, during which time 2x2 half-rows of pixel circuits are read out by the four comparators at a time.

[0046] are discussed together Figure 6 and Figure 7A to D, the details regarding the portions of the timing diagrams and the schematic diagrams illustrating the first comparator 716a and the second comparator 716b that can be coupled to the first bit line BLO 712a and the second bit line BLl 712b are generally similar to Figure 3A in FIGS. 6C and 6D, and Figure 4A to D, and are therefore omitted. The portions of the timing diagrams and the schematic diagrams illustrating the third comparator 716c and the fourth comparator 716d that can be coupled to the third bit line BL2 712c and the fourth bit line BL3 712d reflect the portions of the timing diagrams and the schematic diagrams illustrating the first comparator 716a and the second comparator 716b that can be coupled to the first bit line BLO 712a and the second bit line BLl 712b during each of the four readout periods Tl, T2, T3, and T4.

[0047] For example, during a first DAG long readout period Tl, the first and third comparators 716a, 716c have a comparator gain of 16x or 8x, and the second and fourth comparators 716b, 716d have a comparator gain of lx. In various examples, the first and second comparators 716a, 716b are selectively coupled to the first bit line BL0712a and selectively decoupled from the second bit line BL1712b, and the third and fourth comparators 716c, 716d are selectively coupled to the third bit line BL2712c and selectively decoupled from the fourth bit line BL3712d, such that a DAG readout of the first and third bit lines can be performed.

[0048] During a second DAG long readout period T2, the comparator gains to the comparators 716a-d can remain the same as in the first DAG long readout period Tl. In various examples, the first and second comparators 716a, 716b are selectively coupled to the second bit line BL1712b and selectively decoupled from the first bit line BL0712a, and the third and fourth comparators 716c, 716d are selectively coupled to the fourth bit line BL3712d and selectively decoupled from the third bit line BL2712c, such that a DAG readout of the second and fourth bit lines can be performed.

[0049] In various examples, during the first and second DAG long readout periods Tl, T2, the decoupled (i.e., unselected floating) bit lines (e.g., the second and fourth bit lines BL1712b, 712d for the first readout period Tl, and the first and third bit lines BL0712a, 712c for the second readout period T2) are adjusted to reduce horizontal fixed-pattern noise associated with the bit lines. One example of this adjustment is clamping the bit lines.

[0050] During a first linear mode short readout period T3, all four comparators 716a-d each have an equal 2x gain. The first comparator 716a is coupled to the first bit line BL0712a, the second comparator 716b is coupled to the second bit line BL1712b, the third comparator 716c is coupled to the third bit line BL2712c, and the fourth comparator 716d is coupled to the fourth bit line BL3712d, such that a linear mode readout of all four bit lines can be performed.

[0051] During a second linear mode very short readout period T4, the switches remain in the same configuration as in the first linear mode very short readout period T3. However, the four comparators each have an equal lx gain. Again, a linear mode readout of all four bit lines is performed.

[0052] In various examples, the four sloping gain networks 728a-d can provide any variable comparator gain (e.g., lx, 2x, 4x, 8x, 16x) to their corresponding comparators 716a-d. For example, during the first readout period Tl, the variable comparator gain provided to the first comparator 716a can be configured to be greater than the variable comparator gain provided to the second comparator 716b. It should be appreciated that the same comparators 716a-d are used to perform both the DAG and linear mode readout, which allows for a reduced number of components and column area required.

[0053] The above description of illustrated examples of the disclosure, including what is described in the summary, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific examples of the disclosure are described herein for illustrative purposes, various modifications are possible within the scope of the disclosure as those skilled in the relevant art will recognize.

[0054] These modifications can be made in light of the above detailed description of the disclosure. The terms used in the following claims should not be construed to limit the disclosure to the specific examples disclosed in the specification. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. A pixel unit readout circuit, comprising: A ramp generator with a ramp generator output; A first gain network is coupled to the output of the ramp generator and configured to provide a first variable comparator gain; A second gain network is coupled to the output of the ramp generator and configured to provide a second variable comparator gain. A first comparator has a second input coupled to the first gain network, and the first comparator further has a first input that is switchably coupled to a first bit line and switchably coupled to a second bit line; and A second comparator has a second input coupled to the second gain network, and the second comparator further has a first input that is switchably coupled to the first bit line and switchably coupled to the second bit line. During the first readout cycle, the first variable comparator gain is configured to be different from the second variable comparator gain, and the first input of each of the first and second comparators is selectively coupled to the first bit line and selectively decoupled from the second bit line; and During the second readout cycle, the first variable comparator gain is configured to be different from the second variable comparator gain, and the first input of each of the first comparator and the second comparator is selectively coupled to the second bit line and selectively decoupled from the first bit line.

2. The pixel unit readout circuit of claim 1, wherein during the first readout period and the second readout period, the first variable comparator gain is configured to be greater than the second variable comparator gain.

3. The pixel unit readout circuit of claim 1, wherein the first bit line and the second bit line are coupled to a pixel operating in a dual conversion gain (DCG) mode, and wherein the pixel unit readout circuit is configured to operate in a high conversion gain (HCG) mode during the first readout cycle and the second readout cycle.

4. The pixel unit readout circuit of claim 1, wherein during the third readout cycle, the first variable comparator gain is configured to be equal to the second variable comparator gain, the first input of the first comparator is selectively coupled to the first bit line, and the first input of the second comparator is selectively coupled to the second bit line.

5. The pixel unit readout circuit of claim 4, wherein during the fourth readout cycle, the first variable comparator gain is configured to be equal to the second variable comparator gain, the first input of the first comparator is coupled to the first bit line, and the first input of the second comparator is coupled to the second bit line.

6. The pixel unit readout circuit of claim 5, wherein the first variable comparator gain and the second variable comparator gain during the third readout cycle are configured to be greater than the first variable comparator gain and the second variable comparator gain during the fourth readout cycle.

7. The pixel unit readout circuit of claim 5, wherein the first bit line and the second bit line are coupled to a pixel operating in a dual conversion gain (DCG) mode, and wherein during the third readout cycle and the fourth readout cycle, the pixel unit readout circuit is configured to operate in a low conversion gain (LCG) mode.

8. The pixel unit readout circuit of claim 5, wherein the first bit line and the second bit line are coupled to a pixel operating in a single conversion gain mode, and wherein during all the first readout cycles, the second readout cycle, the third readout cycle, and the fourth readout cycle, the pixel unit readout circuit is configured to operate in a high conversion gain (HCG) mode or a low conversion gain (LCG) mode.

9. The pixel unit readout circuit according to claim 1, wherein the first gain network comprises: A first capacitor is coupled between the output of the ramp generator and the second input of the first comparator; and A second capacitor is selectively coupled between the second input of the first comparator and the output of the ramp generator or ground.

10. The pixel unit readout circuit according to claim 1, wherein the second gain network comprises: A third capacitor is coupled between the output of the ramp generator and the second input of the second comparator; and A fourth capacitor is selectively coupled between the second input of the second comparator and the output of the ramp generator or ground.

11. The pixel unit readout circuit according to claim 1, further comprising: A third gain network is coupled to the output of the ramp generator and configured to provide a third variable comparator gain; A fourth gain network is coupled to the output of the ramp generator and configured to provide a fourth variable comparator gain; A third comparator has a second input coupled to the third gain network, and the third comparator further has a first input that is switchably coupled to a third bit line and switchably coupled to a fourth bit line; and A fourth comparator has a second input coupled to the fourth gain network, and the fourth comparator further has a first input that is switchably coupled to the third bit line and switchably coupled to the fourth bit line. During the first readout cycle, the gain of the third variable comparator is configured to be different from the gain of the fourth variable comparator, and the first input of each of the third and fourth comparators is selectively coupled to the third bit line and selectively decoupled from the fourth bit line; and During the second readout cycle, the third variable comparator gain is configured to be different from the fourth variable comparator gain, and the first input of each of the third and fourth comparators is selectively coupled to the fourth bit line and selectively decoupled from the third bit line.

12. The pixel unit readout circuit of claim 1, wherein during the first readout period, the second bit line is configured to be clamped to reduce horizontal fixed-type noise associated with the second bit line.

13. The pixel unit readout circuit of claim 1, wherein during the second readout cycle, the first bit line is configured to be clamped to reduce horizontal fixed-type noise associated with the first bit line.

14. A method for operating a pixel unit readout circuit, comprising: A first gain network is coupled between the ramp generator and the first comparator, wherein the first gain network is configured to provide a first variable comparator gain; A second gain network is coupled between the ramp generator and the second comparator, wherein the second gain network is configured to provide a second variable comparator gain; During the first readout cycle— The first comparator and the second comparator are selectively coupled to the first bit line; Set the first variable comparator gain and the second variable comparator gain to different values; and Read the image signal from the first bit line; as well as During the second readout cycle— The first comparator and the second comparator are selectively coupled to the second bit line; Set the first variable comparator gain and the second variable comparator gain to different values; and The image signal is read from the second bit line.

15. The method of claim 14, further comprising: The first bit line and the second bit line are coupled to a pixel operating in dual conversion gain (DCG) mode; and During the first readout cycle and the second readout cycle— The pixel unit readout circuit is operated in high conversion gain HCG mode.

16. The method of claim 14, further comprising: During the third readout cycle— The first comparator is selectively coupled to the first bit line; The second comparator is selectively coupled to the second bit line; Set the first variable comparator gain and the second variable comparator gain to the same value; and The image signal is read from the first bit line and the second bit line.

17. The method of claim 16, further comprising: During the fourth readout cycle— Set the first variable comparator gain and the second variable comparator gain to the same value; and The image signal is read from the first bit line and the second bit line.

18. The method of claim 17, further comprising: The first bit line and the second bit line are coupled to a pixel operating in dual conversion gain (DCG) mode; and During the third readout cycle and the fourth readout cycle— The pixel unit readout circuit is operated in low conversion gain (LCG) mode.

19. The method of claim 17, further comprising: The first bit line and the second bit line are coupled to a pixel operating in single-conversion gain mode; and During all the first readout cycles, the second readout cycle, the third readout cycle, and the fourth readout cycle— The pixel unit readout circuit is operated in either high conversion gain HCG mode or low conversion gain LCG mode.

20. The method of claim 14, further comprising: During the first readout cycle and the second readout cycle— Set the gain of the first variable comparator to 8 or 16; and Set the gain of the second variable comparator to 1.

21. The method of claim 17, further comprising: During the third readout cycle— Set the gain of the first variable comparator and the gain of the second variable comparator to 2; and During the fourth readout cycle— Set the first variable comparator gain and the second variable comparator gain to 1.

22. The method of claim 14, further comprising: A third gain network is coupled between the ramp generator and the third comparator, wherein the third gain network is configured to provide a third variable comparator gain; A fourth gain network is coupled between the ramp generator and the fourth comparator, wherein the fourth gain network is configured to provide a fourth variable comparator gain; During the first readout cycle— The third comparator and the fourth comparator are selectively coupled to the third bit line; The third variable comparator gain and the fourth variable comparator gain are set to different values; and The image signal is read from the third bit line; as well as During the second readout cycle— The third comparator and the fourth comparator are selectively coupled to the fourth bit line; The third variable comparator gain and the fourth variable comparator gain are set to different values; and The image signal is read from the fourth bit line.

23. The method of claim 14, further comprising: During the first readout cycle— The second bit line is clamped to reduce horizontal fixed-type noise associated with the second bit line; and During the second readout cycle— The first bit line is clamped to reduce horizontal fixed-type noise associated with the first bit line.

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