Power supply circuit with low quiescent current in bypass mode

Abstract

A power supply circuit with low quiescent current for bypass mode. An example power supply circuit generally includes: a transistor; a switch node coupled to a source of the transistor; a power rail; a capacitor having a first terminal coupled to the power rail and a second terminal coupled to the switch node; a gate driver having an output coupled to a gate of the transistor, a first power input coupled to the power rail, and a second power input coupled to the switch node; a logic element having a first input coupled to the first terminal of the capacitor, a second input coupled to the second terminal of the capacitor, and a first output; and a pull-up circuit having a control input coupled to the second output of the logic element and an output coupled to the gate of the transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. patent application No. 17 / 649,527, filed on January 31, 2022, which is incorporated herein by reference in its entirety. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly to power supply circuits having low quiescent current when operating in bypass mode. Background Art

[0004] Ideally, a voltage regulator provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators can be classified as either linear or switching regulators. While linear regulators tend to be relatively compact, many applications can benefit from the improved efficiency of switching regulators. For example, linear regulators can be implemented as low-dropout (LDO) regulators. For example, switching regulators (also known as "switching converters" or "switchers") can be implemented as switch-mode power supplies (SMPSs), such as buck converters, boost converters, buck-boost converters, or charge pumps.

[0005] For example, a buck converter is a type of SMPS that typically includes: (1) a high-side switch coupled between a relatively high voltage rail and a switching node, (2) a low-side switch coupled between the switching node and a relatively low voltage rail, and (3) an inductor coupled between the switching node and a load (e.g., represented by a shunt capacitor element). The high-side and low-side switches are typically implemented using transistors, but the low-side switch can also be implemented using a diode.

[0006] A charge pump is a type of SMPS that typically includes at least one switching device that controls the connection of a supply voltage across a load via a capacitor. For example, in a voltage doubler (also known as a "multiply-by-two (X2) charge pump"), the charge pump circuit's capacitor can initially be connected across the supply, charging the capacitor to the supply voltage. The charge pump circuit can then be reconfigured to connect the capacitor in series with the supply and load, doubling the voltage across the load. This two-stage cycle is repeated at the charge pump's switching frequency. Charge pumps can be used to multiply or divide voltages by integers or fractional numbers, depending on the circuit topology.

[0007] A power management integrated circuit (PMIC) is used to manage the power scheme of a host system and may include and / or control one or more voltage regulators (e.g., a buck converter and / or a charge pump). A PMIC may be used in battery-powered devices such as mobile phones, tablets, laptops, wearables, etc. to control the flow and direction of power in the device. A PMIC may perform various functions for the device, such as DC-to-DC conversion (e.g., using a voltage regulator as described above), battery charging, power source selection, voltage scaling, power sequencing, etc. Summary of the Invention

[0008] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desirable properties. Without limiting the scope of the present disclosure as expressed in the appended claims, some features are briefly discussed below. After considering this discussion, and particularly after reading the section entitled "Detailed Description," one will understand how the features of the present disclosure provide the advantages described herein.

[0009] Certain aspects of the present disclosure generally relate to a power supply circuit having low quiescent current when operating in a bypass mode, the low quiescent current being achieved based on a discharged boot capacitor of the power supply circuit.

[0010] Certain aspects of the present disclosure relate to a power supply circuit. The power supply circuit generally includes: a power transistor; a switch node coupled to a source of the power transistor; a power rail; a capacitor having a first terminal coupled to the power rail and a second terminal coupled to the switch node; a gate driver having an output coupled to the gate of the power transistor, a first power input coupled to the power rail, and a second power input coupled to the switch node; a logic element having a first input coupled to the first terminal of the capacitor, a second input coupled to the second terminal of the capacitor, and a first output; and a pull-up circuit having a control input coupled to the second output of the logic element and an output coupled to the gate of the power transistor.

[0011] Certain aspects of the present disclosure relate to a battery charging circuit including the power supply circuit described herein, the battery charging circuit further comprising: an inductor having a first terminal coupled to the switch node; and a switch coupled between a second terminal of the inductor and a node for coupling to a battery.

[0012] Certain aspects of the present disclosure relate to a method of operating a power supply circuit. The method generally includes: enabling a bypass mode for the power supply circuit; in response to the enabling, discharging a capacitor coupled across a power input of a gate driver for driving a gate of a power transistor; determining that the capacitor has been discharged; and in response to the determination, pulling up the gate of the power transistor to turn on the power transistor and enter the bypass mode for the power supply circuit.

[0013] Certain aspects of the present disclosure relate to a method of operating a power supply circuit. The method generally includes: enabling a bypass mode for the power supply circuit; in response to the enabling, determining that a capacitor coupled across a power input of a gate driver for driving a gate of a power transistor is discharged; and in response to the determination, pulling up the gate of the power transistor to turn on the power transistor and enter the bypass mode for the power supply circuit.

[0014] To accomplish the foregoing and related ends, one or more aspects include the features fully described below and particularly pointed out in the claims. The following description and accompanying drawings set forth in detail certain illustrative features of these one or more aspects. However, these features are indicative of only some of the various ways in which the principles of the various aspects may be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order that the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description, briefly summarized above, may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only certain typical aspects of the disclosure and are therefore not to be considered limiting of its scope, as the description may admit to other equally effective aspects.

[0016] Figure 1 is a block diagram of an example device including a power management system including power supply circuitry and battery charging circuitry in which aspects of the present disclosure may be implemented.

[0017] Figure 2 is a schematic diagram of an example power supply circuit in which aspects of the present disclosure may be implemented.

[0018] Figure 3A is a block diagram of an example power supply circuit capable of operating in bypass mode with low quiescent current by using a level shifter to discharge a boot capacitor, in accordance with certain aspects of the present disclosure.

[0019] Figure 3B is a block diagram of an example power supply circuit capable of operating in a bypass mode with a low quiescent current, the power supply circuit having a current sink for discharging a startup capacitor, according to certain aspects of the present disclosure.

[0020] Figure 4According to certain aspects of the present disclosure Figure 3A Schematic diagram of the power supply circuit.

[0021] Figure 5 is an example of some aspects of the present disclosure Figure 4 A timing diagram of a power supply circuit entering a bypass mode, operating in the bypass mode, and exiting the bypass mode.

[0022] Figure 6 and Figure 7 is a flow chart of example operations for operating a power supply circuit according to certain aspects of the present disclosure.

[0023] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0024] Certain aspects of the present disclosure provide a power supply circuit having a low quiescent current (e.g., <10 μA) when operating in bypass mode and a method of operating such a power supply circuit. The power supply circuit may include a buck converter having a high-side power transistor, a low-side power transistor, a gate driver for each power transistor, a startup capacitor, and a pull-up circuit. The low quiescent current can be achieved because the startup capacitor is discharged. For certain aspects, the startup capacitor can be determined to have a charge when the bypass mode is first entered, and in this case, the power supply circuit can discharge the startup capacitor before entering the bypass mode. In other aspects, the startup capacitor can be determined to have been discharged when entering the bypass mode. In either scenario, the power supply circuit can also cause: (1) the output of the gate driver of the high-side power transistor to enter a high impedance state, and (2) the gate of the high-side power transistor to be pulled up using the pull-up circuit to turn on the high-side power transistor without using the gate driver.

[0025] The various aspects of the disclosure are described more fully below with reference to the accompanying drawings. However, the disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the disclosure. Rather, these aspects are provided so that the disclosure will be thorough and complete, and the scope of protection of the disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, it will be understood by those skilled in the art that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether it is implemented independently or in combination with any other aspect of the disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the disclosure is intended to cover such devices or methods implemented using other structures, functions, or structures and functions in addition to or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of the claims.

[0026] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0027] As used herein, the term "connected with" in various tenses of the verb "connect" may mean that element A is directly connected to element B or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the context of electronic components, the term "connected with" may also be used herein to mean that wires, traces, or other conductive materials are used to electrically connect element A and element B (and any components electrically connected therebetween).

[0028] Example device

[0029] It should be understood that various aspects of the present disclosure can be used in various applications. Although the present disclosure is not limited in this respect, the circuits disclosed herein can be used in any of a variety of suitable devices, such as power supplies, battery charging circuits or power management circuits for communication systems, video codecs, audio equipment (such as music players and microphones), televisions, camera equipment, and test equipment (such as oscilloscopes). By way of example only, communication systems intended to be included within the scope of the present disclosure include cellular radiotelephone communication systems, satellite communication systems, two-way radio communication systems, one-way pagers, two-way pagers, personal communication systems (PCS), personal digital assistants (PDAs), and the like.

[0030] Figure 1An example device 100 is illustrated in which aspects of the present disclosure may be implemented. Device 100 may be a battery-powered device such as a cellular phone, a PDA, a handheld device, a wireless device, a laptop computer, a tablet computer, a smartphone, a wearable device, or the like.

[0031] Device 100 may include a processor 104 that controls the operation of device 100. Processor 104 may also be referred to as a central processing unit (CPU). Memory 106, which may include both read-only memory (ROM) and random access memory (RAM), provides instructions and data to processor 104. A portion of memory 106 may also include non-volatile random access memory (NVRAM). Processor 104 typically performs logical and arithmetic operations based on program instructions stored in memory 106.

[0032] In some aspects, the device 100 may also include a housing 108, which may include a transmitter 110 and a receiver 112 to allow data to be sent and received between the device 100 and a remote location. In some aspects, the transmitter 110 and the receiver 112 may be combined into a transceiver 114. One or more antennas 116 may be attached or otherwise coupled to the housing 108 and electrically connected to the transceiver 114. The device 100 may also include (not shown) multiple transmitters, multiple receivers, and / or multiple transceivers.

[0033] The device 100 may also include a signal detector 118 that can be used to detect and quantify the signal level received by the transceiver 114. The signal detector 118 can detect signal parameters such as total energy, energy per subcarrier per symbol, and power spectral density, among other signal parameters. The device 100 may also include a digital signal processor (DSP) 120 for processing signals.

[0034] The device 100 may also include a battery 122 that can be used to power various components of the device 100 (e.g., when another power source (such as a wall adapter or wireless charger) is not available). The battery 122 may include a single cell or multiple cells connected in series. The device 100 may also include a power management system 123 for managing power from the battery 122, the wall adapter, and / or the wireless charger to the various components of the device 100. The power management system 123 may perform various functions for the device, such as DC-to-DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. In certain aspects, the power management system 123 may include a power management integrated circuit (power management IC or PMIC) 124 and one or more power circuits that can be controlled by the PMIC, such as a battery charger 125. For certain aspects, at least a portion of one or more of these power circuits may be integrated into the PMIC 124. The PMIC 124 and the one or more power supply circuits may include at least a portion of a switch mode power supply (SMPS) circuit, which may be implemented by any of a variety of suitable SMPS circuit topologies, such as a buck converter, a buck-boost converter, a three-level buck converter, or a charge pump, such as a multiply-by-two (X2) or multiply-by-three (X3) charge pump.

[0035] The various components of the device 100 may be coupled together via a bus system 126 , which may include a power bus, a control signal bus, and / or a status signal bus in addition to a data bus.

[0036] Example Battery Charging Circuit

[0037] Figure 2 is a schematic diagram of an example battery charging circuit 200. The battery charging circuit 200 may include a switch mode power supply (SMPS), a gate driver 218, a battery switch 220 (e.g., transistor QBAT1, also referred to as a "battery transistor" or "BAT FET"), a reverse blocking transistor 222 (labeled "Q1"), and control logic 224. The battery charging circuit 200 may receive power at an input power node 210 (labeled "CHG_IN" for a charger input node) from one of a number of potential power sources, such as a wall adapter or other power cable (e.g., a universal serial bus (USB) adapter) connected via a USB port 226 or a wireless charger (not shown).

[0038] The SMPS may be implemented by any of a variety of suitable switching regulators, such as a two-level buck converter (e.g. Figure 22 and Q3 and an inductor L1). The SMPS may receive power via an input power node 210 located at a power rail 211 (labeled “CHG_MID”) coupled between a reverse-blocking transistor 222 and the drain of transistor Q2. The SMPS may have a switch node 214 (labeled “VSW_CHG”) coupled to the source of transistor Q2 (also referred to as the “high-side transistor”), the drain of transistor Q3 (also referred to as the “low-side transistor”), and the first terminal of inductor L1. Another power rail 212 (labeled “BOOT_CAP”) may have a supply voltage generated internally (e.g., from the CHG_MID rail). The supply voltage of power rail 212 may be limited (e.g., BOOT_CAP-VSW_CHG≤5V). A capacitor Cboot may be coupled between power rail 212 and switch node 214. The output of the SMPS at system power node 216 (labeled "VPH_PWR" and coupled to the second terminal of inductor L1) can provide power to one or more core PMICs (not shown) and / or other circuits within a device (e.g., device 100). As shown, a battery switch 220 can be coupled between system power node 216 and a node 230 (labeled "VBAT_PWR") for coupling to a battery 228. The battery switch 220 can be driven by a gate driver that can be controlled by the BAT FET control logic, as shown. For certain aspects, the BAT FET control logic can be part of the control logic 224.

[0039] The control logic 224 may include a level shifter and a controllable pull-up circuit (relative to the Figure 3A and Figure 4 10). The control logic 224 may control the gate driver 218, which may drive the gates of the power transistors Q2 and Q3 that implement the SMPS. The control logic 224 may also control the reverse blocking transistor 222, the battery switch 220, and other components. It may be desirable to operate the battery charging circuit 200 in a “bypass mode,” as described below, such as in a factory where a device (e.g., device 100) having the battery charging circuit 200 is manufactured. For example, when the battery charging circuit 200 is operated in bypass mode, the control logic 224 may turn off the battery switch 220 and transistor Q3 and turn on the reverse blocking transistor 222 and transistor Q2, so that current flows from the input power node 210 to the system power node 216 and not to the battery 228.

[0040] Example power supply circuit with low quiescent current in bypass mode

[0041] Manufacturers of devices with battery charging circuits and other power supply circuits can test current leakage and sleep current in these power supply circuits. For testing, the device can be placed in "bypass mode." When the device is in bypass mode, input power node 210 is connected to system power node 216, effectively providing direct power from the input power node to the system power node and bypassing the SMPS. Consequently, the reverse-blocking transistor (e.g., reverse-blocking transistor 222) and the high-side power transistor (e.g., power transistor Q2) can be fully turned on to apply the supply voltage (e.g., the Universal Serial Bus (USB) voltage, referred to as "VBUS") at the input power node (e.g., input power node 210) to an internal device power node (e.g., system power node 216), allowing manufacturers to measure current leakage in the power supply circuit at the factory. The current consumed by the power supply circuit itself during bypass mode testing can provide a source of error in the device's current leakage measurement. Therefore, bypass mode specifications may require that the device have a relatively low quiescent current (e.g., <10 μA) when in bypass mode to minimize (or at least reduce) the current consumption of the power supply circuit during testing.

[0042] The reverse blocking transistor is not a switching transistor, and its gate drive can be simpler than the gate drive of the high-side power transistor due to having fewer circuit connections (and therefore less current consumption). Therefore, the reverse blocking transistor may pose fewer challenges for meeting the specified quiescent current. In contrast, when the high-side power transistor is turned on in bypass mode, other components (e.g., components connected through the boot capacitor Cboot) may draw additional current, thereby increasing the total quiescent current of the device. One method of meeting the specified quiescent current involves reducing the current of individual components coupled to the high-side power transistor. However, this approach may introduce circuit complexity, may consume more circuit area, and / or may negatively affect the performance of the power supply circuit in mission mode (e.g., normal operation other than bypass mode or other test modes). Therefore, alternative techniques for reducing the quiescent current of devices operating in bypass mode may be desired.

[0043] Therefore, certain aspects of the present disclosure provide apparatus and techniques for reducing the quiescent current of a device operating in bypass mode by discharging capacitor Cboot (or by determining that capacitor Cboot has been discharged) before entering bypass mode. By discharging capacitor Cboot, the current drawn from capacitor Cboot (and components connected to it) can be eliminated (or at least reduced). In some aspects, the techniques presented herein can be implemented using existing circuitry in a device.

[0044] Figure 3AFIG2 is a block diagram of an example power supply circuit 300A capable of operating in bypass mode with low quiescent current (e.g., <10 μA) according to certain aspects of the present disclosure. The power supply circuit 300A may generally include back-to-back transistors M0 and M1, a power transistor Q2, a capacitor Cboot, a level shifter 302, a gate driver 304, logic 306, and a pull-up circuit 308, among other components (e.g., Figure 2 components of the battery charging circuit).

[0045] The power supply circuit 300A may have a power node 310 (labeled "VARB_CHG") coupled to the source of transistor M0, which may be an n-type transistor, as shown. In some cases, the voltage on power node 310 may be internally generated and may have a finite voltage. The drain of transistor M0 may be coupled to the drain of transistor M1, as shown. The power supply circuit 300A may also include a power rail 314 and a switch node 214. The power rail 314 (labeled "BOOT_CAP" and similar to Figure 2 The power rail 212 in FIG. 2 is coupled to the source of transistor M1. In this manner, back-to-back transistors M0 and M1 are coupled between power node 310 and power rail 314. Switch node 312 (labeled “VSW_CHG” and similar to FIG. Figure 2 2 (a switching node 214 in FIG1 ) is coupled to the source of power transistor Q2. The drain of power transistor Q2 may be coupled to another power rail 211 (labeled “CHG_MID”), which in some cases may have a higher voltage than the voltage of power rail 314. Power transistor Q2 may be referred to as a “high-side” or “HS” transistor.

[0046] The output of the power supply circuit 300A may be coupled to the switch node 312 (eg, through the inductor L1, not in FIG. 1 ). Figure 3A ). Power supply circuit 300A may also include a “low side” or “LS” transistor Q3 having a drain coupled to switch node 312 and a source coupled to a reference potential node (e.g., electrical ground) for power supply circuit 300A.

[0047] like Figure 3A As illustrated in FIG, capacitor Cboot may have a first terminal coupled to power rail 314 and a second terminal coupled to switch node 312. Gate driver 304 may have an output coupled to the gate of power transistor Q2, a first power input coupled to power rail 314, and a second power input coupled to switch node 312. In some aspects, gate driver 304 may include a p-type transistor (e.g., a PFET) to place the output of gate driver 304 in a high impedance state when capacitor Cboot is discharged (as described below with respect to FIG). Figure 4as described).

[0048] Logic 306 may have a first input coupled to a first terminal of capacitor Cboot, a second input coupled to a second terminal of capacitor Cboot, and one or more outputs. Figure 3A , logic 306 has one output coupled to a control input of pull-up circuit 308 and another output coupled to a control input of level shifter 302. For certain aspects, logic 306 may be control logic (e.g., using level shifter 302 and gate driver 304) for controlling the operation of power transistors Q2 and Q3. Figure 2 For other aspects, logic 306 may be external to, but communicatively coupled to, the control logic.

[0049] Pull-up circuit 308 may also have an output coupled to the gate of power transistor Q2 and a power input coupled to another power rail (labeled “CP” for a charge pump) configured to have a higher voltage than the voltage of power rail 314 (e.g., 5V higher than the battery voltage, where the higher voltage may be generated using a multiplying charge pump). Pull-up circuit 308 may be referred to as a “HS gate pull-up circuit” because it may be configured to pull up the voltage at the gate of HS power transistor Q2, thereby turning on power transistor Q2.

[0050] Level shifter 302 may have a signal input 316 (labeled "HSON" for a high-side transistor turn-on signal), a control input coupled to an output of logic 306, an output coupled to an input of gate driver 304, a first power input coupled to power rail 314, and a second power input coupled to switch node 312. Signal input 316 may be used to control the state of power transistor Q2 during normal operation, where "HSON=0" indicates that signal input 316 is logic low during bypass mode. Also during bypass mode, for certain aspects, logic 306 may be configured to control level shifter 302 (via a control input to the level shifter) to discharge capacitor Cboot (e.g., via a current sink or other path internal to the level shifter to ground) and, in response to capacitor Cboot being discharged, enable pull-up circuit 308 (via a control input to the pull-up circuit) to output a voltage to turn on power transistor Q2. Additionally, when the capacitor Cboot is discharged in the bypass mode, the output of the gate driver 304 may be placed in a high impedance state (eg, via a circuit such as Figure 4 The transistor logic element shown or via another output terminal from the logic element 306).

[0051] In some aspects, logic 306 may be further configured to turn on reverse-blocking transistor Q1 (in addition to controlling pull-up circuit 308 to turn on power transistor Q2 during bypass mode), such that input power node 210 is effectively shorted to switch node 312 (and to the output of power circuit 300A via inductor L1).

[0052] Figure 4 is realized Figure 3A Schematic diagram of an example power circuit 400 of the power circuit 300A. The power circuit 400 may include back-to-back transistors M0 and M1, a power transistor Q2, a capacitor Cboot, a level shifter 302, a gate driver 304, a logic element 306, and a pull-up circuit 308, as described above with respect to FIG. Figure 3A described.

[0053] According to certain aspects, gate driver 304 may include a first n-type transistor Q6 having a drain coupled to the output of gate driver 304 and a source coupled to the second power input of gate driver 304, a first p-type transistor Q7 having a drain coupled to the output of gate driver 304 and the drain of first n-type transistor Q6, and a second p-type transistor Q8 having a source coupled to the source of first p-type transistor Q7 and a drain coupled to the first power input of gate driver 304. In certain aspects, second p-type transistor Q8 may be configured to be turned off and effectively place the output of gate driver 304 in a high impedance state when capacitor Cboot is discharged.

[0054] According to certain aspects and Figure 4 As shown, gate driver 304 may also include a second n-type transistor Q9. Second n-type transistor Q9 may have a drain coupled to the gate of second p-type transistor Q8, a gate coupled to power rail 314 (e.g., via a resistor), and a source coupled to switch node 312.

[0055] According to certain aspects, logic 306 may include a comparator having a first input coupled to a first terminal of capacitor Cboot and a second input coupled to a second terminal of capacitor Cboot. In certain aspects, logic 306 may be configured to activate an output signal in response to capacitor Cboot being discharged. In certain aspects, logic 306 may be further configured to enable pull-up circuit 308 to output a voltage to turn on power transistor Q2 based on the activated output signal.

[0056] In some aspects, the comparator may include a Schmitt trigger 406. In this case, the comparator may also include transistors Q4 and Q5 and current sinks 402 and 404. Transistor Q4 may have a source coupled to a first terminal of capacitor Cboot and a drain coupled to a gate of transistor Q4. Current sink 402 may be coupled between the drain of first transistor Q4 and a reference potential node (e.g., electrical ground) for power supply circuit 400. Transistor Q5 may have a source coupled to a second terminal of capacitor Cboot, a gate coupled to the gate and drain of transistor Q4, and a drain coupled to an input of Schmitt trigger 406. Current sink 404 may be coupled between the drain of transistor Q5 and the reference potential node.

[0057] In some aspects, logic 306 may include additional circuitry, such as inverters 408 and 410 , a logic NOR gate 412 , and a multiplexer 414 .

[0058] Inverter 408 may have an input (labeled "skip") that may indicate whether pulse skipping mode is enabled or disabled for power supply circuit 400. Inverter 410 may have an input (labeled "dly," but also referred to as "factory_byp_ena_dly") that provides a delayed version of a control signal (labeled "factory_byp_ena") indicating that factory bypass mode is enabled. The delay may provide time for logic 306 to determine that capacitor Cboot has discharged before instructing pull-up circuit 308 to turn on power transistor Q2. NOR gate 412 may have a first input coupled to the output of inverter 410 and a second input coupled to the output of Schmitt trigger 406, as shown.

[0059] Multiplexer 414 may have a first input coupled to the output of inverter 408 and a second input coupled to the output of NOR gate 412. Multiplexer 414 may also have a control input (labeled "factory_byp_ena") that indicates whether factory bypass mode is enabled and selects between the first and second inputs of multiplexer 414. When the factory_byp_ena signal is high (e.g., a logic 1) and when the output of Schmitt trigger 406 is low (e.g., a logic 0), the second input of multiplexer 414 will be high. Otherwise, the second input of multiplexer 414 will be low. When capacitor Cboot is not discharged (e.g., when the voltage of capacitor Cboot is greater than the voltage at switch node 312), the output of Schmitt trigger 406 will be low. The output signal of multiplexer 414 may serve as a control input to level shifter 302. For example, the multiplexer 414 may output a high signal to instruct the level shifter 302 to discharge the capacitor Cboot (eg, act as a current sink).

[0060] According to certain aspects, the pull-up circuit 308 may have a power input coupled to another power rail 420, which is configured to have a higher voltage than the voltage of the power rail 314 (e.g., 5V higher than the battery voltage Vbat). In certain aspects, the higher voltage of the other power rail 420 may be generated by a charge pump circuit (e.g., a multiplying charge pump). As shown, the pull-up circuit 308 may include a current mirror 422, transistors Q10, Q11, and Q12, and current sinks 424 and 426. The current mirror 422 may have a first branch and a second branch, wherein the first branch and the second branch are coupled to the power input of the pull-up circuit 308. The transistor Q10 may have a source coupled to the second branch of the current mirror 422 and a drain coupled to the output of the pull-up circuit 308. The transistor Q11 may have a drain coupled to the first branch of the current mirror 422 and a gate coupled to the control input of the pull-up circuit 308. A current sink 424 may be coupled between the source of transistor Q11 and a reference potential node for the power supply circuit (e.g., electrical ground). Transistor Q12 may have a drain coupled to the gate of transistor Q10 and a gate coupled to a control input (labeled "cboot_eq_vsw") of pull-up circuit 308. A current sink 426 may be coupled between the source of third transistor Q12 and a reference potential node for the power supply circuit 400. The control input of pull-up circuit 308 may be coupled to the output of logic element 306 (e.g., "cboot_eq_vsw" at the output of Schmitt trigger 406).

[0061] In some aspects, the pull-up circuit 308 may further include another transistor Q13, which may be an n-type transistor. The transistor Q13 may have a drain coupled to the power supply input of the pull-up circuit 308, a source coupled to the first branch and the second branch of the current mirror 422, and a gate coupled to the gate of the transistor Q10 and the drain of the transistor Q12.

[0062] The power supply circuit 400 may include a low-side transistor Q3 having a drain coupled to the switching node 312 and a source coupled to electrical ground, as shown. The low-side transistor Q3 may have a gate coupled to the output of a gate driver 430. The gate driver 430 may have a first power input (labeled "VARB_CHG" and coupled to the power node 310), a second power input (coupled to electrical ground), and a signal input (labeled "LSON"). Figure 4 The middle signal input terminal being equal to logic 0 ("LSON=0") indicates that the low-side transistor Q3 is turned off during bypass mode. In addition, the back-to-back transistors M0 and M1 can be turned off during bypass mode (e.g., Figure 4 ), so that power rail 314 does not receive power from the internal power supply (eg, VARB_CHG) and capacitor Cboot can be discharged.

[0063] Figure 5 is an example of some aspects of the present disclosure Figure 4 A timing diagram 500 of the power supply circuit 400 entering the bypass mode, operating in the bypass mode, and exiting the bypass mode is shown.

[0064] Before the power supply circuit 400 has entered the bypass mode, the capacitor Cboot may have a non-zero voltage (e.g., "Vcboot"), which may be, for example, equal to the switch voltage Vsw plus 5V, as shown. At time t1, the factory bypass mode enable signal "factory_byp_ena" may transition from low (e.g., logic 0) to high (e.g., logic 1), thereby indicating that the power supply circuit 400 has enabled the factory bypass mode. For certain aspects, after a delay time Δt1 (e.g., 20 μs), the signal "factory_byp_ena_dly" (e.g., a delayed version of the factory bypass mode enable signal) may transition from low to high at time t2. This delay may provide time for the logic element 306 to determine that the capacitor Cboot has been discharged (e.g., has a voltage equal to Vsw, or at least the difference between the voltages is less than a threshold) before the logic element 306 instructs the pull-up circuit 308 to turn on the power transistor Q2.

[0065] At time t2, the signal "ena_cboot_lvlshift_disch_current" may transition from low to high, thereby instructing the level shifter 302 (or another current sink circuit) to discharge the capacitor Cboot. As shown, in response to the transition of the signal "ena_cboot_lvlshift_disch_current", the voltage of the capacitor Cboot begins to decrease from Vsw + 5V to Vsw as the capacitor Cboot discharges. However, in other examples, the logic 306 may determine that the capacitor Cboot has been discharged. In this case, the signal "ena_cboot_lvlshift_disch_current" may not transition from low to high.

[0066] At time t3, when capacitor Cboot has been discharged, the output of gate driver 304 may enter a high impedance state, and signal "Q4 state (H = Q4 on)" may transition from high to low, thereby causing the comparator output to change state, indicating that capacitor Cboot has been discharged, and controlling multiple components to prepare for and enter bypass mode. Therefore, at time t3, signal "cboot_eq_vsw" may transition from low to high, which may cause power supply circuit 400 to enable pull-up circuit 308 to pull up the voltage at the gate of power transistor Q2, and may cause signal "ena_cboot_lvlshift_disch_current" to transition from high to low, thereby ending the discharge of capacitor Cboot. In addition, at time t3, by causing signal "ena_Q1_gate_pullup" to transition from low to high, power supply circuit 400 may indicate to pull up the voltage at the gate of reverse-blocking transistor Q1, thereby turning on transistor Q1.

[0067] Therefore, as illustrated by the bottom two signals of the timing diagram 500, after entering the bypass mode at time t3, the voltage at the gate of the reverse blocking transistor Q1 and the gate of the power transistor Q2 begins to ramp up. The voltage at the gate of the reverse blocking transistor Q1 and the gate of the power transistor Q2 may continue to ramp up until the voltage reaches a predefined voltage (e.g., the battery voltage VBAT plus 5V). Also at time t3, the system power node (e.g., Figure 2 The voltage at the system power node 216 in FIG. 216 , labeled “VPH_PWR,” may transition from the battery voltage (e.g., VBAT) to the USB voltage labeled “VBUS” (e.g., from Figure 2 Input power node 210 in)).

[0068] At time t4, the signal "factory_byp_ena" may transition from high to low, indicating that the power supply circuit 400 has disabled the bypass mode. At time t4, because the power supply circuit 400 has indicated that the bypass mode has been disabled, the signal "cboot_eq_vsw" may transition from high to low, indicating that the pull-up circuit 308 stops pulling up the voltage at the gate of the power transistor Q2. Also at time t4, the signal "ena_Q1_gate_pullup" may transition from high to low, indicating that the power supply circuit 400 stops pulling up the voltage at the gate of the reverse-blocking transistor Q1.

[0069] After a delay time Δt1, the signal "factory_byp_ena_dly" (e.g., a delayed version of the factory bypass mode enable signal) may transition from high to low at time t5. Also at time t5, the signal "Q4 state (H=Q4 on)" may transition from low to high, thereby indicating that the power supply circuit 400 is no longer operating in the bypass mode.

[0070] In some aspects, at time t5, the signal "ena_Q2_gate_pulldown_oneshot" may transition from low to high. After time Δt2, the signal "ena_Q2_gate_pulldown_oneshot" may transition from high to low, making the signal pulsed. The signal "ena_Q2_gate_pulldown_oneshot" may instruct the pull-down circuit to quickly pull down the voltage at the gate of the power transistor Q2, thereby turning it off. As shown, at time t5, the voltage at the gate of the reverse blocking transistor Q1 and the gate of the power transistor Q2 may drop to the voltage level of the gate before the power supply circuit 400 enters the bypass mode. Additionally, the voltage at the system power node (e.g., the system power node 216) may increase from (e.g., Figure 2 The USB voltage at the input power node 210 in FIG. 1 is converted to the battery voltage (eg, VBAT).

[0071] Figure 3B is a block diagram of an example power supply circuit 300B with additional current sink circuitry capable of operating in a bypass mode with reduced current according to certain aspects of the present disclosure. The power supply circuit 300B may be similar to Figure 3A , but with a current sink 318 separate from the level shifter 302.

[0072] In some aspects, the level shifter 302 may include a current sink and may be configured to discharge the capacitor Cboot via the current sink when the control input of the level shifter 302 is activated by the logic element 306. However, in some other aspects, the current sink 318 may be an additional current sink separate from the level shifter 302, as shown. In this case, the current sink 318 may be selectively coupled to the first terminal of the capacitor Cboot (or otherwise effectively selectively enabled). Additionally, during the bypass mode, the logic element 306 may be configured to effectively enable the current sink 318 via the first output of the logic element 306 to discharge the capacitor Cboot, and in response to the capacitor Cboot being discharged, enable the pull-up circuit 308 to output a voltage to turn on the power transistor Q2.

[0073] Example Operation

[0074] Figure 6 is a flow chart of example operations 600 for operating a power supply circuit according to certain aspects of the present disclosure. Operations 600 may be performed by a power supply circuit (e.g., Figure 3A Power supply circuit 300A, Figure 3B Power supply circuit 300B or Figure 4 The power supply circuit 400) is used to perform.

[0075] Operations 600 may begin at block 602, where a power supply circuit enables a bypass mode for the power supply circuit. At block 604, the power supply circuit may discharge a capacitor (e.g., capacitor Cboot) coupled across a power input (e.g., a power input coupled to power rail 314 and switch node 312) of a gate driver (e.g., gate driver 304) for driving the gate of a power transistor (e.g., power transistor Q2) in response to the enabling at block 602. At block 606, the power supply circuit (and more specifically, logic, such as logic 306) may determine that the capacitor has been discharged. At block 608, in response to the determination at block 606, the power supply circuit (and more specifically, a pull-up circuit, such as pull-up circuit 308) may pull up the gate of the power transistor to turn on the power transistor and enter the bypass mode for the power supply circuit.

[0076] According to certain aspects, operation 600 may also involve activating a control signal (eg, signal “cboot_eq_vsw”) to effectively enable a current sink (eg, level shifter 302 or current sink 318 ) such that the current sink begins discharging the capacitor.

[0077] According to certain aspects, operation 600 may also involve activating a control signal (e.g., signal "cboot_eq_vsw") for a level shifter (e.g., level shifter 302) across which a capacitor is coupled for a power supply input (e.g., a power supply input coupled to power rail 314 and switch node 312), so that the level shifter begins to discharge the capacitor. In this case, the power supply circuit may also deactivate an input signal (e.g., signal "HSON") for the level shifter in response to the activation.

[0078] According to certain aspects, operations 600 also involve turning on a power supply coupled to an input power node (eg, Figure 2 A reverse blocking transistor (eg, a transistor connected to the input power node 210 in FIG. 2 ) and the drain of the power transistor (eg, which is coupled to “CHG_MID”) is connected to the input power node 210 in FIG. Figure 2 The reverse blocking transistor 222 in FIG. 2 is used to enter a bypass mode for the power supply circuit.

[0079] According to certain aspects, operations 600 may also involve causing the output of the gate driver to enter a high impedance state based on the discharge at block 604 and before pulling up the gate of the power transistor at block 608 .

[0080] According to certain aspects, operation 600 may also involve activating an output signal (e.g., signal "cboot_eq_vsw") in response to determining that the capacitor has been discharged. In this case, pulling up the gate of the power transistor may involve enabling a pull-up circuit (e.g., pull-up circuit 308) to output a voltage to turn on the power transistor based on the activated output signal.

[0081] For certain aspects, determining that the capacitor has been discharged at block 606 may involve comparing a first voltage at a first terminal of the capacitor to a second voltage at a second terminal of the capacitor, and determining that the capacitor has been discharged when a difference between the first voltage and the second voltage is less than a threshold voltage. The first terminal of the capacitor may be coupled to a power rail (e.g., power rail 314), and the second terminal of the capacitor may be coupled to a source of the power transistor (e.g., at switch node 214 or 312).

[0082] According to certain aspects, the operation 600 may also involve the power supply circuit disconnecting the inductor (eg, Figure 2 A first terminal of the inductor L1 in FIG. 1 is connected to a node (eg, Figure 2 230) between the switch (eg, Figure 2 220 in the battery switch), a second terminal of the inductor is coupled to the source of the power transistor (eg, at switching node 214 or 312).

[0083] Figure 7 is a flow chart of example operations 700 for operating a power supply circuit according to certain aspects of the present disclosure. Operations 700 may be performed by a power supply circuit (e.g., Figure 3A Power supply circuit 300A, Figure 3B Power supply circuit 300B or Figure 4 The power supply circuit 400) is used to perform.

[0084] Operations 700 may begin at block 702, where a power supply circuit enables a bypass mode for the power supply circuit. At block 704, in response to the enabling at block 702, the power supply circuit may determine that a capacitor (e.g., capacitor Cboot) coupled across a power input (e.g., a power input coupled to power rail 314 and switch node 312) of a gate driver (e.g., gate driver 304) for driving the gate of a power transistor (e.g., power transistor Q2) is discharged. At block 706, in response to the determination at block 704, the power supply circuit (and more specifically, a pull-up circuit, such as pull-up circuit 308) may pull up the gate of the power transistor to turn on the power transistor and enter the bypass mode for the power supply circuit.

[0085] According to certain aspects, operations 700 may also involve turning on a power supply coupled to an input power node (eg, Figure 2 A reverse blocking transistor (eg, Figure 2 The reverse blocking transistor 222 in FIG. 2 is used to enter a bypass mode for the power supply circuit.

[0086] According to certain aspects, operations 700 may also involve causing the output of the gate driver to enter a high impedance state based on the capacitor being discharged (eg, as determined at block 704 ) and before pulling up the gate of the power transistor at block 706 .

[0087] According to certain aspects, operation 700 may also involve activating an output signal (e.g., signal “cboot_eq_vsw”) in response to the determination at block 704. In this case, pulling up the gate of the power transistor at block 706 may include enabling a pull-up circuit (e.g., pull-up circuit 308) to output a voltage to turn on the power transistor based on the activated output signal.

[0088] For certain aspects, determining that the capacitor is discharged can involve comparing a first voltage at a first terminal of the capacitor to a second voltage at a second terminal of the capacitor (e.g., by logic, such as logic 306), and determining that a difference between the first voltage and the second voltage is less than a threshold voltage. The first terminal of the capacitor can be coupled to a power rail (e.g., power rail 314), and the second terminal of the capacitor can be coupled to a source of the power transistor (e.g., at switch node 214 or 312).

[0089] Example aspects

[0090] In addition to the above aspects, specific combinations of the aspects are also within the scope of the present disclosure, and details of some of the specific combinations are as follows:

[0091] Aspect 1: A power supply circuit, comprising: a power transistor; a switch node, the switch node being coupled to the source of the power transistor; a power rail; a capacitor, the capacitor having a first terminal coupled to the power rail and a second terminal coupled to the switch node; a gate driver, the gate driver having an output terminal coupled to the gate of the power transistor, a first power input terminal coupled to the power rail, and a second power input terminal coupled to the switch node; a logic element, the logic element having a first input terminal coupled to the first terminal of the capacitor, a second input terminal coupled to the second terminal of the capacitor, and a first output terminal; and a pull-up circuit, the pull-up circuit having a control input terminal coupled to the second output terminal of the logic element and an output terminal coupled to the gate of the power transistor.

[0092] Aspect 2: The power supply circuit according to Aspect 1 further includes a level shifter, wherein the level shifter has a signal input terminal, a control input terminal, an output terminal coupled to the input terminal of the gate driver, a first power input terminal coupled to the power rail, and a second power input terminal coupled to the switching node, wherein: the first output terminal of the logic element is coupled to the control input terminal of the level shifter; and during the bypass mode, the logic element is configured to control the level shifter to discharge the capacitor, and enable the pull-up circuit to output a voltage to turn on the power transistor in response to the capacitor being discharged.

[0093] Aspect 3: The power supply circuit according to aspect 2, wherein the level shifter comprises a current sink, and is configured to discharge the capacitor via the current sink when the control input of the level shifter is activated by the logic element.

[0094] Aspect 4: The power supply circuit according to Aspect 2 or 3 further includes a reverse blocking transistor coupled between an input power node and a drain of the power transistor, wherein the logic element is configured to turn on the reverse blocking transistor during the bypass mode so that the input power node is effectively shorted to the switching node.

[0095] Aspect 5: A power supply circuit according to any one of the preceding aspects, wherein the gate driver comprises: a first n-type transistor, the first n-type transistor having a drain coupled to the output terminal of the gate driver and having a source coupled to the second power input terminal of the gate driver; a first p-type transistor, the first p-type transistor having a drain coupled to the output terminal of the gate driver and the drain of the first n-type transistor; and a second p-type transistor, the second p-type transistor having a source coupled to the source of the first p-type transistor and having a drain coupled to the first power input terminal of the gate driver.

[0096] Aspect 6: The power supply circuit of aspect 5, wherein the second p-type transistor is configured to be turned off when the capacitor is discharged and effectively place the output terminal of the gate driver in a high impedance state.

[0097] Aspect 7: The power supply circuit of aspect 5 or 6, wherein the gate driver further comprises a second n-type transistor having a drain coupled to the gate of the second p-type transistor, having a gate coupled to the power rail, and having a source coupled to the switch node.

[0098] Aspect 8: A power supply circuit according to any of the preceding aspects, wherein: the logic element includes a comparator having a first input terminal coupled to the first terminal of the capacitor and a second input terminal coupled to the second terminal of the capacitor; the logic element is configured to activate an output signal in response to the capacitor being discharged; and the logic element is configured to enable the pull-up circuit to output a voltage to turn on the power transistor based on the activated output signal.

[0099] Aspect 9: The power supply circuit according to aspect 8, wherein the comparator comprises a Schmitt trigger.

[0100] Aspect 10: The power supply circuit according to Aspect 9, wherein the comparator further comprises: a first transistor having a source coupled to the first terminal of the capacitor and a drain coupled to the gate of the first transistor; a first current sink coupled between the drain of the first transistor and a reference potential node for the power supply circuit; a second transistor having a source coupled to the second terminal of the capacitor, a gate coupled to the gate and the drain of the first transistor, and a drain coupled to the input of the Schmitt trigger; and a second current sink coupled between the drain of the second transistor and the reference potential node.

[0101] Aspect 11: The power supply circuit according to any one of the preceding aspects, wherein the pull-up circuit has a power input coupled to another power rail, the other power rail being configured to have a higher voltage than the voltage of the power rail.

[0102] Aspect 12: The power supply circuit according to Aspect 11, wherein the pull-up circuit comprises: a current mirror having a first branch and a second branch, the first branch and the second branch being coupled to the power supply input of the pull-up circuit; a first transistor having a source coupled to the second branch of the current mirror and a drain coupled to the output of the pull-up circuit; a second transistor having a drain coupled to the first branch of the current mirror and a gate coupled to the control input of the pull-up circuit; a first current sink coupled between the source of the second transistor and a reference potential node for the power supply circuit; a third transistor having a drain coupled to the gate of the first transistor and a gate coupled to the control input of the pull-up circuit; and a second current sink coupled between the source of the third transistor and the reference potential node for the power supply circuit.

[0103] Aspect 13: The power supply circuit according to Aspect 12, wherein the pull-up circuit further comprises a fourth transistor, the fourth transistor having a drain coupled to the power supply input terminal of the pull-up circuit, a source coupled to the first branch and the second branch of the current mirror, and a gate coupled to the gate of the first transistor and the drain of the third transistor.

[0104] Aspect 14: The power supply circuit according to any of the preceding aspects further includes a current sink selectively coupled to the first terminal of the capacitor, wherein during the bypass mode, the logic element is configured to effectively enable the current sink via the first output end of the logic element to discharge the capacitor, and enable the pull-up circuit to output a voltage to turn on the power transistor in response to the capacitor being discharged.

[0105] Aspect 15: A battery charging circuit, comprising the power supply circuit according to any of the preceding aspects, the battery charging circuit further comprising: an inductor having a first terminal coupled to the switching node; and a switch coupled between the second terminal of the inductor and a node for coupling to a battery.

[0106] Aspect 16: The battery charging circuit according to Aspect 15 further includes a level shifter, wherein the level shifter has a signal input terminal, a control input terminal, an output terminal coupled to the input terminal of the gate driver, a first power input terminal coupled to the power rail, and a second power input terminal coupled to the switching node, wherein the first output terminal of the logic element is coupled to the control input terminal of the level shifter, and wherein during the bypass mode, the logic element is configured to: control the switch to be disconnected; control the level shifter to discharge the capacitor; and enable the pull-up circuit to output a voltage to turn on the power transistor in response to the capacitor being discharged.

[0107] Aspect 17: A method of operating a power supply circuit, the method comprising: enabling a bypass mode for the power supply circuit; in response to the enabling, discharging a capacitor coupled across a power input terminal of a gate driver for driving a gate of a power transistor; determining that the capacitor has been discharged; and in response to the determination, pulling up the gate of the power transistor to turn on the power transistor and enter the bypass mode for the power supply circuit.

[0108] Aspect 18: The method of aspect 17, further comprising: activating a control signal to effectively enable a current sink such that the current sink begins discharging the capacitor.

[0109] Aspect 19: The method of aspect 17 or 18, further comprising: activating a control signal for a level shifter, the capacitor being coupled across a power supply input of the level shifter, such that the level shifter begins to discharge the capacitor.

[0110] Aspect 20: The method according to aspect 19, further comprising: deactivating an input signal for the level shifter in response to the enabling.

[0111] Aspect 21: The method according to any one of aspects 17 to 20, further comprising: turning on a reverse blocking transistor coupled between an input power node and a drain of the power transistor to enter the bypass mode for the power circuit.

[0112] Aspect 22: The method according to any one of Aspects 17 to 21, further comprising: causing an output terminal of the gate driver to enter a high impedance state based on the discharging and before pulling up the gate of the power transistor.

[0113] Aspect 23: The method according to any one of Aspects 17 to 22 further includes: activating an output signal in response to determining that the capacitor has been discharged, wherein pulling up the gate of the power transistor includes enabling a pull-up circuit to output a voltage to turn on the power transistor based on the activated output signal.

[0114] Aspect 24: A method according to any one of Aspects 17 to 23, wherein determining that the capacitor has been discharged includes: comparing a first voltage at a first terminal of the capacitor with a second voltage at a second terminal of the capacitor, the first terminal of the capacitor being coupled to a power rail and the second terminal of the capacitor being coupled to the source of the power transistor; and determining that the capacitor has been discharged when the difference between the first voltage and the second voltage is less than a threshold voltage.

[0115] Aspect 25: The method according to any one of aspects 17 to 24 further includes: in response to the enabling, opening a switch coupled between a first terminal of an inductor and a node for coupling to a battery, the second terminal of the inductor being coupled to the source of the power transistor.

[0116] Aspect 26: A method of operating a power supply circuit, the method comprising: enabling a bypass mode for the power supply circuit; in response to the enabling, determining that a capacitor coupled across a power input terminal of a gate driver for driving a gate of a power transistor is discharged; and in response to the determination, pulling up the gate of the power transistor to turn on the power transistor and enter the bypass mode for the power supply circuit.

[0117] Aspect 27: The method of aspect 26, further comprising: turning on a reverse blocking transistor coupled between an input power node and a drain of the power transistor to enter the bypass mode for the power circuit.

[0118] Aspect 28: The method according to aspect 26 or 27, further comprising: causing the output terminal of the gate driver to enter a high impedance state based on the capacitor being discharged and before the gate of the power transistor is pulled up.

[0119] Aspect 29: The method according to any one of Aspects 26 to 28, further comprising: activating an output signal in response to the determination, wherein pulling up the gate of the power transistor comprises enabling a pull-up circuit to output a voltage to turn on the power transistor based on the activated output signal.

[0120] Aspect 30: A method according to any one of Aspects 26 to 29, wherein determining that the capacitor is discharged includes: comparing a first voltage at a first terminal of the capacitor with a second voltage at a second terminal of the capacitor, the first terminal of the capacitor being coupled to a power rail and the second terminal of the capacitor being coupled to the source of the power transistor; and determining that a difference between the first voltage and the second voltage is less than a threshold voltage.

[0121] Additional Notes

[0122] The various operations of the above method can be performed by any suitable component that can perform the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally speaking, when there are operations illustrated in the accompanying drawings, those operations may have corresponding corresponding component-plus-function components with similar numbers.

[0123] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, and the like. Furthermore, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Furthermore, "determining" may include resolving, selecting, choosing, establishing, and the like.

[0124] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). By way of example, "at least one of a, b, or c" is intended to encompass: a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0125] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchangeable with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0126] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A power supply circuit, comprising: Power transistors; a switch node coupled to a source of the power transistor; Power rails; a capacitor having a first terminal coupled to the power rail and having a second terminal coupled to the switch node; a gate driver having an output coupled to a gate of the power transistor, having a first power input coupled to the power rail, and having a second power input coupled to the switch node; a logic element having a first input coupled to the first terminal of the capacitor, a second input coupled to the second terminal of the capacitor, and a first output; and A pull-up circuit has a control input coupled to the second output of the logic element and has an output coupled to the gate of the power transistor.

2. The power supply circuit of claim 1 , further comprising a level shifter having a signal input, having a control input, having an output coupled to an input of the gate driver, having a first power input coupled to the power rail, and having a second power input coupled to the switch node, wherein: The first output terminal of the logic element is coupled to the control input terminal of the level shifter; and During a bypass mode, the logic element is configured to control the level shifter to discharge the capacitor, and enable the pull-up circuit to output a voltage to turn on the power transistor in response to the capacitor being discharged. 3 . The power supply circuit of claim 2 , wherein the level shifter comprises a current sink, and is configured to discharge the capacitor via the current sink when the control input of the level shifter is activated by the logic element.

4. The power supply circuit of claim 2 , further comprising a reverse blocking transistor coupled between an input power node and a drain of the power transistor, wherein the logic element is configured to turn on the reverse blocking transistor during the bypass mode such that the input power node is effectively shorted to the switch node.

5. The power supply circuit according to claim 1 , wherein the gate driver comprises: a first n-type transistor having a drain coupled to the output of the gate driver and having a source coupled to the second power input of the gate driver; a first p-type transistor having a drain coupled to the output of the gate driver and the drain of the first n-type transistor; and a second p-type transistor having a source and a drain, the source of the second p-type transistor being coupled to the source of the first p-type transistor, the drain of the second p-type transistor being coupled to the first power input of the gate driver; 6 . The power supply circuit of claim 5 , wherein the second p-type transistor is configured to be turned off when the capacitor is discharged and effectively place the output of the gate driver in a high impedance state.

7. The power supply circuit of claim 5 , wherein the gate driver further comprises a second n-type transistor having a drain coupled to the gate of the second p-type transistor, having a gate coupled to the power rail, and having a source coupled to the switch node.

8. The power supply circuit according to claim 1, wherein: The logic element includes a comparator having a first input coupled to the first terminal of the capacitor and having a second input coupled to the second terminal of the capacitor; The logic element is configured to activate an output signal in response to the capacitor being discharged; and The logic element is configured to enable the pull-up circuit to output a voltage to turn on the power transistor based on the activated output signal.

9. The power supply circuit of claim 8, wherein the comparator comprises a Schmitt trigger.

10. The power supply circuit according to claim 9, wherein the comparator further comprises: a first transistor having a source coupled to the first terminal of the capacitor and having a drain coupled to the gate of the first transistor; a first current sink coupled between the drain of the first transistor and a reference potential node for the power supply circuit; a second transistor having a source coupled to the second terminal of the capacitor, a gate coupled to the gate and the drain of the first transistor, and a drain coupled to an input of the Schmitt trigger; and A second current sink is coupled between the drain of the second transistor and the reference potential node. 11 . The power supply circuit of claim 1 , wherein the pull-up circuit has a power supply input coupled to another power supply rail, the another power supply rail being configured to have a higher voltage than a voltage of the power supply rail.

12. The power supply circuit according to claim 11, wherein the pull-up circuit comprises: a current mirror having a first branch and a second branch, wherein the first branch and the second branch are coupled to the power input terminal of the pull-up circuit; a first transistor having a source coupled to the second branch of the current mirror and having a drain coupled to the output of the pull-up circuit; a second transistor having a drain coupled to the first branch of the current mirror and having a gate coupled to the control input of the pull-up circuit; a first current sink coupled between a source of the second transistor and a reference potential node for the power supply circuit; a third transistor having a drain coupled to the gate of the first transistor and having a gate coupled to the control input of the pull-up circuit; and A second current sink is coupled between a source of the third transistor and the reference potential node for the power supply circuit.

13. The power supply circuit according to claim 12 , wherein the pull-up circuit further comprises a fourth transistor having a drain coupled to the power input terminal of the pull-up circuit, a current mirror coupled to the first branch and the second branch, and a current mirror coupled to the first branch.

14. The power supply circuit of claim 1 , further comprising a current sink selectively coupled to the first terminal of the capacitor, wherein during a bypass mode, the logic element is configured to effectively enable the current sink via the first output terminal of the logic element to discharge the capacitor, and enable the pull-up circuit to output a voltage to turn on the power transistor in response to the capacitor being discharged.

15. A battery charging circuit, comprising the power supply circuit according to claim 1, further comprising: an inductor having a first terminal coupled to the switch node; and A switch is coupled between the second terminal of the inductor and a node for coupling to a battery.

16. The battery charging circuit of claim 15 , further comprising a level shifter having a signal input, a control input, an output coupled to an input of the gate driver, a first power input coupled to the power rail, and a second power input coupled to the switch node, wherein the first output of the logic element is coupled to the control input of the level shifter, and wherein during a bypass mode, the logic element is configured to: controlling the switch to open; controlling the level shifter to discharge the capacitor; as well as The pull-up circuit is enabled to output a voltage to turn on the power transistor in response to the capacitor being discharged.

17. A method of operating a power circuit, the method comprising: enabling a bypass mode for the power circuit; responsive to the enabling, discharging a capacitor coupled across a power supply input of a gate driver for driving a gate of a power transistor; determining that the capacitor has been discharged; as well as In response to the determination, the gate of the power transistor is pulled up to turn on the power transistor and enter the bypass mode for the power supply circuit.

18. The method according to claim 17, further comprising: A control signal is activated to effectively enable a current sink, causing the current sink to begin discharging the capacitor.

19. The method according to claim 17, further comprising: A control signal for a level shifter is activated, with the capacitor coupled across a power supply input of the level shifter, causing the level shifter to begin discharging the capacitor.

20. The method according to claim 19, further comprising: An input signal for the level shifter is deactivated in response to the enabling.

21. The method of claim 17, further comprising: A reverse blocking transistor coupled between an input power node and a drain of the power transistor is turned on to enter the bypass mode for the power supply circuit.

22. The method of claim 17, further comprising: Based on the discharge and before the gate of the power transistor is pulled up, the output terminal of the gate driver is caused to enter a high impedance state.

23. The method of claim 17, further comprising: An output signal is activated in response to the determining that the capacitor has been discharged, wherein pulling up the gate of the power transistor includes enabling a pull-up circuit to output a voltage to turn on the power transistor based on the activated output signal.

24. The method of claim 17, wherein determining that the capacitor has been discharged comprises: comparing a first voltage at a first terminal of the capacitor to a second voltage at a second terminal of the capacitor, the first terminal of the capacitor being coupled to a power rail and the second terminal of the capacitor being coupled to a source of the power transistor; as well as The capacitor is determined to be discharged when a difference between the first voltage and the second voltage is less than a threshold voltage.

25. The method of claim 17, further comprising: In response to the enabling, a switch coupled between a first terminal of an inductor and a node for coupling to a battery is opened, the second terminal of the inductor being coupled to the source of the power transistor.

26. A method of operating a power circuit, the method comprising: enabling a bypass mode for the power circuit; In response to the enabling, determining that a capacitor coupled across a power supply input of a gate driver for driving a gate of a power transistor is discharged; as well as In response to the determination, the gate of the power transistor is pulled up to turn on the power transistor and enter the bypass mode for the power supply circuit.

27. The method according to claim 26, further comprising: A reverse blocking transistor coupled between an input power node and a drain of the power transistor is turned on to enter the bypass mode for the power supply circuit.

28. The method of claim 26, further comprising: The output terminal of the gate driver is caused to enter a high impedance state based on the capacitor being discharged and before the gate of the power transistor is pulled up.

29. The method of claim 26, further comprising: An output signal is activated in response to the determination, wherein pulling up the gate of the power transistor includes enabling a pull-up circuit to output a voltage to turn on the power transistor based on the activated output signal.

30. The method of claim 26, wherein determining that the capacitor is discharged comprises: comparing a first voltage at a first terminal of the capacitor to a second voltage at a second terminal of the capacitor, the first terminal of the capacitor being coupled to a power rail and the second terminal of the capacitor being coupled to a source of the power transistor; as well as It is determined that a difference between the first voltage and the second voltage is less than a threshold voltage.

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