Semiconductor device and method of forming a polishing pad and chemical mechanical polishing apparatus

Abstract

A semiconductor device and a method of forming a polishing pad and a chemical mechanical polishing apparatus are provided according to some embodiments. The chemical mechanical polishing apparatus includes a polishing pad. The polishing pad includes a stack of a plurality of first pad portions and a stack of a plurality of second pad portions. The first pad portions and the second pad portions have different hardnesses. The stack of the first pad portions and the stack of the second pad portions are arranged in a pattern corresponding to predetermined features of a structure to be polished by the chemical mechanical polishing apparatus. The predetermined features can include a surface profile or a material of the structure to be polished.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor device, a method for forming a polishing pad, and a chemical mechanical polishing apparatus. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have led to the production of several generations of ICs, each featuring smaller and more complex circuits than the previous generation. In the evolution of ICs, while geometric dimensions (i.e., the smallest element (or outline) that a process can produce) have decreased, functional density (i.e., the number of interconnects per unit wafer area) has generally increased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] The pursuit of higher device density, higher performance, and lower cost has led to the development of three-dimensional designs, such as multi-gate field-effect transistors (FETs), including nanosheet FETs. One of the challenges arising from the increasing number of interconnect layers in a given IC involves chemical-mechanical polishing (CMP) processes, which are typically used to selectively remove high-elevation features by combining mechanical polishing with chemical reactions.

[0004] In 3nm or smaller processes, improving planarization efficiency (PE) and reducing CMP-induced defects play a crucial role in the manufacturing process within traditional CMP systems. Unfortunately, in traditional CMP systems, improving planarization efficiency often leads to more CMP-induced defects. Summary of the Invention

[0005] According to some embodiments of this disclosure, a chemical mechanical polishing (CMP) apparatus includes a polishing pad. The polishing pad comprises a stack of multiple first pad portions and a stack of multiple second pad portions. The first pad portions and the second pad portions have different hardnesses. The stacks of the first pad portions and the stacks of the second pad portions are arranged in a pattern corresponding to predetermined features of the structure to be polished by the CMP apparatus.

[0006] According to some embodiments of this disclosure, a method for forming a polishing pad includes the following steps: Depositing a first material, a second material, and a third material on a plane to form patterns of a plurality of first pad portions, a plurality of second pad portions, and a plurality of pore portions corresponding to predetermined features of a structure to be polished by a chemical mechanical polishing apparatus. Repeating the deposition step on different planes until a predetermined number of these patterns are formed and these patterns are stacked on top of each other. The hardness of the first material is different from the hardness of the second material, and the third material used to form these pore portions comprises a water-soluble material.

[0007] According to some embodiments of this disclosure, a method for forming a semiconductor device includes the following steps: forming a material layer on a substrate; polishing the material layer using a chemical mechanical polishing pad having multiple pad portions of different hardness, the pad portions having patterns corresponding to predetermined features of the material layer. Attached Figure Description

[0008] The nature of this disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0009] Figure 1 A side view of the CMP device is shown;

[0010] Figure 2 It shows, as Figure 1 The polishing mechanism of the CMP apparatus shown;

[0011] Figure 3 It is a cross-sectional view showing the surface of a semiconductor device planarized by CMP;

[0012] Figure 4 The material removal at various gradients is shown when using two polishing pads of different hardness in a CMP process;

[0013] Figure 5 It is a graph showing the polishing uniformity in each radial region of the wafer;

[0014] Figure 6 This is a side view of a polishing pad according to one embodiment;

[0015] Figure 7 The formation of a polishing pad according to an embodiment is shown;

[0016] Figure 8 Showing Figure 7 The dimensions of each section of the polishing pad;

[0017] Figure 9A top view shows a nanostructure polished using two different shaped polishing pads;

[0018] Figure 10 Various shapes of multiple pad portions of the polishing pad are shown;

[0019] Figure 11 An exemplary field design of a polishing pad according to one embodiment is shown;

[0020] Figure 12 The gradient of the oxide layer after the CMP process is shown;

[0021] Figure 13 The CMP removal rates of the oxide layer are shown using two different polishing pads;

[0022] Figure 14 It is a graph showing the CMP removal rate of oxides along the wafer radius;

[0023] Figure 15 The oxide removal rate is shown within the region along the wafer radius;

[0024] Figures 16 to 18 Various patterns of multiple pad portions of a polishing pad according to some embodiments are shown;

[0025] Figures 19 to 21 The process of using CMP (Chemical Mechanical Polishing) to planarize and form shallow trench isolation (STI) is shown.

[0026] [Symbol Explanation]

[0027] 10: CMP device

[0028] 12: Platform

[0029] 14: Polishing Pad

[0030] 16: Slurry supply device

[0031] 18: Slurry

[0032] 20: Wafer carrier

[0033] 21: Porosity

[0034] 22: Carrier membrane

[0035] 23: Wall Structure

[0036] 24: Wafer

[0037] 25: Uneven

[0038] 26: Regulator

[0039] 35: Oxide layer

[0040] 37: Silicon layer

[0041] 40: Curve

[0042] 42: Curve

[0043] 50H: Wafer area

[0044] 50L: Wafer area

[0045] 52: Polishing Pad

[0046] 52A: Pad portion

[0047] 52B: Pad portion

[0048] 60: 3D Printer

[0049] 62: Pad Material

[0050] 62A: Hard pad material

[0051] 62B: Padding material

[0052] 62C: Porous materials

[0053] 64: Pad portion

[0054] 64A: Hard pad portion

[0055] 64B: Padged portion

[0056] 64C: Porous portion

[0057] 70A: Pad portion

[0058] 70A': Pad portion

[0059] 70B: Pad portion

[0060] 70B': Pad portion

[0061] 72: Nanostructures

[0062] 90:3D polishing pad structure

[0063] 92: Pad portion

[0064] 94: Pad portion

[0065] 95: 3D Polishing Pad

[0066] 96: Groove

[0067] 100: Polishing pad structure

[0068] 102: Pad section

[0069] 104: Part

[0070] 110: Polishing pad structure

[0071] 112: Hard padding section

[0072] 114: Pad portion

[0073] 120: Polishing pad structure

[0074] 122: Hard padding section

[0075] 124: Pad portion

[0076] 126: Porous portion

[0077] 200:Substrate

[0078] 202: Semiconductor layer

[0079] 202a: First semiconductor layer

[0080] 202b: Second semiconductor layer

[0081] 204: Hard Mask

[0082] 206: Fin Structure

[0083] 208: Trap Section

[0084] 210: Lining layer

[0085] 212: Dielectric layer

[0086] l: length

[0087] h: height

[0088] w: width

[0089] W c angular velocity

[0090] W p angular velocity

[0091] X: axis

[0092] X-X': Direction

[0093] Y: axis

[0094] Z: Axis

[0095] Z-Z': Direction Detailed Implementation

[0096] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements, values, operations, materials, arrangements, or the like are described below to simplify this disclosure. These examples are, of course, illustrative only and are not intended to be limiting. Other elements, values, operations, materials, arrangements, and the like are considered. For example, the following description of forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0097] In addition, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” and similar terms may be used herein for descriptive purposes to describe the relationship of one part or feature to another part or feature(s), as shown in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The system may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0098] The fabrication of complex devices involves multiple semiconductor steps, such as lithography, etching, metal deposition, and CMP (Chemical Mechanical Polishing). CMP is a driver of the transition from planar to 3D device integration in logic and memory wafers, with each wafer having multiple CMP channels. The CMP process removes and planarizes excess material on the front surface of a wafer by applying downward forces to the back side of the wafer and pressing the front surface against a special material spin pad containing a mixture of chemicals and abrasives. CMP applications include shallow trench isolation (STI), inter-layer dielectric (ILD), tungsten interconnect, copper damascene, and other existing or emerging applications.

[0099] Figure 1 An exemplary CMP apparatus used in a planarization process is shown. The CMP apparatus 10 includes a platform 12 that can be driven at an angular velocity w. pRotation. Polishing pad 14 is disposed on the front surface of platform 12. Slurry supply device 16 is located above platform 12 to supply slurry 18 to polishing pad 14 disposed on the front surface of platform. For polishing the surface of wafer 24, CMP apparatus 10 includes wafer carrier 20 to hold wafer 24 on carrier film 22 within wafer carrier 20. Figure 1 As shown, wafer 24 can be driven by wafer carrier 20 at an angular velocity w c Rotation. During planarization, the wafer carrier 20 may use a vacuum to hold the wafer 24 in place and use a removal retaining ring or wafer guide to prevent movement. In some embodiments, the CMP apparatus 10 may include multiple wafer carriers 20 to planarize multiple wafers simultaneously.

[0100] In some embodiments, the polishing pad 14 is circular and the wafer 24 is placed face down and pressed against the polishing pad 14. The platform 12 rotates about its own axis and drives the wafer 24 by rotating the wafer carrier 20 about its axis. The force applied to the wafer 24 by the wafer carrier 20 can be adjusted within a predetermined range, for example, from 1 to 10 psi. The force applied to the wafer 24 by the wafer carrier 20 can be adjusted to suit the material being polished. For polishing oxide materials, the higher end of the range is applied, while metal polishing is performed using the lower end of the range. An important element of the CMP process is the uniform and well-controlled application of pressure on the wafer 24 and the well-controlled rotational speeds w of the wafer carrier 20 and the platform 12, respectively. c and w p The slurry 18 is dispensed from the tubular slurry supply device 16 in front of the wafer 24, such that the slurry 18 is pulled below the wafer 24 as the platform 12 rotates. In some embodiments, the bottom of the retaining ring of the wafer carrier 20 may be recessed from the bottom plane of the wafer 24.

[0101] The surface of polishing pad 14 provides two functions for material removal. The first function is to deliver slurry 18 to the material removal area and remove byproducts. The second function is to apply pressure to the various material regions of wafer 24. (e.g., ...) Figure 2 As shown, the polishing pad 14 may include apertures 21 to perform the first function. The wall structures 23 between the apertures 21 can perform the second function. Two-body abrasion at the contact area between the wafer 24 and the unevenness 25 formed on the wall structures 23 appears to be the primary material removal mechanism in the CMP process using the polishing slurry 18. Due to the irregular and non-uniform size and shape of the apertures 21 of the wall structures 23 of the polishing pad 14 and the rough cut surface, the contact area of ​​the two-body abrasion has an uneven shape and edges.

[0102] CMP apparatus 10 may also include a conditioner 26, which moves a hard abrasive surface, typically a matrix with embedded diamond dots, across the pad surface to roughen the polishing pad 14. The conditioner 26 can determine the inherent roughness of the polishing pad 14 in order to maintain surface stability by removing worn surface material and restoring the inherent structure. The conditioning process is crucial to the CMP process because insufficiently roughened pad 14 results in a very low polishing rate. It has been shown that the surface topologies of the polishing pad 14 play a key role in CMP, as they transmit normal forces and tangential motion to the hard nanoscale abrasive grains in the slurry 18.

[0103] Various types of polishing pads have been developed for dielectric CMP, polysilicon CMP, and metal CMP. Polishing pads can be made from the same materials, such as acrylic, polyurethane (PU), and polyimide. Harder pads, such as urethane-based pads, may be able to produce polished surfaces with a longer planarization range. In contrast, when using softer pads for CMP, the polishing pressure may deform the softer pads against the wafer surface, potentially causing pitting. For example, as... Figure 3 As shown, the softer pad deforms, with its center portion moving closer to the wafer placed below. This deformation causes the center portion of the oxide layer 35's surface to recess from the silicon layer 37 surrounding it. When using a softer pad during CMP, a recess effect can also occur in the metallic material.

[0104] Figure 4 This illustrates oxide loss at different step heights on a wafer during CMP processes using polishing pads of varying hardness. Curve 40 shows the oxide loss when using a polishing pad with a lower hardness, resulting in the oxide loss represented by curve 42. The arrows crossing curves 40 and 42 indicate that increasing the hardness of the polishing pad reduces oxide loss at lower step heights. For example, in... At the gradient, using a softer pad, the oxide loss may be approximately [missing value]. Using a harder pad, the oxide loss may be approximately [missing information]. The oxide loss at lower gradients indicates that the indentation effect is more pronounced when using a softer pad.

[0105] Ideally, Figure 3The removal rate of the oxide layer 35 within the trench shown is zero, while the removal rate (RR) of the active oxide layer, i.e., the oxides outside the trench, is 100%. The planarization efficiency (PE) used to form the STI can be expressed as:

[0106]

[0107] Due to the low planarization efficiency, a thicker deposition film is required, which leads to increased manufacturing costs and reduced yield (wafers per hour, WPH).

[0108] Planarization efficiency can be improved or resolved by using harder pads. However, harder pads inevitably introduce more CMP-induced defects. Increased defects can lead to significant within-zone (WiZ) inhomogeneities and reduced yield; thus, device degradation. In CMP operations, multiple polishing radial zones can be defined along the wafer radius. The downward force applied from one zone to another, the slurry material, and the rotational speed can be controlled. c and w p Other parameters are used to maintain the uniformity of polishing from area to area. However, the downward force applied to the same area, the material of the slurry, and the rotational speed w all affect the uniformity of the polishing. c and w p Because they are the same, it is impossible to improve intra-regional uniformity in the same way to maintain region-to-region polishing uniformity. For example... Figure 5 As shown, several regions (regions 1 to 7) have been defined based on their radial positions on the wafer. Figure 5 In this process, as the radial position moves further away from the central axis of the wafer, the inhomogeneity within the region (WiZ) becomes increasingly pronounced.

[0109] Pattern density is also an important factor that can affect the indentation effect. The removal rate of the oxide layer (or other material to be planarized) in regions with higher pattern density tends to be lower than that in regions with lower pattern density. In other words, the indentation effect is more pronounced in regions with lower pattern density than in regions with higher pattern density. Figure 6 A polished structure is shown that effectively prevents depressions in areas with low pattern density without introducing significant CMP defects. For example... Figure 6As shown, the polishing pad 52 is in the form of a stacked array of pad portions 52A and 52B. The pad portion 52A, aligned below the wafer region 50H with a higher pattern density, is made of a softer material compared to the material used to form the pad portion 52B aligned with the wafer region 50L with a lower pattern density. The softer pad portion 52A prevents the introduction of significant defects in the wafer region 50H with a higher pattern density during the CMP process, while the harder pad 52B minimizes the pitting effect at the wafer region 50L with a lower pattern density through the CMP process.

[0110] Instead of traditional processes, it forms block-shaped polishing pads made of the same material, such as... Figure 6 As shown, the polishing pad 52 (the polishing pad according to this disclosure) can be made to have different hardnesses in different areas. This allows the polishing pad to be soft overall and hard in specific areas. Different hardnesses can be achieved by using different materials or the same material with different properties. Figure 7 In the illustrated embodiment, the polishing pad is formed as a stack of segments or portions using 3D printing. The hardness of the polishing pad can be controlled at the pixel level by individually depositing each pad material 62 and then stacking each layer of the pad portion 64 onto each other. In one embodiment, three types of pad portions 64 can be formed within the polishing pad portion 64, including a hard pad portion 64A, a soft pad portion 64B, and a porous pad portion 64C. The hard pad portion 64A has greater hardness compared to the soft pad portion 64B. The porous pad portion 64C is made of a water-soluble material to become porous when water (liquid) is applied to the polishing pad 64.

[0111] like Figure 7 As shown, three types of filaments can be deposited from the 3D printer 60. The filaments, i.e., the pad material 62, can include a hard pad material 62A for forming the hard pad portion 64A, a soft pad material 62B for forming the soft pad portion 64B, and a porous material 62C for forming the pores 64C. The 3D printer 60 operates along the X and Y directions (…). Figure 7 The paper moves perpendicular to the X-X' and Z-Z' feed and output directions to form a pad layer on the XY surface along the Z-Z' direction to form an array of soft pad portions 64A, hard pad portions 64B, and porous portions 64C at the Z level. The same process is repeated at different Z levels to form multiple pad layers along the z-axis. The pad layers at different Z levels are stacked on top of each other to form a three-dimensional (3D) polishing pad 64.

[0112] In this embodiment, two rigid pad portions 64A, one soft pad portion 64B, and one porous portion 64C are sequentially and repeatedly formed along the X direction. The arrangement or order of the rigid pad portions 64A, soft pad portions 64B, and porous portions 64C along the Y direction can be the same as or different from the arrangement along the X direction. In the current embodiment, the same pattern of the rigid pad portions 64A, soft pad 64B, and porous portions 64C is arranged in each pad layer. That is, as shown... Figure 7 As shown, the polishing pad 64 includes an array of multiple stacked hard pad portions 64A, multiple stacked soft pad portions 64B, and multiple stacked porous pad portions 64C.

[0113] Figure 7 The polishing pad 64 is shown along the XZ plane. Figure 8 It shows, as Figure 7 The diagram shows a perspective view of any one of the pad portions 64A, 64B, and 64C. In one embodiment, each pad portion 64A, 64B, and 64C may be in the shape of a rectangular prism having a length l, a width w, and a height h, such as... Figure 8 As shown. The rigid pad portion 64A can have a length ranging from approximately 1 μm to 1000 μm. H and a width w ranging from approximately 1 μm to approximately 1000 μm H The height of the rigid pad portion 64A can range from about 1 μm to about 100 μm. The soft pad portion 64B can have a length ranging from about 1 μm to about 1000 μm. S Width w ranging from approximately 1 μm to approximately 1000 μm S and height h ranging from approximately 1 μm to approximately 100 μm S The perforated portion 64C can have a length ranging from about 1 μm to about 1000 μm. P Width w ranging from approximately 1 μm to approximately 1000 μm P and height h in the range of 1μm to approximately 100μm P According to some embodiments, the hardness of the rigid pad portion 64A can be in the range of about 40 Shore D to about 90 Shore D, and the hardness of the soft pad portion 64B can be in the range of about 30 Shore D to about 70 Shore D. The porous portion 64C can be a water-soluble hollow sphere.

[0114] As mentioned above, defect-free planarization without scratches or defects is crucial for achieving high yields and precise control of intra-zone (WiZ) uniformity during material removal. Manufacturing efficiency depends on two key factors. First, the material removal rate (MRR) must be maximized for a given cycle time. Second, the amount of CMP slurry, polishing pad, and conditioner must be minimized to improve cost efficiency. According to Preston's law, the material removal rate is proportional to the relative velocity v between the wafer to be planarized and the polishing pad, the polishing pressure p, and the Preston coefficient k:

[0115] MRR = k × p × v.

[0116] Preston's Law predicts that material removal rate increases with increasing relative velocity v, polishing load (pressure p), and Preston coefficient k. The Preston coefficient k is influenced by several process factors, including the physical contact between the abrasive and chemicals. As described earlier in this specification, material is removed through contact between nanoscale abrasives and chemically altered material surfaces. Therefore, the material removal mechanics of nanoscale abrasives directly affects material removal efficiency. Surface roughness of the polishing force applies polishing forces to the actively working abrasive. Therefore, the surface roughness of the pad is also important.

[0117] exist Figure 9 In designs (a) and (b), the two polishing pad structures consist of pad portions of different shapes on the XY plane. Each polishing pad includes two stacks of pad portions 70A and 70A' with a first hardness and a stack of pad portions 70B and 70B' with a second hardness. The stacks of pad portions 70B and 70B' are sandwiched between the stacks of pads 70A and 70A', respectively. In some embodiments, the first hardness is different from the second hardness. For example, the first hardness is less than the second hardness when pad portions 70B and 70B' are to be aligned to polish a wafer region with a lower pattern density and when pad portions 70A and 70B' are to be aligned with a wafer region with a higher pattern density during a CMP process. Figure 9 In the design shown in (a), the stack of each pad portion 70A and 70B has a rectangular front surface extending along the XY plane, while Figure 9 Each of the pad portions 70A' and 70B' in design (b) has a triangular front surface extending in the XY plane. As... Figure 9As shown, during the polishing of a wafer with a triangular nanostructure 72, the stacking of pad portions 70A and 70B with rectangular roughness of the polishing pad portion leads to uneven contact between the wafer and the polishing pad. Conversely, by configuring the pad roughness as a triangular profile, uniform contact between the wafer and the polishing pad can be obtained, as shown in Figure 9(b). Therefore, the shape of the front surface of each pad portion of the polishing pad can be configured with reference to the nanostructure 72 of the wafer to be planarized to reduce CMP-induced defects and improve polishing uniformity.

[0118] Depending on the nanostructure of the wafer to be polished, the polishing pad can be formed into cylinders, cubes, triangular prisms, pentagonal prisms, hexagonal prisms, polygonal prisms, or other regular or irregular shapes, such as... Figure 10 As shown. Different part shapes can allow for more localized and uniform contact pressure between the wafer and the polishing pad, such as... Figure 9 As shown.

[0119] Figure 11 An exemplary design of at least a portion of a polishing pad with pixel-level control is shown. Figure 11 As shown in the top view, the 3D polishing pad structure 90 has a stack of first pad portions 92 in the form of a field, within which an array of four stacked second pad portions 94 are arranged. The hardness of the first pad portions 92 is softer than that of the second pad portions 94. In some embodiments, the 3D polishing pad structure 90 may be repeatedly formed throughout the polishing pad. In some other embodiments, the 3D polishing pad structure 90 may extend locally within a portion of the polishing pad, while other polishing pad structures may be formed in other portions of the polishing pad. Figure 12 The use of a bulk polishing pad with the same hardness is shown, as well as... Figure 11 The surface profile of the wafer polished by the 3D polishing pad 90 is shown. Figure 12 The gradient process of the oxide layer on a CMP-processed wafer is shown. This was achieved using a conventional polishing pad and, for example... Figure 11 The planarization efficiency of the 3D polishing pad 90 shown can be obtained from Figure 12 The gradient shown is calculated. Empirical data shows that using a polishing pad of 90... There is a 58% improvement at the gradient.

[0120] Figure 13 The graph shows the functional relationship between CMP removal rate and radial position R, using both conventional polishing pads and pads with... Figure 11 The novel 3D polishing pad with field design is shown. When using a conventional polishing pad with uniform hardness, the removal rate RR (thickness removed per minute) at a radial position of R = 10 mm is [not specified]. ) can be in about to approximately Within a certain range. The removal rate ranges from approximately... As shown in the figure, the removal rate RR increases as the radial position R approaches the edge of the wafer. When approaching... At a radial position, the removal rate RR may range from approximately To date Therefore, when using traditional polishing pads in a CMP process, the uniformity of the removal rate decreases as R increases. Conversely, when 3D polishing pads with different hardnesses are arranged in different locations, the removal rate RR remains essentially constant, approximately [value missing]. Therefore, 3D polishing pads significantly improve the uniformity of removal rate (RR).

[0121] Figure 14 Showing the use of conventional polishing pads and 3D polishing pads 95 with a groove 96 design (see...) Figure 15 In the CMP process, a graph showing the range of in-area removal rate (WiZRR) as a function of radial position R. The groove design 92 may include segmented helical grooves to provide a smoother slurry distribution. As shown in the graph, conventional polishing pads result in an in-area removal rate ranging from... arrive Random fluctuations, with the highest range approaching In comparison, except arrive Outside the edges, the 3D polishing pad 100 with a spiral groove design 102 provides a substantially consistent surface finish. Small area. The 3D polishing pad 95 with segmented spiral grooves 96 exhibits a 64% improvement in uniformity.

[0122] Apart from Figure 11 In addition to the on-site design shown, the polishing pad can also be designed into various patterns according to the wafer morphology and other process requirements. Figure 16 Display and Figure 11 The polishing pad 90 shown is a top view of a polishing pad structure 100 with a similar structure. However, the polishing pad structure 100 has a region of pad portion 102 in which four hard portions 104 are arranged in a 2×2 matrix within the pad portion 102. Figure 17 The polishing pad structure 110, showing a hard pad portion 112 and a soft pad portion 114, is arranged in an alternating checkerboard pattern. Figure 18 In the polishing pad 120, not only are the hard pad portion 122 and the soft pad portion 124 included, but also the porous portion 126. For example... Figure 18 As shown, a mixture of two rows of porous portions 126, hard pad portions 122, and soft pad portions 124 is arranged between each pair of adjacent rows of soft pad portions 124. Each row of the mixture includes multiple pairs of adjacent hard pad portions 122 and soft pad portions 124 and porous portions 126 arranged alternately between adjacent pairs of hard pad portions 122.

[0123] As mentioned above, CMP processes with 3D polishing pads can be applied to the formation of various structures in semiconductor devices. Figures 19 to 21 The process for forming shallow trench isolation that can be used in FET, GAA devices, and other nanosheet devices is shown. Figures 19 to 21 Each of these provides perspective views and cross-sectional views. Figure 19 A substrate 200 is provided. According to one embodiment, the substrate 200 may be a semiconductor substrate. In some embodiments, the substrate 200 includes at least a single-crystal semiconductor layer on its surface. The substrate 200 may include single-crystal semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide antimony (GaAsSb), and indium phosphide (InP). In this embodiment, the substrate 200 is made of silicon. In some embodiments, the substrate 200 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxide.

[0124] One or more buffer layers (not shown) may be formed on the surface of substrate 200. The buffer layers may be used to gradually change the lattice constant from the substrate to the source / drain (S / D) region, thereby growing on substrate 100. The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, Germanium-tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaN, and InP. In one embodiment, substrate 200 includes a silicon-germanium buffer layer epitaxially grown on silicon substrate 200. The germanium concentration of the SiGe buffer layer may increase from 30 atomic percent germanium in the bottom buffer layer to 70 atomic percent germanium in the top buffer layer. Substrate 200 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type impurities). Dopants are, for example, boron for n-type field-effect transistors (NFETs) and phosphorus for p-type FETs (PFETs).

[0125] Stacked semiconductor layers 202 are formed on substrate 200, including alternately formed first semiconductor layers 202a and second semiconductor layers 202b. The first semiconductor layers 202a and 202b are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 202a may be made of Si, and the second semiconductor layer 202b may be made of SiGe. In some examples, the first semiconductor layer 202a may be made of SiGe, and the second semiconductor layer 202b may be made of Si. Alternatively, in some embodiments, either semiconductor layer 202a or 202b may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. Figure 19 In the illustrated embodiment, the first semiconductor layer 202a is made of Si, and the second semiconductor layer 202b is made of Si. 1-x Ge x It is made in a range of approximately 25% to approximately 50%.

[0126] The first semiconductor layer 202a, or a portion thereof, may form nanosheet channels of a semiconductor device structure in subsequent manufacturing stages. The term nanosheet is used herein to refer to any portion of material having a nanometer or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as beam or rod-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanosheet channels of the semiconductor device structure may be surrounded by gate electrodes. The semiconductor device structure may include nanosheet transistors. Nanosheet transistors may be referred to as nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes surrounding the channel. The first semiconductor layer 202a is used to define one or more channels of the semiconductor device structure.

[0127] The first and second semiconductor layers 202a and 202b can be formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the semiconductor layer stack 202 can be performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. Semiconductor layer 202a can define a channel for a FET, such as an n-type FET (NFET), or a channel for a second FET, such as a p-type FET (PFET). The thickness of the first semiconductor layer 202a is selected based on device performance considerations. In some embodiments, the second semiconductor layer 102b can be eventually removed and used to define space for the gate stack to be formed therein.

[0128] exist Figure 19 In the stack of semiconductor layers 202, there are three first semiconductor layers 202a and four second semiconductor layers 202b. It should be understood that the number of first semiconductor layers 202a and second semiconductor layers 202b in the stack of semiconductor layers 202 can vary depending on the desired number of nanosheet channels required for the semiconductor structure.

[0129] A hard mask 204 can be formed on the semiconductor stack 202. The hard mask 204 may include an oxygen-containing layer and a nitrogen-containing layer. The oxygen-containing layer may be a pad oxide layer, such as a SiO2 layer. The nitrogen-containing layer may be a pad nitride layer, such as Si3N4. The hard mask 204 can be formed by any suitable deposition process, such as chemical vapor deposition (CVD) or plasma-enhanced atomic layer deposition (PEALD). The semiconductor stack 202, a portion of the substrate 200, and the hard mask 204 are then patterned to form at least two fin structures 206. Each fin structure 206 includes a stack comprising a well portion 208 formed by one of the patterned portions of the substrate 200 and one of the stacks of the semiconductor layers 202. A liner layer 210, such as an oxide pad, may be conformally formed to cover the exposed surfaces of the fin structures 206.

[0130] exist Figure 20 In the middle, dielectric layer 212 is formed in such a way as Figure 19The semiconductor structure shown is superimposed on and fills the trenches between the fin structures 206. The dielectric layer 212 may comprise silicon oxide deposited by a process such as high-density plasma (HDP). High-density plasma allows oxide deposition to fill small trenches without leaving voids. Other processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or other similar processes may also be used to form the oxide layer. A CMP process is then performed to remove the silicon oxide layer 212, with a hard mask 204 acting as an etch stop layer because the removal rate of silicon nitride is approximately three times slower than that of silicon oxide. The CMP process is performed using a 3D polishing pad comprising a stacked array of hard pad portions, soft pad portions, and via portions. In some embodiments, each of the hard pad portions, soft pad portions, and via portions may have a length of approximately 40 μm, a width of approximately 40 μm, and a height of approximately 5 μm. The dimensions of each hard pad portion, soft pad portion, and via portion can be adjusted according to the topology and other process parameters of the wafer to be polished.

[0131] The polishing pad has a polishing surface including hard pad portions arranged in multiple locations to polish portions of the oxide layer 212 that are easily recessed by the CMP process. For example, the hard pad portions are arranged to polish groove oxides, i.e., the oxide layer 212 fills and lies above the grooves between the fin structures 206. The polishing surface also includes soft pad portions arranged to polish active oxides 212, such as the oxide layer 212 on the fin structures 206, which are generally more resistant to the dishing effect. As a result, CMP-induced defects can be minimized. Porous portions are also arranged between the soft and hard pad portions to allow for a smoother and more efficient introduction of slurry to further improve polishing uniformity. Figure 21 As shown, a basically flat shallow trench isolation surface without obvious indentation effect can be obtained.

[0132] Besides the formation of dielectric structures such as STI discussed above, CMP is also widely used to form conductive structures, such as planarizing metal surfaces and defining copper (Cu) back-end-of-line (BEOL) technology. Similar to oxides, CMP introduces undesirable side effects, including pitting and scratch defects. The pitting effect may be due to the difference in material properties between the dielectric and the metal during the CMP process. The dishing effect may also be caused by the hardness of the polishing pad used in the CMP process. Because Cu is softer than oxides, it is more sensitive to chemical slurries; therefore, Cu polishes at a faster rate compared to the surrounding material (e.g., silicon oxide). Furthermore, when using softer polishing pads, the force applied from the center of the pad results in greater pressure on the wafer in direct contact with the pad than at the edges. The pitting effect is more pronounced with wider metal lines compared to narrower metal lines. Choosing a softer polishing pad can further improve the pitting effect of CMP on Cu. However, when a harder polishing pad is chosen, polishing defects increase significantly, severely degrading device performance.

[0133] In one embodiment, a 3D polishing pad made of a stacked array of hard pad portions, soft pad portions, and porous portions is used to perform CMP processes on conductive structures such as metal wires in a BEOL. The arrangement of the individual stacks of the hard pad portions, soft pad portions, and porous portions can be designed according to the specific layout of the BOEL structure. For example, stacks of hard pad portions can be arranged to polish metal wires, while stacks of soft pad portions can be arranged to polish the dielectric layer surrounding the metal wires. Stacks of porous portions can be arranged between the hard pad portions and the soft pad portions to result in a smoother and more efficient slurry supply. Examples of stacked arrangements of hard pad portions, soft pad portions, and porous portions can be found in [reference needed]. Figure 7 , Figure 10 , Figures 15 to 17 Those shown, as well as other patterns not shown in the figure.

[0134] According to some embodiments, a chemical mechanical polishing (CMP) apparatus is provided. The CMP apparatus includes a polishing pad. The polishing pad includes a plurality of first pad portions stacked together and a plurality of second pad portions stacked together. The first pad portions and the second pad portions have different hardnesses. The stacks of the first pad portions and the stacks of the second pad portions are arranged in a pattern corresponding to predetermined features of the structure to be polished by the CMP apparatus. The predetermined features may include the surface profile or material of the structure to be polished.

[0135] The polishing pad may also comprise multiple porous portions. The length of each porous portion can range from about 1 μm to about 1000 μm. The porous portions may include water-soluble hollow spheres. The polishing pad may also comprise multiple polishing layers stacked on top of each other. The porous portions may be arranged between a first pad portion and a second pad portion. Each of the first pad portion and the second pad portion may have a length ranging from about 1 μm to about 1000 μm. Each of the first pad portion and the second pad portion may have a width ranging from about 1 μm to about 1000 μm. Each of the first pad portion and the second pad portion may have a height ranging from about 1 μm to about 100 μm. Each of the first pad portion and the second pad portion may have a cylindrical, square prism, triangular prism, cubic, pentagonal prism, hexagonal prism, or polygonal prism shape.

[0136] In one embodiment, the pattern comprises a 2×2 matrix of first pad portions arranged within a second pad portion. In another embodiment, the first and second pad portions are arranged in a grid pattern. The pattern may also comprise a first mixture of two columns of first pad portions, one column of first pad portions, second pad portions, and pore portions, and a second mixture of one column of first pad portions, second pad portions, and pore portions. Columns of the first mixture and columns of the second mixture are arranged between the two columns of the first pad portions.

[0137] In some embodiments, each first pad portion may have a hardness in the range of about 40 Shore D to about 90 Shore D, and each second pad portion may have a hardness in the range of about 30 Shore D to about 90 Shore D. The polishing pad may include a matrix of about 1×1 to 100×100 first pad portions and a matrix of 1×1 to 100×100 second pad portions.

[0138] According to one embodiment, a method for forming a polishing pad for a chemical mechanical polishing (CMP) apparatus is provided. This method includes depositing a first material, a second material, and a third material on a plane to form patterns of a plurality of first pad portions, a plurality of second pad portions, and a plurality of pore portions corresponding to predetermined features of a structure to be polished by the CMP apparatus. The deposition steps are repeated on different planes until a predetermined number of patterns are formed and these patterns are stacked on top of each other. The hardness of the first material is different from the hardness of the second material, and the third material used to form the pore portions comprises a water-soluble material.

[0139] This method may also include forming a first pad portion, a second pad portion, and a porous portion having the shape of a cylinder, a square prism, a triangular prism, a cube, a pentagonal prism, or a hexagonal prism. In some embodiments, the 3D printing process may be used to deposit a first material, a second material, and a third material.

[0140] A method for forming a semiconductor device is provided according to some embodiments. This method includes the steps of forming a material layer on a substrate and polishing the material layer using a polishing pad employing a chemical mechanical process. The polishing pad has multiple pad portions of different hardnesses, these pad portions having patterns corresponding to predetermined features of the material layer. The method may further include planarizing the material layer on a first region having a first pattern density using pad portions having a first hardness, and planarizing the material layer on a second region having a second pattern density using pad portions having a second hardness. The first pattern density is higher than the second pattern density, and the first hardness is lower than the second hardness.

[0141] The foregoing outlines several features of the embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A chemical mechanical polishing apparatus, characterized in that, Include: A polishing pad, comprising: Stacking of multiple first pad portions; and A stack of multiple second pad portions, wherein The plurality of first pad portions and the plurality of second pad portions have different hardness, and The stack of the plurality of first pad portions and the stack of the plurality of second pad portions are arranged in a pattern corresponding to a predetermined feature of a structure to be polished by a chemical mechanical polishing apparatus, wherein the pattern includes: The plurality of first pad portions in the two columns; A first mixture of the plurality of first pad portions, the plurality of second pad portions, and the plurality of pore portions in a row; and A second mixture of the plurality of first pad portions, the plurality of second pad portions, and the plurality of pore portions in a column, wherein the column of the first mixture and the column of the second mixture are arranged between two columns of the plurality of first pad portions.

2. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, The polishing pad also contains a stack of multiple porous sections.

3. The chemical mechanical polishing apparatus as described in claim 2, characterized in that, The length of each of these pore portions ranges from 1µm to 1000µm.

4. The chemical mechanical polishing apparatus as described in claim 2, characterized in that, The plurality of porous portions comprise a plurality of water-soluble hollow spheres.

5. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, The predetermined feature includes a surface profile of the structure to be polished.

6. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, The predetermined feature includes a material of the structure to be polished.

7. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, Each of the first pad portion and each of the second pad portions has a length range from 1µm to 1000µm.

8. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, Each of the first pad portion and each of the second pad portions has a width range from 1µm to 1000µm.

9. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, Each of the first pad portion and each of the second pad portions has a height range from 1µm to 100µm.

10. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, Each of the first pad portions and each of the second pad portions has a front surface that has a shape of a cylinder, a square prism, a triangular prism, a cube, a pentagonal prism, a hexagonal prism, or a polygonal prism.

11. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, Each of the first pad portions has a length of 40µm, a width of 40µm, and a height of 5µm.

12. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, The plurality of first pad portions and the plurality of second pad portions are arranged in a grid pattern.

13. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, Each of the second pad portions has a length of 40µm, a width of 40µm, and a height of 5µm.

14. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, in: Each of the first pad portions has a hardness ranging from 40 Shore D to 90 Shore D; and Each of the second pad portions has a hardness ranging from 30 Shore D to 90 Shore D.

15. The chemical mechanical polishing apparatus as described in claim 1, characterized in that, The polishing pad includes: A matrix of 1×1 to 100×100 of the plurality of first pad portions; and A matrix of 1×1 to 100×100 of the plurality of second pad portions.

16. A method for forming a polishing pad, characterized in that, Include: A first material, a second material, and a third material are deposited on a plane to form a pattern of a plurality of first pad portions, a plurality of second pad portions, and a plurality of pore portions corresponding to a predetermined feature of a structure to be polished by a chemical mechanical polishing apparatus, wherein the pattern includes: The plurality of first pad portions in the two columns; A first mixture of the plurality of first pad portions, the plurality of second pad portions, and the plurality of pore portions in a row; and A second mixture of the plurality of first pad portions, the plurality of second pad portions, and the plurality of pore portions in a column, wherein the column of the first mixture and the column of the second mixture are arranged between two columns of the plurality of first pad portions; as well as The deposition process is repeated on multiple different planes until a predetermined number of the patterns are formed and the predetermined number of patterns are stacked on top of each other, wherein The hardness of the first material is different from the hardness of the second material, and The third material used to form the plurality of porous portions comprises a water-soluble material.

17. The method for forming a polishing pad as described in claim 16, characterized in that, It also includes the plurality of first pad portions, the plurality of second pad portions, and the plurality of pore portions forming a shape having a cylinder, a square prism, a triangular prism, a cube, a pentagonal prism, a hexagonal prism, or a polygonal prism.

18. The method for forming a polishing pad as described in claim 16, characterized in that, It also includes using a 3D printing process to deposit the first material, the second material, and the third material.

19. A method for forming a semiconductor device, characterized in that, Include: A material layer is formed on a substrate; and The material layer is polished using a polishing pad with multiple pad portions of different hardness via a chemical mechanical process. Each pad portion has a pattern corresponding to a predetermined feature of the material layer, wherein the pattern includes: Multiple first pad portions in two columns; A first mixture of the plurality of first pad portions, the plurality of second pad portions, and the plurality of pore portions in a column; and A second mixture of the plurality of first pad portions, the plurality of second pad portions, and the plurality of pore portions in a column, wherein the column of the first mixture and the column of the second mixture are arranged between two columns of the plurality of first pad portions.

20. The method for forming a semiconductor device as claimed in claim 19, characterized in that, Also includes: The material layer on a first region having a first pattern density is planarized using the plurality of pad portions having a first hardness; The material layer on a second region having a second pattern density is planarized using the plurality of pad portions having a second hardness, wherein The density of the first pattern is higher than that of the second pattern, and The first hardness is less than the second hardness.

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