Electronic package and method of making the same

Abstract

This invention proposes an electronic package and its manufacturing method. The electronic package includes providing a circuit structure having a circuit layer; forming an insulating layer on the circuit structure, wherein the insulating layer has a plurality of first through holes; forming a plurality of conductive pillars in the plurality of first through holes, and disposing an electronic component on the insulating layer; forming an encapsulation layer on the insulating layer such that the encapsulation layer covers the electronic component and the plurality of conductive pillars, wherein the encapsulation layer has a plurality of second through holes exposing the plurality of conductive pillars; and filling the plurality of second through holes with a plurality of conductive material.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging process, and more particularly to an electronic package that can reduce overall thickness and its manufacturing method. Background Technology

[0002] Figure 1 This is a cross-sectional view of an existing electronic package 1. Figure 1 As shown, the electronic package 1 includes a circuit structure 11, an insulating layer 12, an electronic component 13, multiple conductive pillars 14, an encapsulation layer 15, conductive traces 16, and an electronic device 17. The insulating layer 12 is disposed on the circuit structure 11. The electronic component 13 is disposed on the insulating layer 12. The encapsulation layer 15 is formed on the insulating layer 12 and covers the electronic component 13. Multiple conductive pillars 14 are embedded in the insulating layer 12 and the encapsulation layer 15, with their tops flush with the encapsulation layer 15. Conductive traces 16 are disposed on the encapsulation layer 15 and electrically connected to the conductive pillars 14. The electronic device 17 is disposed on the conductive traces 16 via multiple conductive bumps 18.

[0003] However, in the existing electronic package 1, the gap G between the electronic device 17 and the package layer 15 cannot be reduced due to the presence of multiple conductive bumps 18 and conductive traces 16, making it difficult for the overall thickness of the electronic package 1 to meet the requirements for thinning.

[0004] Therefore, overcoming the various problems of the existing technologies has become an urgent issue to be addressed. Summary of the Invention

[0005] The purpose of this invention is to provide an electronic package and its manufacturing method to solve at least one of the above-mentioned problems.

[0006] In view of the various deficiencies of the prior art, the present invention provides an electronic package comprising: a circuit structure having a circuit layer; an insulating layer disposed on the circuit structure and having a plurality of first through holes exposing the circuit layer; an electronic component disposed on the insulating layer and electrically connected to the circuit structure; a plurality of conductive pillars formed in the plurality of first through holes and partially protruding from the insulating layer; an encapsulation layer formed on the insulating layer and covering the electronic component and the plurality of conductive pillars, and having a plurality of second through holes exposing the plurality of conductive pillars; and a plurality of conductive materials filling the plurality of second through holes and partially protruding from the encapsulation layer.

[0007] The present invention also provides a method for manufacturing an electronic package, comprising: providing a circuit structure having a circuit layer; forming an insulating layer on the circuit structure, wherein the insulating layer has a plurality of first through holes exposing the circuit layer; forming a plurality of conductive pillars in the plurality of first through holes, and disposing an electronic component on the insulating layer such that the plurality of conductive pillars partially protrude from the insulating layer, and electrically connecting the electronic component to the circuit structure; forming an encapsulation layer on the insulating layer such that the encapsulation layer covers the electronic component and the plurality of conductive pillars, wherein the encapsulation layer has a plurality of second through holes exposing the plurality of conductive pillars; and filling a plurality of conductive materials in the plurality of second through holes, such that the plurality of conductive materials partially protrude from the encapsulation layer.

[0008] In the aforementioned electronic package and its manufacturing method, each of the plurality of conductive pillars has a first pillar and a second pillar connected together. The first pillar is formed in the first through hole, and the second pillar is embedded in the package layer and protrudes from the insulating layer.

[0009] In the aforementioned electronic package and manufacturing method, the height of the second pillar protruding from the insulating layer is equal to or less than the height of the electronic component disposed on the insulating layer.

[0010] In the aforementioned electronic package and its manufacturing method, the size of the second column is larger than the size of the second perforation.

[0011] In the aforementioned electronic package and its manufacturing method, the depth of the second perforation is less than the thickness of the package layer.

[0012] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, by forming a second through hole with exposed conductive pillars in the packaging layer and filling the second through hole with conductive material, the gap between the electronic device and the packaging layer of the packaging structure can be reduced, which is beneficial to reducing the overall thickness of the electronic package. Attached Figure Description

[0013] Figure 1 This is a cross-sectional schematic diagram of an existing electronic package.

[0014] Figures 2A to 2G This is a cross-sectional schematic diagram of a first embodiment of the manufacturing method of the electronic package of the present invention.

[0015] Figures 3A to 3G This is a cross-sectional schematic diagram of a second embodiment of the manufacturing method of the electronic package of the present invention.

[0016] The attached figures are labeled as follows:

[0017] 1, 2 Electronic packages

[0018] Line structures 11 and 21

[0019] 12, 22 Insulation layer

[0020] 13, 23 Electronic components

[0021] 14, 24 conductive pillars

[0022] 15, 25 encapsulation layers

[0023] 16 Conductive traces

[0024] 17.2b Electronic Devices

[0025] 18, 230 conductive bumps

[0026] 2a Packaging Structure

[0027] 211 Dielectric Layer

[0028] 212 Line Layer

[0029] 221 First perforation

[0030] 241 First Column

[0031] 242 Second Column

[0032] 251 Second perforation

[0033] 26 Conductive materials

[0034] 28 Metal Layers

[0035] 29. Barrier layer

[0036] 291 Through Hole

[0037] D Depth

[0038] D1, D2 dimensions

[0039] G and G1 gaps

[0040] H1, H2 height

[0041] Thickness T Detailed Implementation

[0042] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0043] It should be understood that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the invention, should still fall within the scope of the disclosed technical content. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0044] Figures 2A to 2G This is a cross-sectional schematic diagram of a first embodiment of the manufacturing method of the electronic package of the present invention.

[0045] like Figure 2A As shown, a circuit structure 21 is provided, comprising a plurality of dielectric layers 211 and a plurality of circuit layers 212 bonded to the plurality of dielectric layers 211. The outermost dielectric layer 211 serves as a solder resist layer, and the outermost circuit layer 212 is exposed outside the solder resist layer to serve as an electrical contact pad. Furthermore, relative to the outermost circuit layer 212, the innermost circuit layer 212 (i.e., Figure 2A The circuit structure 21 is embedded in the dielectric layer 211 on its bottom side and is flush with the surface of the dielectric layer 211 on the bottom side of the circuit structure 21. Therefore, the circuit structure 21 provided by the present invention can be an embedded circuit substrate.

[0046] Next, an insulating layer 22 having a plurality of first through holes 221 is provided on the outermost dielectric layer 211, and a barrier layer 29 having a plurality of through holes 291 is provided on the insulating layer 22.

[0047] In this embodiment, the circuit structure 21 can be a coreless substrate structure, the circuit layer 212 adopts the redistribution layer (RDL) specification, and the dielectric layer 211 is an ABF (Ajinomoto build-up film) dielectric material with a coefficient of thermal expansion (CTE) of 13 to 17 ppm / ℃.

[0048] Furthermore, the insulating layer 22 can be made of a photo-imageable dielectric (PID), specifically photosensitive polyimide (PSPI) with a CTE of 30 to 35 ppm / ℃. Therefore, multiple first vias 221 can be formed using an exposure and development method, with the first vias 221 exposing portions of the circuit layer 212.

[0049] In addition, the barrier layer 29 is made of dry film or other photoresist and is formed on the insulating layer 22 by spin coating or lamination. Multiple vias 291 are formed by exposure and development. The multiple vias 291 correspond to multiple first through holes 221 in the connected portion, and the width of the vias 291 is greater than the width of the first through holes 221.

[0050] like Figure 2B As shown, a metal material (such as copper) is formed in the through hole 291 and the first through hole 221 by electroplating or sputtering to serve as a conductive pillar 24. Then, the barrier layer 29 is removed to expose the portion of the first through hole 221.

[0051] In this embodiment, the conductive post 24 has a first post 241 and a second post 242 connected together. The first post 241 is formed in the first through hole 221 and is electrically connected to the outermost circuit layer 212. The second post 242 is formed on the first post 241 and the insulating layer 22 and protrudes from the top surface of the insulating layer 22.

[0052] like Figure 2C As shown, at least one electronic component 23 is disposed on the insulating layer 22 and electrically connected to the circuit layer 212 via conductive bumps 230 in a plurality of first through holes 221 disposed in the exposed portion of the circuit layer 212, such that the height H2 of the second pillar 242 protruding from the insulating layer 22 is less than the height H1 of the electronic component 23 disposed on the insulating layer 22.

[0053] In this embodiment, the electronic component 23 is an active component, a passive component, or a combination of both. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, or an inductor. The conductive bump 230 is, for example, solder material (solder paste or solder balls).

[0054] like Figure 2DAs shown, an encapsulation layer 25 is formed on the insulating layer 22 to cover the electronic component 23, a plurality of second pillars 242, and conductive bumps 230. The thickness T of the encapsulation layer 25 is greater than the height H2 of the second pillars 242 protruding from the insulating layer 22, and greater than the height H1 of the electronic component 23 disposed on the insulating layer 22. The encapsulation layer 25 is an insulating material, such as polyimide (PI), dry film, epoxy resin encapsulant, or other molding compound, and can be formed on the insulating layer 22 by lamination or molding.

[0055] like Figure 2E As shown, a portion of the material of the encapsulation layer 25 is removed by laser to form a plurality of second perforations 251 exposing the top surface of a plurality of second pillars 242. The thickness T of the encapsulation layer 25 is greater than the depth D of the second perforations 251, and the size D2 of the second perforations 251 is smaller than the size D1 of the second pillars 242, so that only the second pillars 242 are partially exposed, for example, only the upper surface of the second pillars 242 is partially exposed.

[0056] like Figure 2F As shown, a metal layer 28 is formed on the bottom surface, side surface, and part of the encapsulation layer 25 in the second through-hole 251 by chemical plating. The metal layer 28 may be made of, for example, copper, and is electrically connected to the second pillar 242. Next, a conductive material 26 is filled into the metal layer 28 in the second through-hole 251, and the conductive material 26 protrudes from the top surface of the encapsulation layer 25, thereby obtaining an encapsulation structure 2a. It should be understood that the metal layer 28 may not be formed, and the conductive material 26 may be filled directly into the second through-hole 251.

[0057] In this embodiment, the conductive material 26 may be, for example, solder paste.

[0058] like Figure 2G As shown, a heating operation, such as a reflow process, can be performed to reflow multiple conductive materials 26, allowing an electronic device 2b to be attached to the package structure 2a via the multiple conductive materials 26, thereby obtaining the electronic package 2 of the present invention. A gap G1 exists between the electronic device 2b and the package layer 25 of the package structure 2a. In one embodiment, the electronic device 2b is a ball grid array (BGA) semiconductor package or a wire bond (WB) semiconductor package, but is not limited thereto.

[0059] In summary, in the electronic package 2 of the present invention, by forming a second through hole 251 with exposed conductive pillar 24 in the package layer 25, filling the second through hole 251 with conductive material 26, and connecting the package structure 2a to the electronic device 2b by reflowing the conductive material 26, the gap G1 between the electronic device 2b and the package layer 25 of the package structure 2a can be reduced (that is, smaller than the gap G between the electronic device 17 and the package layer 15 in the prior art), which is beneficial to reducing the overall thickness of the electronic package 2.

[0060] Furthermore, the insulating layer 22 forms the first through-hole 221 by exposure and development, thus it is not limited by the aspect ratio of laser drilling, which is beneficial for the fabrication of the conductive post 24. The conductive post 24 can be exposed without grinding the encapsulation layer 25, and the conductive post 24 interconnected with the conductive material 26 can provide a larger surface area, which is beneficial for the adhesion between the conductive material 26 and the conductive post 24, and can avoid reliability problems caused by cracks.

[0061] Furthermore, the dielectric layer 211 is composed of ABF, and the CTE of the insulating layer 22 is greater than that of the dielectric layer 211 (that is, the CTE gradually increases from bottom to top). This helps to reduce warpage and avoid risks such as solder ball peeling, cracking or displacement after packaging during the reflow process.

[0062] Figures 3A to 3G This is a cross-sectional schematic diagram of a second embodiment of the manufacturing method of the electronic package of the present invention. The second embodiment differs from the first embodiment only in some manufacturing methods. The differences are described below, and the same technical content will not be repeated here.

[0063] like Figure 3A As shown, a circuit structure 21 is provided, comprising multiple dielectric layers 211 and multiple circuit layers 212 bonded to the dielectric layers 211. The outermost dielectric layer 211 serves as a solder resist layer, and the outermost circuit layers 212 are exposed outside the solder resist layer to serve as electrical contact pads. Next, an insulating layer 22 having multiple first through-holes 221 is provided on the outermost dielectric layer 211, and a barrier layer 29 having multiple through-holes 291 is provided on the insulating layer 22. In this embodiment, the thickness of the barrier layer 29 is greater than the thickness of the barrier layer 29 in the first embodiment.

[0064] like Figure 3B As shown, a metal material (such as copper) is formed in the through hole 291 and the first through hole 221 by electroplating or sputtering to serve as a conductive pillar 24, and the barrier layer 29 is removed to expose the first through hole 221.

[0065] In this embodiment, the conductive post 24 has a first post 241 and a second post 242 connected together. The first post 241 is formed in the first through hole 221 and is electrically connected to the outermost circuit layer 212. The second post 242 is formed on the first post 241 and the insulating layer 22 and protrudes from the top surface of the insulating layer 22.

[0066] like Figure 3C As shown, at least one electronic component 23 is disposed on the insulating layer 22 and electrically connected to the circuit layer 212 via a plurality of conductive bumps 230 disposed in the first through hole 221, such that the height H2 of the second pillar 242 protruding from the insulating layer 22 is equal to the height H1 of the electronic component 23 disposed on the insulating layer 22.

[0067] like Figure 3D As shown, an encapsulation layer 25 is formed on the insulating layer 22 to cover the electronic component 23 and a plurality of second pillars 242. The thickness T of the encapsulation layer 25 is greater than the height H2 of the second pillars 242 protruding from the insulating layer 22 and greater than the height H1 of the electronic component 23 disposed on the insulating layer 22.

[0068] like Figure 3E As shown, a portion of the material of the encapsulation layer 25 is removed by laser to form a plurality of second perforations 251 exposing the top surface of a plurality of second pillars 242. The thickness T of the encapsulation layer 25 is greater than the depth D of the second perforations 251, and the size D2 of the second perforations 251 is smaller than the size D1 of the second pillars 242, so that only the second pillars 242 are partially exposed, for example, the upper surface of the second pillars 242 is partially exposed.

[0069] like Figure 3F As shown, a conductive material 26 is filled into the second through-hole 251, and the conductive material 26 protrudes partially from the top surface of the encapsulation layer 25, thereby obtaining an encapsulation structure 2a. In this embodiment, the conductive material 26 may be, for example, solder paste.

[0070] like Figure 3G As shown, a heating operation, such as a reflow process, can be performed to reflow multiple conductive materials 26, allowing an electronic device 2b to be attached to the packaging structure 2a via the multiple conductive materials 26, thereby obtaining the electronic package 2 of the present invention. A gap G1 exists between the electronic device 2b and the packaging layer 25 of the packaging structure 2a, and this gap G1 is smaller than the gap G between the electronic device 17 and the packaging layer 15 in the prior art, which is beneficial for reducing the overall thickness of the electronic package 2.

[0071] The present invention provides an electronic package 2, comprising a circuit structure 21, an insulating layer 22, at least one electronic component 23, a plurality of conductive pillars 24, an encapsulation layer 25, a plurality of conductive materials 26, and an electronic device 2b.

[0072] The circuit structure 21 includes multiple dielectric layers 211 and multiple circuit layers 212 bonded to the multiple dielectric layers 211. The outermost dielectric layer 211 can serve as a solder resist layer, and the outermost circuit layer 212 is exposed to the solder resist layer to serve as an electrical contact pad.

[0073] The insulating layer 22 is disposed on the outermost dielectric layer 211 and has a plurality of first through holes 221 that expose the outermost circuit layer 212.

[0074] At least one electronic component 23 is disposed on the insulating layer 22 and is electrically connected to the circuit layer 212 via a plurality of conductive bumps 230 disposed in the first through hole 221.

[0075] Multiple conductive pillars 24 are formed in multiple first through-holes 221 and partially protrude from the insulating layer 22. In this embodiment, the conductive pillars 24 have connected first pillars 241 and second pillars 242. The first pillar 241 is formed in the first through-hole 221 and is electrically connected to the outermost circuit layer 212. The second pillar 242 is formed on the first pillar 241 and the insulating layer 22 and protrudes from the top surface of the insulating layer 22.

[0076] In one embodiment, the height H2 of the second pillar 242 protruding from the insulating layer 22 is less than the height H1 of the electronic component 23 disposed on the insulating layer 22. In another embodiment, the height H2 of the second pillar 242 protruding from the insulating layer 22 is equal to the height H1 of the electronic component 23 disposed on the insulating layer 22.

[0077] The encapsulation layer 25 is formed on the insulating layer 22 and covers the electronic component 23 and a plurality of conductive pillars 24. It has a plurality of second through holes 251 that expose the conductive pillars 24. The thickness T of the encapsulation layer 25 is greater than the height H2 of the second pillars 242 protruding from the insulating layer 22, greater than the height H1 of the electronic component 23 disposed on the insulating layer 22, and greater than the depth D of the second through holes 251. The size D2 of the second through holes 251 is smaller than the size D1 of the second pillars 242 and can only partially expose the second pillars 242.

[0078] Multiple conductive materials 26 are filled in multiple second through holes 251 and partially protrude from the encapsulation layer 25, thereby obtaining an encapsulation structure 2a.

[0079] In one embodiment, a metal layer 28 may be formed on the side surface of the second through-hole 251 and on a portion of the encapsulation layer 25, and a conductive material 26 may be filled on the metal layer 28 in the second through-hole 251. In another embodiment, the metal layer 28 may not be formed, and the conductive material 26 may be filled directly into the second through-hole 251.

[0080] An electronic device 2b can be attached to the packaging structure 2a via a plurality of conductive materials 26, thereby obtaining the electronic package 2 of the present invention.

[0081] In summary, in the electronic package and its manufacturing method of the present invention, by forming a second through-hole with exposed conductive pillars in the packaging layer and filling the second through-hole with conductive material, the gap between the electronic device connected via the conductive material and the packaging layer of the packaging structure can be reduced, which is beneficial for reducing the overall thickness of the electronic package. Furthermore, forming the through-hole by exposure display is not limited by the aspect ratio of laser drilling, which is beneficial for the fabrication of the conductive pillars and the adhesion between the conductive material and the conductive pillars, thus avoiding warpage problems. In addition, the CTE of the dielectric layer and insulating layer gradually increases from bottom to top, which helps reduce warpage during the reflow process and avoids risks such as solder ball peeling, cracking, or displacement after packaging.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Those skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. An electronic package, comprising: a circuit structure having a circuit layer; an insulating layer disposed on the circuit structure and having a plurality of first vias exposing the circuit layer; an electronic element disposed on the insulating layer and electrically connected to the circuit structure; a plurality of conductive posts each having a first post body and a second post body connected thereto, the first post body formed in the first via and the second post body protruding from the insulating layer; a packaging layer formed on the insulating layer and covering the electronic element and the second post body, and having a plurality of second vias exposing top surfaces of the second post body, the second vias having a depth less than a thickness of the packaging layer, and the second post body having a size greater than a size of the second vias; and a plurality of conductive materials filled in the plurality of second vias and partially protruding from the packaging layer. The second post body protrudes from the insulating layer by a height equal to or less than a height of the electronic element disposed on the insulating layer.

2. The electronic package of claim 1, wherein, 3. A method of manufacturing an electronic package, comprising: providing a circuit structure having a circuit layer; forming an insulating layer on the circuit structure, wherein the insulating layer has a plurality of first vias exposing the circuit layer; forming a plurality of conductive posts in the plurality of first vias and disposing an electronic element on the insulating layer, the plurality of conductive posts each having a first post body and a second post body connected thereto, such that the first post body is formed in the first via and the second post body protrudes from the insulating layer, and such that the electronic element is electrically connected to the circuit structure; forming a packaging layer on the insulating layer such that the packaging layer covers the electronic element and the second post body, wherein the packaging layer has a plurality of second vias exposing top surfaces of the second post body, wherein the second vias have a depth less than a thickness of the packaging layer, and the second post body has a size greater than a size of the second vias; and filling a plurality of conductive materials in the plurality of second vias and partially protruding the plurality of conductive materials from the packaging layer. The second post body protrudes from the insulating layer by a height equal to or less than a height of the electronic element disposed on the insulating layer.

4. The method of making an electronic package of claim 3, wherein, ​

Images