Method and device for determining adjustment strategy, storage medium and electronic device

Abstract

The embodiment of the present application provides a method and device for determining an adjustment strategy, a storage medium and an electronic device, the method comprising: determining the instruction queues corresponding to the multiple processing cores of the target device; determining the instruction information table corresponding to the multiple instruction queues, the instruction information table at least including: the effective address of the second instruction belonging to the target type in the first instruction, and the position of the second instruction in the instruction queue to which it belongs; determining the adjustment strategy for the sniffing operation of each processing core according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue, and the positions corresponding to any two adjacent second instructions. The problem that the cache consistency control protocol adopted by the RISC‑V multi-core processor is fixed, resulting in many invalid snoop operations in the cache consistency control process of the RISC‑V multi-core processor, and thus resulting in low processing efficiency of the RISC‑V multi-core processor is solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular, to a method and device for determining an adjustment strategy, a storage medium, and an electronic device. Background Art

[0002] The fifth generation of reduced instruction set computer version 5 (RISC-V) is a new instruction set architecture. It is an open instruction set architecture based on the principle of reduced instruction set computing (RISC). It is open source and can be freely used by any academic institution or commercial organization. It has the advantage of independent control. In related technologies, RISC-V multi-core processors are increasingly used as special-purpose processors (not general-purpose processors, and the main programs / algorithms running on special-purpose processors are fixed / unified). Among them, one of the application scenarios includes: using RISC-V multi-core processors for parallel computing. In the case of parallel computing, each processing core (core) of the RISC-V multi-core processor runs a set of specific operations. There is communication and data interaction between cores, but the frequency of interaction is low.

[0003] However, with the widespread application of RISC-V multi-core processors, more and more problems have arisen. For example, the cache consistency control protocol used by RISC-V multi-core processors is fixed, so that no matter what the specific application scenario of the application layer corresponding to the RISC-V multi-core processor is, the corresponding state process jump and snoop operation scheme in cache consistency control are fixed. However, in specific fields or specific applications, many state process jumps and snoop schemes in cache consistency control are invalid. A large number of invalid processes will lead to low overall prediction efficiency of RISC-V multi-core processors.

[0004] Regarding the related technology, the cache consistency control protocol used by the RISC-V multi-core processor is fixed, which leads to many invalid snoop operations in the cache consistency control process of the RISC-V multi-core processor, which in turn leads to the low processing efficiency of the RISC-V multi-core processor, and has not yet been effectively solved. Summary of the invention

[0005] The embodiments of the present application provide a method and device for determining an adjustment strategy, a storage medium, and an electronic device, so as to at least solve the problem that the cache consistency control protocol adopted by the RISC-V multi-core processor in the related art is fixed, resulting in many invalid snoop operations in the cache consistency control process of the RISC-V multi-core processor, thereby resulting in low processing efficiency of the RISC-V multi-core processor.

[0006] According to one embodiment of the present application, a method for determining an adjustment strategy is provided, comprising: determining instruction queues corresponding to multiple processing cores of a target device, wherein the instruction queues include: a first instruction issued by each processing core and currently not executed; determining instruction information tables corresponding to multiple instruction queues, wherein the instruction information table includes at least: an effective address of a second instruction belonging to a target type in the first instruction, and a position of the second instruction in the instruction queue to which it belongs; determining an adjustment strategy for a sniffing operation on each processing core according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to any two adjacent second instructions, wherein the sniffing operation is used to indicate to each processing core an operation allowed to be performed on other processing cores between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores other than each processing core among the multiple processing cores.

[0007] In an exemplary embodiment, determining instruction queues corresponding to multiple processing cores of a target device includes: determining a first-level cache corresponding to each processing core, wherein the first-level cache stores the first instruction corresponding to each processing core; obtaining the first instruction from the first-level cache to obtain the instruction queue, wherein the first-level cache is a cache directly connected to each processing core.

[0008] In an exemplary embodiment, obtaining the first instruction from the first-level cache to obtain the instruction queue includes: determining a first number of the first instructions allowed to be obtained from the first-level cache, wherein the first number is determined by a second number of applications running on each processing core; obtaining a first number of the first instructions from the first-level cache, and storing the first number of the first instructions in sequence in a preset queue corresponding to each processing core to obtain the instruction queue.

[0009] In an exemplary embodiment, obtaining the first instruction from the first-level cache to obtain the instruction queue includes: determining a preset execution order of W first instructions included in the first-level cache, where W is a positive integer; and determining the instruction queue by the preset execution order.

[0010] In an exemplary embodiment, determining the instruction queue through the preset execution order includes: determining the third instruction among W first instructions through the preset execution order, wherein the third instruction is the Nth instruction among the W first instructions, and N is an integer greater than 1; determining the instruction queue corresponding to each processing core through the third instruction.

[0011] In an exemplary embodiment, the instruction queue corresponding to each processing core is determined by the third instruction, including: an acquisition step: acquiring the third instruction into a preset queue corresponding to each processing core; an update step: when it is determined that the third instruction is not a branch instruction, determining a fourth instruction to be executed after the third instruction by the preset execution order, and updating the fourth instruction to the third instruction; when it is determined that the third instruction is a branch instruction, predicting the execution result of the third instruction to obtain a prediction result; updating the fifth instruction indicated by the prediction result in W first instructions to the third instruction; and looping M times the acquisition step and the update step to obtain the instruction queue, wherein M is used to represent the first number of the first instructions allowed to be obtained from the first-level cache.

[0012] In an exemplary embodiment, determining the instruction information table corresponding to the plurality of instruction queues includes: parsing the first instructions included in the plurality of instruction queues to obtain parsing results; and determining the instruction information table according to the parsing results.

[0013] In an exemplary embodiment, the first instruction included in the multiple instruction queues is parsed to obtain a parsing result, including: parsing the first instruction according to the instruction architecture of the target type of instruction to obtain the instruction type of the first instruction and the effective address of the first instruction, wherein the target type includes the instruction type; and determining the position of the first instruction in the instruction queue to which the first instruction belongs; determining the instruction type, the effective address, and the position of the first instruction in the instruction queue to which the first instruction belongs as the parsing result.

[0014] In an exemplary embodiment, the first instruction is parsed according to the instruction architecture of the target type of instruction to obtain the instruction type of the first instruction, including: parsing the first instruction according to the instruction architecture to obtain the operation code of the first instruction; when the operation code is a first value, determining that the instruction type of the first instruction is the first type; when the operation code is a second value, determining that the instruction type of the first instruction is the second type.

[0015] In an exemplary embodiment, the first instruction is parsed according to the instruction architecture of the target type of instruction to obtain the effective address of the first instruction, including: parsing the first instruction according to the instruction architecture to obtain the index of the first source register recorded in the first instruction, and obtaining a sign-bit extended K-bit immediate number of the first instruction, wherein K is a positive integer; and determining the sum of the index and the K-bit immediate number as the effective address.

[0016] In an exemplary embodiment, the instruction information table is determined through the parsing result, including: determining a fill position in the instruction information table according to the instruction type and the target processing core to which the first instruction belongs, wherein the multiple processing cores include: the target processing core; filling the effective address and the position of the first instruction in the instruction queue to which the first instruction belongs into the fill position to obtain the instruction information table.

[0017] In an exemplary embodiment, an adjustment strategy for the sniffing operation of each processing core is determined based on the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, including: determining the sixth instruction and the seventh instruction among the any two adjacent second instructions through the instruction information table; determining the first effective address and the first position corresponding to the sixth instruction, and determining the second effective address and the second position corresponding to the seventh instruction; determining the eighth instruction of the other processing cores, wherein the third position of the eighth instruction is between the first position and the second position; and determining the adjustment strategy through the eighth instruction, the first effective address, and the second effective address.

[0018] In an exemplary embodiment, determining the sixth instruction and the seventh instruction among any two adjacent second instructions through the instruction information table includes: determining the query position corresponding to the target processing core corresponding to the instruction queue in the instruction information table, wherein the multiple processing cores include: the target processing core; the query position includes: a filling position; the filling position is determined by the instruction type of the first instruction in the target type, and the target processing core to which the first instruction belongs; and obtaining the sixth instruction and the seventh instruction from the query position.

[0019] In an exemplary embodiment, determining the eighth instruction of the other processing core includes: traversing remaining positions in the instruction information table except the query position; and determining the eighth instruction from the remaining positions.

[0020] In an exemplary embodiment, determining the eighth instruction of the other processing core includes: obtaining all instructions in other instruction queues whose positions are between the first position and the second position, wherein the other instruction queues are other instruction queues among the multiple instruction queues except the instruction queue; and determining the instruction of the target type among all the instructions as the eighth instruction.

[0021] In an exemplary embodiment, the adjustment strategy is determined by the eighth instruction, the first effective address, and the second effective address, including: determining the third effective address of the eighth instruction through the instruction information table; determining whether the third effective address is consistent with a fourth effective address, wherein the fourth effective address includes at least one of the following: the first effective address, the second effective address; when the third effective address is consistent with the fourth effective address, determining the adjustment strategy to allow each processing core to perform the sniffing operation on the other processing cores.

[0022] In an exemplary embodiment, after determining whether the third effective address is consistent with the fourth effective address, the method further includes: when the third effective address and the fourth effective address are inconsistent, determining that the adjustment strategy is to prohibit each processing core from performing the sniffing operation on the other processing cores.

[0023] In an exemplary embodiment, after determining the adjustment strategy for the sniffing operation of each processing core based on the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, the method further includes: when each processing core executes the any two adjacent second instructions, determining whether there is a branch instruction in the any two adjacent second instructions; when there is a branch instruction in the any two adjacent second instructions, determining the execution result of the branch instruction; and determining the execution method of the adjustment strategy through the execution result.

[0024] In an exemplary embodiment, determining the execution method of the adjustment strategy through the execution result includes: determining a ninth instruction and a tenth instruction, wherein the ninth instruction is the first instruction of any two adjacent second instructions, and the tenth instruction is the second instruction of any two adjacent second instructions; when the ninth instruction is a branch instruction, determining whether the tenth instruction is the eleventh instruction indicated by the execution result, or an instruction allowed to be executed after the eleventh instruction; when the tenth instruction is the eleventh instruction or an instruction allowed to be executed after the eleventh instruction, determining that the adjustment strategy is allowed to be executed.

[0025] According to another embodiment of the present application, a device for determining an adjustment strategy is provided, comprising: a first determination module, used to determine instruction queues corresponding to multiple processing cores of a target device, wherein the instruction queues include: first instructions issued by each processing core and currently not executed; a second determination module, used to determine instruction information tables corresponding to multiple instruction queues, wherein the instruction information table includes at least: the effective address of a second instruction belonging to the target type in the first instruction, and the position of the second instruction in the instruction queue to which it belongs; a third determination module, used to determine an adjustment strategy for a sniffing operation on each processing core according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to any two adjacent second instructions, wherein the sniffing operation is used to indicate to each processing core an operation allowed to be performed on other processing cores between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores other than each processing core among the multiple processing cores.

[0026] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0027] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0028] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0029] Through the present application, the instruction queues corresponding to the multiple processing cores of the target device are determined, wherein the instruction queues include: the first instruction issued by each processing core and not currently executed; the instruction information tables corresponding to the multiple instruction queues are determined, wherein the instruction information table includes at least: the effective address of the second instruction belonging to the target type in the first instruction, and the position of the second instruction in the instruction queue to which it belongs; according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue, and the positions corresponding to any two adjacent second instructions, the adjustment strategy of the sniffing operation of each processing core is determined, wherein the sniffing operation is used to indicate that each processing core is allowed to perform operations on other processing cores between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores other than each processing core in the multiple processing cores. Therefore, the problem that the cache consistency control protocol adopted by the RISC-V multi-core processor is fixed in the related art, resulting in many invalid snoop operations in the cache consistency control process of the RISC-V multi-core processor, thereby resulting in low processing efficiency of the RISC-V multi-core processor can be solved. Improved the processing efficiency of RISC-V multi-core processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a hardware structure block diagram of a computer terminal of a method for determining an adjustment strategy in an embodiment of the present application;

[0031] Figure 2 is a flow chart of a method for determining an adjustment strategy according to an embodiment of the present application;

[0032] Figure 3 is a schematic diagram of a multi-core processor cache architecture according to a method for determining an adjustment strategy in an embodiment of the present application;

[0033] Figure 4 It is a schematic diagram of the instruction architecture corresponding to the RISC-V instruction set according to the method for determining the adjustment strategy of an embodiment of the present application;

[0034] Figure 5 It is a schematic diagram of the state jump process of the MESI cache consistency protocol according to the method for determining the adjustment strategy of an embodiment of the present application;

[0035] Figure 6 It is a schematic diagram of the snoop process of the MESI cache consistency protocol according to the method for determining the adjustment strategy of an embodiment of the present application;

[0036] Figure 7 is a schematic diagram of an instruction processing optimization module according to a method for determining an adjustment strategy according to an embodiment of the present application;

[0037] Figure 8 is a schematic diagram of an instruction set related to RISC-C Load according to a method for determining an adjustment strategy according to an embodiment of the present application;

[0038] Figure 9 is a schematic diagram of an instruction set related to RISC-C Store according to a method for determining an adjustment strategy according to an embodiment of the present application;

[0039] Figure 10 It is a structural block diagram of a device for determining an adjustment strategy according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0041] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0042] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 FIG. 1 is a hardware structure block diagram of a computer terminal for determining a method for adjusting a strategy according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0043] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for allocating load resources in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the above method is implemented. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0044] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0045] Figure 2 is a flow chart of a method for determining an adjustment strategy according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0046] Step S202, determining instruction queues corresponding to the multiple processing cores of the target device, wherein the instruction queues include: first instructions issued by each processing core and not currently executed;

[0047] Step S204, determining instruction information tables corresponding to the plurality of instruction queues, wherein the instruction information table includes at least: an effective address of a second instruction of a target type in the first instruction, and a position of the second instruction in the instruction queue to which it belongs;

[0048] It should be noted that the target type specifically refers to Load and Store instructions. The instructions issued by each processing core are not limited to Load and Store instructions, so it is necessary to determine the second instruction belonging to the target type from the instruction queue and obtain the instruction information table of the second instruction.

[0049] Step S206, determining an adjustment strategy for the sniffing operation of each processing core according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, wherein the sniffing operation is used to indicate the operations allowed to be performed on other processing cores by each processing core between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores among the multiple processing cores except for each processing core.

[0050] It should be noted that the determined adjustment strategy for the sniffing operation specifically refers to the adjustment strategy for the sniffing operation of each processing core between any two adjacent second instructions.

[0051] It should be noted that the sniffing operation is the Snoop operation. The CPU (or processing core) perceives the behavior of other CPUs (such as reading and writing a cache line) by sniffing the request messages sent by other CPUs in the line. Sometimes the CPU also needs to respond to certain request messages in the bus. This is called the "bus sniffing mechanism".

[0052] Through the above steps, the instruction queues corresponding to the multiple processing cores of the target device are determined, wherein the instruction queues include: the first instruction issued by each processing core and not currently executed; the instruction information tables corresponding to the multiple instruction queues are determined, wherein the instruction information table at least includes: the effective address of the second instruction belonging to the target type in the first instruction, and the position of the second instruction in the instruction queue to which it belongs; according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue, and the positions corresponding to any two adjacent second instructions, the adjustment strategy of the sniffing operation of each processing core is determined, wherein the sniffing operation is used to indicate that each processing core is allowed to perform operations on other processing cores between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores other than each processing core in the multiple processing cores. Therefore, the problem that the cache consistency control protocol adopted by the RISC-V multi-core processor is fixed in the related art, resulting in many invalid snoop operations in the cache consistency control process of the RISC-V multi-core processor, thereby resulting in low processing efficiency of the RISC-V multi-core processor can be solved. Improved the processing efficiency of RISC-V multi-core processors.

[0053] In an exemplary embodiment, determining instruction queues corresponding to multiple processing cores of a target device includes: determining a first-level cache corresponding to each processing core, wherein the first-level cache stores the first instruction corresponding to each processing core; obtaining the first instruction from the first-level cache to obtain the instruction queue, wherein the first-level cache is a cache directly connected to each processing core.

[0054] It should be noted that the multiple processing cores in the embodiment of the present application may be multiple processing cores in a RISC-V multi-core processor. The cache architecture of a multi-core processor is as follows: Figure 3 As shown, the central processing unit (CPU) includes processing cores 0, 1, 2, and 3. Each processing core has its own L1 cache, and four processing cores share a L2 cache. The L2 cache is connected to a double data rate synchronous dynamic random access memory (DDR) outside the CPU.

[0055] Optionally, in one case, the memory is DRAM (Dynamic RAM) and the cache is SRAM (Static RAM).

[0056] The first-level cache consists of two parts: L1I Cache (first-level instruction cache) and L1D Cache (first-level data cache). The closer the cache is to the CPU, the faster it is and the more expensive it is. When the Core queries the cache, it searches from near to far, giving priority to searching from the first-level cache; the unit of searching from the cache is called a cache line; if it is found, the search ends, and if it is not found, the second-level cache is searched. If the second-level cache is still not found, the main memory is searched; the main memory here refers to the memory (DDR); the unit of searching from the memory is called a memory line.

[0057] In the embodiment of the present application, the first instruction is obtained from the first-level instruction cache in the first-level cache exclusively used by each processing core. Optionally, the first instruction can be pushed into the instruction queue according to the order in which the first instruction is obtained.

[0058] Optionally, obtaining the first instruction from the first-level cache to obtain the instruction queue includes: determining a first number of the first instructions allowed to be obtained from the first-level cache, wherein the first number is determined by a second number of applications running on each processing core; obtaining a first number of the first instructions from the first-level cache, and storing the first number of the first instructions in sequence in a preset queue corresponding to each processing core to obtain the instruction queue.

[0059] That is, in one implementation, the first instruction is acquired according to the first number of first instructions allowed to be acquired from the L1 cache. Optionally, the acquired first number of instructions may be stored in a preset queue in the acquisition order, and the preset queue may be an empty queue preset for each processing core.

[0060] Optionally, obtaining the first instruction from the first-level cache to obtain the instruction queue includes: determining a preset execution order of W first instructions included in the first-level cache, where W is a positive integer; and determining the instruction queue according to the preset execution order.

[0061] That is, in another implementation, the instruction queue is determined according to the preset execution order of the W first instructions in the first-level cache.

[0062] Specifically, determining the instruction queue through the preset execution order includes: determining the third instruction among W first instructions through the preset execution order, wherein the third instruction is the Nth instruction among the W first instructions, and N is an integer greater than 1; determining the instruction queue corresponding to each processing core through the third instruction.

[0063] It is understandable that, since it takes time to analyze any two adjacent second instructions in the instruction queue, when obtaining the first instruction from the first-level cache, it cannot be obtained from the first instruction of the W first instructions, but the first instruction can be obtained from the Nth instruction of the W first instructions. Thus, it can be ensured that before the adjustment strategy for the sniffing operation of each processing core is determined according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, the two adjacent second instructions are not executed, thereby ensuring that the adjustment strategy is effectively implemented.

[0064] Optionally, in another implementation, the third instruction among W first instructions is determined through the preset execution order, and starting from the third instruction, a first number of first instructions are acquired into the preset queue to obtain the execution queue.

[0065] Furthermore, the instruction queue corresponding to each processing core is determined by the third instruction, including: an acquisition step: acquiring the third instruction into a preset queue corresponding to each processing core; an update step: when it is determined that the third instruction is not a branch instruction, determining a fourth instruction to be executed after the third instruction by the preset execution order, and updating the fourth instruction to the third instruction; when it is determined that the third instruction is a branch instruction, predicting the execution result of the third instruction to obtain a prediction result; updating the fifth instruction indicated by the prediction result in W of the first instructions to the third instruction; and looping M times the acquisition step and the update step to obtain the instruction queue, wherein M is used to represent the first number of the first instructions allowed to be obtained from the first-level cache.

[0066] In the process of acquiring the first instruction into the preset queue, starting from the third instruction, for each acquired instruction (such as the third instruction and the fourth instruction), it is necessary to determine whether the instruction is a branch instruction. In the case where the instruction is a branch instruction, it is necessary to predict the execution result of the instruction, and acquire the fifth instruction corresponding to the predicted result into the preset queue. It should be noted that if the prediction result is inaccurate, it will cause all instructions in the instruction queue from the fifth instruction onwards to be acquired incorrectly, so that the sniffing operation determined for the instructions from the fifth instruction onwards is invalid.

[0067] Among them, a branch instruction is an instruction in a computer program that is used to select different execution paths based on different conditions. These instructions allow the program to jump to different code blocks during execution based on whether the conditions are met, thereby implementing branch logic in the program. Common branch instructions include conditional branch instructions, unconditional branch instructions, etc. By using branch instructions, the program can execute different codes based on different conditions, thereby implementing different processing logic in different situations.

[0068] In an exemplary embodiment, determining the instruction information table corresponding to the plurality of instruction queues includes: parsing the first instructions included in the plurality of instruction queues to obtain parsing results; and determining the instruction information table according to the parsing results. That is, after obtaining the instruction queues, the first instructions in the instruction queues are parsed in sequence according to the order in which they are pushed into the instruction queues (i.e., the acquisition order) to obtain the parsing results, thereby obtaining the execution information table.

[0069] Optionally, the first instruction included in the multiple instruction queues is parsed to obtain a parsing result, including: parsing the first instruction according to the instruction architecture of the target type of instruction to obtain the instruction type of the first instruction, and the effective address of the first instruction, wherein the target type includes the instruction type; and determining the position of the first instruction in the instruction queue to which the first instruction belongs; determining the instruction type, the effective address, and the position of the first instruction in the instruction queue to which the first instruction belongs as the parsing result.

[0070] Furthermore, the first instruction is parsed according to the instruction architecture of the target type of instruction to obtain the instruction type of the first instruction, including: parsing the first instruction according to the instruction architecture to obtain the operation code of the first instruction; when the operation code is a first value, determining that the instruction type of the first instruction is the first type; when the operation code is a second value, determining that the instruction type of the first instruction is the second type.

[0071] In the embodiment of the present application, the target type of instruction specifically refers to Load and Store instructions. Load and Store instructions both belong to the RISC-V instruction set. The instruction architecture corresponding to the RISC-V instruction set is as follows: Figure 4 As shown, the Load instruction belongs to the I type instruction (equivalent to the first type), and the Store instruction belongs to the S type instruction (equivalent to the second type). Specifically, Figure 4 In the instruction, opcode is the operation code, which is 7 bits wide and is located in bits 0-6 of the instruction. The opcode of the I-type Load instruction is 7'b000011 (equivalent to the first value); the opcode of the S-type Store instruction is 7'b0100011 (equivalent to the second value).

[0072] Therefore, whether the first instruction is of the first type or the second type can be determined by the operation code of the first instruction, so that the instruction information table can be obtained quickly and efficiently.

[0073] Furthermore, the first instruction is parsed according to the instruction architecture of the target type of instruction to obtain the effective address of the first instruction, including: parsing the first instruction according to the instruction architecture to obtain the index of the first source register recorded in the first instruction, and obtaining a sign-bit extended K-bit immediate number of the first instruction, wherein K is a positive integer; and determining the sum of the index and the K-bit immediate number as the effective address.

[0074] Figure 4The "imm[]" in the table represents an immediate value. Therefore, the K-bit immediate value of the first instruction of the first type, i.e., the Load instruction, is imm[11:0], which is at bits 20-31 of the instruction. The K-bit immediate value of the first instruction of the second type, i.e., the Store instruction, is imm[4:0]+imm[11:5]. Optionally, K is equal to 12. The first source register is the rs1 register.

[0075] Optionally, the instruction information table is determined through the parsing result, including: determining a filling position in the instruction information table according to the instruction type and the target processing core to which the first instruction belongs, wherein the multiple processing cores include: the target processing core; filling the effective address and the position of the first instruction in the instruction queue to which the first instruction belongs into the filling position to obtain the instruction information table.

[0076] Optionally, the instruction information table may be as shown in Table 1. Each row corresponds to each processing core, and each column corresponds to the effective address (Load_addr) and position (Load_instr_position) of the first instruction of the first type, and the effective address (Store_addr) and position (Store_instr_position) of the first instruction of the second type. Optionally, the position is filled, for example, the row where core0 is located in Table 1 is used to fill the position of Load_addr and Load_instr_position, or the row where core0 is located is used to fill the position of Store_addr and Store_instr_position.

[0077] Table 1

[0078] Load_addr Load_instr_position Store_addr Store_instr_position Core0 Core0_Load_addr_0Core0_Load_addr_1Core0_Load_addr_2…… Core0_Load_instr_position_0Core0_Load_instr_position_1Core0_Load_instr_position_2…… Core0_Store_addr_0Core0_Store_addr_1Core0_Store_addr_2…… Core0_Store_instr_position_0Core0_Store_instr_position_1Core0_Store_instr_position_2 Core1 Core1_Load_addr_0Core1_Load_addr_1Core1_Load_addr_2…… Core1_Load_instr_position_0Core1_Load_instr_position_1Core1_Load_instr_position_2…… Core1_Store_addr_0Core1_Store_addr_1Core1_Store_addr_2…… Core1_Store_instr_position_0Core1_Store_instr_position_1Core1_Store_instr_position_2 Core2 Core2_Load_addr_0Core2_Load_addr_1Core2_Load_addr_2…… Core2_Load_instr_position_0Core2_Load_instr_position_1Core2_Load_instr_position_2…… Core2_Store_addr_0Core2_Store_addr_1Core2_Store_addr_2…… Core2_Store_instr_position_0Core2_Store_instr_position_1Core2_Store_instr_position_2 Core3 Core3_Load_addr_0Core3_Load_addr_1Core3_Load_addr_2…… Core3_Load_instr_position_0Core3_Load_instr_position_1Core3_Load_instr_position_2…… Core3_Store_addr_0Core3_Store_addr_1Core3_Store_addr_2…… Core3_Store_instr_position_0Core3_Store_instr_position_1Core3_Store_instr_position_2

[0079] In an exemplary embodiment, an adjustment strategy for the sniffing operation of each processing core is determined based on the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, including: determining the sixth instruction and the seventh instruction among the any two adjacent second instructions through the instruction information table; determining the first effective address and the first position corresponding to the sixth instruction, and determining the second effective address and the second position corresponding to the seventh instruction; determining the eighth instruction of the other processing cores, wherein the third position of the eighth instruction is between the first position and the second position; and determining the adjustment strategy through the eighth instruction, the first effective address, and the second effective address.

[0080] Optionally, determining the sixth instruction and the seventh instruction among any two adjacent second instructions through the instruction information table includes: determining the query position corresponding to the target processing core corresponding to the instruction queue in the instruction information table, wherein the multiple processing cores include: the target processing core; the query position includes: a fill position; the fill position is determined by the instruction type of the first instruction in the target type, and the target processing core to which the first instruction belongs; obtaining the sixth instruction and the seventh instruction from the query position.

[0081] Exemplarily, as shown in Table 1, if core0 is the target processing core, the query position of core0 is the row where core0 is located in Table 1. Any two adjacent second instructions may be two adjacent Load instructions, two adjacent Store instructions, adjacent Load instructions and Store instructions, or adjacent Store instructions and Load instructions. It is specifically determined by querying the position recorded in the instruction information table. This is because the position and effective address information are directly reflected in the instruction information table. It can also be understood that the sixth instruction, the seventh instruction, the first effective address and the first position of the sixth instruction, and the second effective address and the second position corresponding to the seventh instruction are determined at the same time.

[0082] In an exemplary embodiment, determining the eighth instruction of the other processing core includes: traversing remaining positions in the instruction information table except the query position; and determining the eighth instruction from the remaining positions.

[0083] For example, if core0 is the target processing core, as shown in Table 1, the rows where core1, core2, and core3 are located are the remaining positions.

[0084] For another example, if core0 is the target processing core, any two adjacent second instructions of core0 are a Load instruction and a Store instruction. The position of the Load instruction is Core0_Load_instr_position_0=3, and the position of the Store instruction is Core0_Store_instr_position_0=10;

[0085] If the position of the Load instruction of Core1 is Core1_Load_instr_position_0=5, it is determined that the Load instruction of Core1 is between the Load and Store instructions of Core0.

[0086] If the position of the Load instruction of Core1 is Core1_Load_instr_position_0=11, it is determined that the Load instruction of Core1 is not between the Load and Store instructions of Core0.

[0087] It should be noted that the first number of first instructions allowed to be included in the instruction queues corresponding to the multiple processing cores is the same. Core0_Load_instr_position_0=3 can be understood as the instruction with position 3 in the instruction queues corresponding to other processing cores will be executed simultaneously.

[0088] In an exemplary embodiment, determining the eighth instruction of the other processing core includes: obtaining all instructions in other instruction queues whose positions are between the first position and the second position, wherein the other instruction queues are other instruction queues among the multiple instruction queues except the instruction queue; and determining the instruction of the target type among all the instructions as the eighth instruction.

[0089] For example, if core0 is the target processing core, any two adjacent second instructions of core0 are a Load instruction and a Store instruction. The first position of the Load instruction is Core0_Load_instr_position_0=3, and the second position of the Store instruction is Core0_Store_instr_position_0=10;

[0090] Then all instructions between positions 3-10 in other instruction queues are determined, and the instruction belonging to the target type among all instructions is determined as the eighth instruction.

[0091] In an exemplary embodiment, the adjustment strategy is determined by the eighth instruction, the first effective address, and the second effective address, including: determining the third effective address of the eighth instruction through the instruction information table; determining whether the third effective address is consistent with a fourth effective address, wherein the fourth effective address includes at least one of the following: the first effective address, the second effective address; when the third effective address is consistent with the fourth effective address, determining the adjustment strategy to allow each processing core to perform the sniffing operation on the other processing cores.

[0092] Therefore, by sorting out the instruction information table, any two adjacent second instructions and the eighth instruction located between any two adjacent second instructions can be simply and directly determined, thereby determining the execution strategy of the sniffing operation between any two adjacent second instructions for each processing core.

[0093] In an exemplary embodiment, after determining whether the third effective address is consistent with the fourth effective address, the method further includes: when the third effective address and the fourth effective address are inconsistent, determining that the adjustment strategy is to prohibit each processing core from performing the sniffing operation on the other processing cores.

[0094] Therefore, when it is determined that the third effective address is inconsistent with the fourth effective address, it can be determined that between any two adjacent second instructions, each processing core does not need to perform a sniffing operation. Thus, invalid sniffing operations are omitted and the processing efficiency of the RISC-V multi-core processor is improved.

[0095] In an exemplary embodiment, after determining the adjustment strategy for the sniffing operation of each processing core based on the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, the method further includes: when each processing core executes the any two adjacent second instructions, determining whether there is a branch instruction in the any two adjacent second instructions; when there is a branch instruction in the any two adjacent second instructions, determining the execution result of the branch instruction; and determining the execution method of the adjustment strategy through the execution result.

[0096] It is understandable that after the adjustment strategy is determined, the execution result of the branch instruction of each processing core is determined, and if the execution result is the predicted result, the adjustment strategy is allowed to be executed.

[0097] In an exemplary embodiment, determining the execution method of the adjustment strategy through the execution result includes: determining a ninth instruction and a tenth instruction, wherein the ninth instruction is the first instruction of any two adjacent second instructions, and the tenth instruction is the second instruction of any two adjacent second instructions; when the ninth instruction is a branch instruction, determining whether the tenth instruction is the eleventh instruction indicated by the execution result, or an instruction allowed to be executed after the eleventh instruction; when the tenth instruction is the eleventh instruction or an instruction allowed to be executed after the eleventh instruction, determining that the adjustment strategy is allowed to be executed.

[0098] Optionally, when it is determined that the tenth instruction is not the eleventh instruction indicated by the execution result, or is an instruction allowed to be executed after the eleventh instruction, it is determined that the execution of the adjustment strategy is prohibited; each processing core is instructed to suspend the execution of any two adjacent second instructions; the instruction queue corresponding to each processing core is re-acquired, and the adjustment strategy is updated through the re-acquired instruction queue.

[0099] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0100] In order to better understand the process of determining the above adjustment strategy, the implementation process of the above adjustment strategy determination method is described below in combination with an optional embodiment, but it is not used to limit the technical solution of the embodiment of the present application.

[0101] In the related art, Figure 3 In the multi-core processor shown, there may be multiple copies of the same data in different caches. The existence of these copies seriously affects the correctness of program execution. For example, the same data in L2 Cache may have copies in L1 Cache of core0 and L1 Cache of core1, and the values ​​of the data in the copies are likely to be different. In this way, a cache coherence protocol is needed to manage multiple copies of shared data. Common cache coherence protocols include MESI protocol.

[0102] Optionally, in concurrent scenarios (such as multi-threading), if the same variable is operated, how to ensure that the variable cached in each core is the correct value involves some "cache consistency" protocols. Among them, the most widely used protocol for RISC-V processors is the MESI protocol.

[0103] The MESI protocol is an Invalidate-based cache consistency protocol and is one of the most commonly used protocols that supports write-back cache. It belongs to the CPU cache consistency protocol.

[0104] It should be noted that there is a Flag field in the cache line information, which indicates four states, which correspond to the following states: M, E, S, and I. That is, Modified, Exclusive, Shared, and Invalid.

[0105] Among them, M state: means that the content of the cache line has been modified, and the cache line is only cached in the first-level cache exclusive to the core. The data in the cache line in this state is different from the data in the memory, and it will be written to the memory at some point in the future (when other cores want to read the content of the cache line. Or when other cores want to modify the content in the memory corresponding to the cache).

[0106] Among them, the E state: means that the content in the memory corresponding to the cache line is only cached by this core, and other cores do not cache the content in the memory line corresponding to the cache. The content in the cache line in this state is consistent with the content in the memory. The cache can be changed to the S state when any other core reads the content in the memory corresponding to the cache. Or the local core (the core that occupies the cache line alone) writes to the cache and it will become the M state.

[0107] Among them, S state: This state means that the data exists not only in the local Core cache, but also in the cache of other Cores. The data in this state is consistent with the data in the memory. When other Cores modify the content of the memory corresponding to the cache line, the cache line will be changed to I state.

[0108] Among them, the I state represents that the content in the cache line is invalid.

[0109] Optionally, in an optional embodiment of the present application, the state jump process of the MESI cache consistency protocol is as follows: Figure 5 As shown, based on the state jump, the snoop process of the MESI cache consistency protocol is as follows Figure 6 shown.

[0110] for Figure 5 or Figure 6 It should be noted that local refers to the operation of Core0 on Core0's L1 cache, and remote refers to the operation of other Cores (excluding Core0) on Core0's L1 cache. For example, for the cacheline of Core0's L1 Cache, the read and write operations of Core0 on Core0's L1 Cache are called local reads or local writes, while the operations of other Cores on Core0's L1 Cache initiated through L2 Cache are called remote reads or remote writes. Figure 3 For the cacheline of L2 Cache, since it is shared by 4 cores, there is no such thing as Local, all operations are Remote.

[0111] based on Figure 6 , the traditional MESI consistency protocol is handled as follows:

[0112] 1: The initial state of the cache line is I state, and the data is empty.

[0113] 2: In the I state,

[0114] 1) Local Read: requires snoop operation.

[0115] If other caches do not have this data, this cache fetches the data from the memory and the cache line status changes to E;

[0116] If the other cache has this data and its status is M, the data will be updated to the memory, and the cache will fetch the data from the memory. The cache line status of both caches will become S.

[0117] If other caches have this data and their status is S or E, this cache fetches the data from the memory, and the cache line status of these caches becomes S.

[0118] 2) Local Write:

[0119] Get data from memory, modify it in cache, and change the state to M;

[0120] If other caches have this data and the status is M, the data must be updated to the memory first;

[0121] If other caches have this data, the cache line status of other caches becomes I;

[0122] In Remote Read and Remote Write operations, the next state after the I state is still I.

[0123] 3: In E state:

[0124] Local Read: Get data from the cache, and the status remains unchanged.

[0125] Local Write: Modify the data in the cache and the status becomes M.

[0126] Remote Read: Data is shared with other cores and the status becomes S.

[0127] Remote Write: The data is modified, the cache line can no longer be used, and the status becomes I.

[0128] 4: In S state: snoop operation is required.

[0129] Local Read: Get data from the cache, and the status remains unchanged.

[0130] Local Write: Modify the data in the cache, the state becomes M, and the state of the cache line shared by other cores becomes I.

[0131] Remote Read: The status remains unchanged.

[0132] Remote Write: The data is modified, the cache line can no longer be used, and the status becomes I.

[0133] 5: In M state: snoop operation is required.

[0134] Local Read: Get data from the cache, and the status remains unchanged.

[0135] Local Write: Modify the data in the cache without changing the status.

[0136] Remote Read: This row of data is written to the memory, allowing other cores to use the latest data, and the status becomes S.

[0137] Remote Write: This row of data is written to the memory so that other cores can use the latest data. Since other cores will modify this row of data, the status becomes I.

[0138] Therefore, it can be found from the MESI state jump that the cache needs a large number of snoop operations in the I state, S state, and M state in order to achieve cache consistency. However, in specific fields or specific applications, many state flow jumps and snoop operations on cache consistency control are invalid, resulting in generally low overall processing efficiency of multi-core processors. Especially in the current RISC-V multi-core processors for parallel computing, each core runs a specific set of operations, and there is communication and data interaction between cores, but there are more and more application scenarios with low interaction frequency, and traditional MESI can no longer efficiently meet the needs of the above applications.

[0139] In summary, the optional embodiment of the present application proposes a design method for optimizing the performance of a multi-core RISC-V CPU. In view of the drawbacks of the traditional solution, the current RISC-V multi-core processor is used for parallel computing, and each core runs a set of specific operations, and there is communication and data interaction between cores, but the frequency of interaction is very low.

[0140] The optional embodiment of the present application first sets an instruction collection function, collects the unexecuted instructions in the L1 instruction Cache of each Core according to a preset collection width (equivalent to the first number), filters and analyzes the Load and Store instructions according to the instruction type, where Load corresponds to a read operation and Store corresponds to a write operation, and analyzes and predicts the scenarios in which the Load and Store instructions of each Core (equivalent to each processing core) are executed simultaneously within a predetermined time period, and then dynamically optimizes the L1L2 Cache cache consistency (MESI) state processing according to the prediction result to avoid invalid Snoop operations. At the same time, in order to avoid errors, a monitoring and correction function is also set to ensure timely correction when errors are predicted, ensure the normal execution of instruction functions, and greatly improve the performance of multi-core RISC-V CPUs in specific scenarios.

[0141] The optional embodiment of the present application first adds an Instruction_Process_Optimization module to the traditional solution, that is, an instruction processing optimization module, such as Figure 7 As shown. This module contains 5 sub-modules, namely Mode_Cfg (mode configuration module), Instruction_Collect (instruction collection module), Instruction_Analyse (instruction analysis module), Snoop_Adjust (Snoop adjustment module, i.e. sniffing operation adjustment module), and Monitor_Correct (monitoring correction module).

[0142] The following is a description of the five sub-modules included in the instruction processing optimization module.

[0143] 1. Mode_cfg, i.e., mode configuration module. Users can configure whether the module is to select normal mode or instruction optimization mode. If the configuration register Mode_cfg_mode=0, it means that the user selects normal mode. If the configuration register Mode_cfg_mode=1, it means that the user selects instruction optimization mode. It should be noted that the normal mode is to bypass the instruction processing optimization module; the instruction optimization mode is to enable the instruction processing optimization module. Therefore, the multi-core RISC-V CPU of the optional embodiment of the present application can be used in the normal mode or in the RISC-V multi-core processor for parallel computing. Each core runs a set of specific operations, and there is communication and data interaction between cores, but the frequency of interaction is very low.

[0144] 2. Instruction_Collect, instruction collection module, also accepts the collection width from the Mode_cfg module. The so-called collection width refers to the first number of instructions collected from multiple Core L1 instruction caches, and this width or number is determined by the user based on the specific applications running on each Core, such as 20 or 30, because different applications use Load or Store instructions (because only Load or Store instructions will Core read and write external L1 / L2 caches, where Load corresponds to read operations and Store corresponds to write operations) at different frequencies. In some applications, the interval between Load or Store instructions will be short, while in some applications, the interval between Load or Store instructions will be long. The so-called collection means that the module obtains the instructions that have not been executed from the instruction cache of each Core. The L1 Cache is divided into two categories, one for caching instructions, called instruction cache, and the other for caching data, called data cache. Therefore, this module has an AXIMaster interface to read the L1 instruction cache of each Core. It is worth noting that when this submodule obtains unexecuted instructions, it cannot start from the first unexecuted instruction, because the subsequent analysis and judgment takes time, so time must be reserved. Make sure that before the judgment result of the subsequent Snoop_Adjust (Snoop jump module) comes out, the first instruction read by this submodule has not been executed by each Core.

[0145] Therefore, the instruction collection module can dynamically adjust the number of collected instructions according to the different applications running on each Core, thereby enhancing the flexibility and practicality of the design.

[0146] 3. Instruction_Analyse, instruction analysis module, this module receives the instruction information passed by the previous instruction collection module Instruction_Collect, and parses the instructions to obtain the Load and Store instructions of each Core. Generally speaking, the load instruction copies the value of the effective address in the memory / peripheral to the rd register, and the store instruction copies the value in the rs2 register to the effective address in the memory / peripheral.

[0147] The instruction analysis module has the function of parsing RISC-V instructions. The parsing is done based on the Opcode of the instruction. Figure 4 shown.

[0148] It should be noted that Load instructions belong to Class I instructions, and Store instructions belong to Class S instructions;

[0149] Among them, for Category I instructions:

[0150] opcode is the operation code, 7 bits wide, in bits 0-6 of the instruction;

[0151] rd (Destination Register) is the destination register, 5 bits wide, located at bits 7-11 of the instruction;

[0152] Funct3 is the operation field. Funct3 occupies 3 bits, at bits 12-14 of the instruction;

[0153] rs1 (Source Register 1) is the first source operand register, which occupies 5 bits and is located at bits 15-19 of the instruction.

[0154] Stores the 12-bit immediate value - imm[11:0], at bits 20-31 of the instruction.

[0155] Among them, for S-type instructions:

[0156] opcode is the operation code, 7 bits wide, in bits 0-6 of the instruction;

[0157] imm[4:0]+imm[11:5];

[0158] Funct3 is the operation field. Funct3 occupies 3 bits, at bits 12-14 of the instruction;

[0159] rs1 (Source Register 1) is the first source operand register, which occupies 5 bits and is located at bits 15-19 of the instruction.

[0160] rs2 (Source Register 2) is the second source operand register, which occupies 5 bits and is located at bits 25-31 of the instruction.

[0161] Furthermore, RISC-C Load related instruction sets are as follows Figure 8 As shown, based on Figure 8 It can be seen that the Opcode of the I-type Load instruction is 7'b000011.

[0162] Furthermore, RISC-C Store related instruction sets such as Fig. 9 As shown, based on Fig. 9 It can be seen that the opcode code of the S-type Store instruction = 7'b0100011.

[0163] In addition to parsing out the Load / Store instruction type of each Core, the instruction analysis module also needs to parse out the corresponding effective address Load_addr / Store_addr in each Load / Store. The effective address of the instruction is obtained by adding the value in the rs1 register to the 12-bit immediate number (imm[11:0]) with sign bit extension (the immediate number in the store instruction is split into two parts, imm[4:0]+imm[11:5]). It is also necessary to parse out the position of each Core's Load / Store in the instruction queue. The position refers to the position of the current Load / Store instruction in the instruction queue read in the instruction collection module, and the position of the first instruction = 0.

[0164] The instruction analysis module can create an instruction information table of Load / Store instructions of multiple processing cores. The instruction information table can be shown in Table 1.

[0165] 4. Snoop_Adjust, the Snoop adjustment module, is a submodule that performs a comprehensive analysis based on the Load / Store instruction information table of each Core transmitted from the previous stage, and then makes a judgment, and adjusts the Snoop (i.e. determines the adjustment strategy) based on the judgment result. The principle of the analysis is to check the address correlation between the Load and Store instructions of multiple Cores.

[0166] The analysis method is:

[0167] Optionally, between each Core executing two Loads, other Cores may or may not perform Load or Store operations on the corresponding addresses. For example, when Core1 performs Load operations on Core1_Load_addr_1 and Core1_Load_addr_2, and Core0, Core2, and Core3 do not perform Load or Store operations on the Core1_Load_addr_1 and Core1_Load_addr_2 addresses, it is determined that the Read operation on Core1 does not require a Snoop operation, because during this period of time, other Cores will not read or write to the address, and only Core1 occupies the data on the Core1_Load_addr_1 and Core1_Load_addr_2 addresses.

[0168] Optionally, between each Core executing two Store operations, whether other Cores perform Load or Store operations on the corresponding addresses, for example, Core0 performs Store operations on Core0_Store_addr_2 and Core0_Store_addr_3 addresses, and Core1, Core2, and Core3 do not perform Load or Store operations on the Core0_Store_addr_2 and Core0_Store_addr_3 addresses, then the Write operation of Core0 is determined, and no snoop operation is required, because during this time period, other Cores will not read or write to the address, and only Core0 occupies the Core0_Store_addr_2 and Core0_Store_addr_3 addresses.

[0169] Optionally, between each Core executing Load and Store, whether there are other Cores performing Load or Store operations on the corresponding addresses, for example, Core2 performs Load operation on Core2_Load_addr_0 address and Store operation on Core2_Store_addr_1 address, and Core0, Core1, and Core3 do not perform Load or Store operations on the Core2_Load_addr_0 address and Core2_Store_addr_1 address, then the Read operation and Write operation of Core2 are determined, and no snoop operation is required, because during this time period, other Cores will not read or write to the address, and only Core2 occupies the Core2_Load_addr_0 and Core2_Store_addr_1 addresses.

[0170] Optionally, between each Core executing Store and Load, whether there are other Cores performing Store or Load operations on the corresponding addresses, for example, Core3 performs Store operation on Core3_Store_addr_1 address and Load operation on Core3_Load_addr_1 address, and Core0, Core1, and Core2 do not perform Store or Load operation on the Core3_Store_addr_1 address and Core3_Load_addr_1 address, then the Write operation and Read operation of Core3 are determined, and no snoop operation is required, because during this time period, other Cores will not read or write to the address, and only Core3 occupies the Core3_Store_addr_1 and Core3_Load_addr_1 addresses.

[0171] It should be noted that the judgment basis of the "between ***" described above is based on the position in the instruction queue read from the Load or Store instruction collection module of each Core, for example, Core0_Load_instr_position_0, Core2_Store_instr_position_2, etc.

[0172] Exemplarily, the position of the Load instruction of Core0 is Core0_Load_instr_position_0=3; the position of the Store instruction of Core0 is Core0_Store_instr_position_0=10.

[0173] If the position of the Load instruction of Core1 is Core1_Load_instr_position_0=5, it is determined that the Load instruction of Core1 is between the Load and Store instructions of Core0.

[0174] If the position of the Load instruction of Core1 is Core1_Load_instr_position_0=11, it is determined that the Load instruction of Core1 is not between the Load and Store instructions of Core0.

[0175] 5: Monitor_Correct, which is the monitoring and correction function. The function of this module ensures timely correction when the prediction error occurs, and ensures the normal execution of the instruction function. This is mainly because of the "branch instruction". If the prediction result of the branch instruction is found to be wrong during execution, the instruction to be executed by the Core next will not be the next instruction in the instruction cache, and it needs to be reloaded. Therefore, for this scenario, the instruction collection module needs to re-acquire the unexecuted instructions

[0176] In summary, the optional embodiment of the present application optimizes the hardware implementation of the cache consistency protocol by adding a new hardware design (i.e., adding an instruction processing optimization module). The new hardware design implements the instruction collection function, which can collect the unexecuted instructions in the L1 instruction cache of each Core according to the preset collection width, filter and analyze the Load and Store instructions according to the instruction type, and analyze and predict the scenarios in which each Core Load and Store instruction is executed at the same time within a predetermined time period, and then dynamically implement and optimize the L1 L2 Cache cache consistency (MESI) state processing according to the prediction results to avoid invalid Snoop operations. At the same time, in order to avoid errors, a monitoring and correction function is also set to ensure timely correction of errors in the prediction of branch instructions, thereby ensuring the normal execution of instruction functions, greatly improving the performance of multi-core RISC-VCPU in specific scenarios, and greatly optimizing the cache consistency protocol processing rate.

[0177] In the present embodiment, a device for determining an adjustment strategy is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made are not repeated here. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0178] Fig.10 is a structural block diagram of a device for determining an adjustment strategy according to an embodiment of the present application, such as Fig.10 As shown, the device comprises:

[0179] A first determining module 1002 is used to determine instruction queues corresponding to multiple processing cores of the target device, wherein the instruction queues include: first instructions issued by each processing core and not currently executed;

[0180] A second determining module 1004 is used to determine an instruction information table corresponding to a plurality of the instruction queues, wherein the instruction information table includes at least: an effective address of a second instruction of a target type in the first instruction, and a position of the second instruction in the instruction queue to which it belongs;

[0181] The third determination module 1006 is used to determine the adjustment strategy of the sniffing operation on each processing core according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, wherein the sniffing operation is used to indicate the operation allowed to be performed on other processing cores by each processing core between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores other than each processing core among the multiple processing cores.

[0182] Through the above-mentioned device, the instruction queues corresponding to the multiple processing cores of the target device are determined, wherein the instruction queues include: the first instruction issued by each processing core and not currently executed; the instruction information tables corresponding to the multiple instruction queues are determined, wherein the instruction information table at least includes: the effective address of the second instruction belonging to the target type in the first instruction, and the position of the second instruction in the instruction queue to which it belongs; according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue, and the positions corresponding to any two adjacent second instructions, the adjustment strategy of the sniffing operation of each processing core is determined, wherein the sniffing operation is used to indicate that each processing core is allowed to perform operations on other processing cores between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores other than each processing core in the multiple processing cores. Therefore, the problem that the cache consistency control protocol adopted by the RISC-V multi-core processor is fixed in the prior art, resulting in many invalid snoop operations in the cache consistency control process of the RISC-V multi-core processor, thereby resulting in low processing efficiency of the RISC-V multi-core processor can be solved. Improved the processing efficiency of RISC-V multi-core processors.

[0183] In an exemplary embodiment, the first determination module 1002 is used to: determine the first-level cache corresponding to each processing core, wherein the first-level cache stores the first instruction corresponding to each processing core; obtain the first instruction from the first-level cache to obtain the instruction queue, wherein the first-level cache is a cache directly connected to each processing core.

[0184] In an exemplary embodiment, the first determination module 1002 is used to: determine a first number of the first instructions allowed to be obtained from the first-level cache, wherein the first number is determined by a second number of applications running on each processing core; obtain a first number of the first instructions from the first-level cache, and store the first number of the first instructions in sequence in a preset queue corresponding to each processing core to obtain the instruction queue.

[0185] In an exemplary embodiment, the first determination module 1002 is used to: determine a preset execution order of W first instructions included in the first level cache, where W is a positive integer; and determine the instruction queue according to the preset execution order.

[0186] In an exemplary embodiment, the first determination module 1002 is used to: determine the third instruction among the W first instructions through the preset execution order, wherein the third instruction is the Nth instruction among the W first instructions, and N is an integer greater than 1; and determine the instruction queue corresponding to each processing core through the third instruction.

[0187] In an exemplary embodiment, the first determination module 1002 is used for: an acquisition step: acquiring the third instruction into a preset queue corresponding to each processing core; an update step: when it is determined that the third instruction is not a branch instruction, determining the fourth instruction to be executed after the third instruction by the preset execution order, and updating the fourth instruction to the third instruction; when it is determined that the third instruction is a branch instruction, predicting the execution result of the third instruction to obtain a prediction result; updating the fifth instruction indicated by the prediction result in W first instructions to the third instruction; looping M times the acquisition step and the update step to obtain the instruction queue, wherein M is used to represent the first number of the first instructions allowed to be obtained from the first-level cache.

[0188] In an exemplary embodiment, the second determining module 1004 is used to: parse the first instructions included in the plurality of instruction queues to obtain parsing results; and determine the instruction information table according to the parsing results.

[0189] In an exemplary embodiment, the second determination module 1004 is used to: parse the first instruction according to the instruction architecture of the target type of instruction to obtain the instruction type of the first instruction and the effective address of the first instruction, wherein the target type includes the instruction type; and determine the position of the first instruction in the instruction queue to which the first instruction belongs; and determine the instruction type, the effective address, and the position of the first instruction in the instruction queue to which the first instruction belongs as the parsing result.

[0190] In an exemplary embodiment, the second determination module 1004 is used to: parse the first instruction according to the instruction architecture to obtain the operation code of the first instruction; when the operation code is a first value, determine that the instruction type of the first instruction is a first type; when the operation code is a second value, determine that the instruction type of the first instruction is a second type.

[0191] In an exemplary embodiment, the second determination module 1004 is used to: parse the first instruction according to the instruction architecture, obtain the index of the first source register recorded in the first instruction, and obtain a sign-bit extended K-bit immediate number of the first instruction, where K is a positive integer; and determine the sum of the index and the K-bit immediate number as the effective address.

[0192] In an exemplary embodiment, the second determination module 1004 is used to: determine the filling position in the instruction information table according to the instruction type and the target processing core to which the first instruction belongs, wherein the multiple processing cores include: the target processing core; fill the effective address and the position of the first instruction in the instruction queue to which the first instruction belongs into the filling position to obtain the instruction information table.

[0193] In an exemplary embodiment, the third determination module 1006 is used to: determine the sixth instruction and the seventh instruction among any two adjacent second instructions through the instruction information table; determine the first effective address and the first position corresponding to the sixth instruction, and determine the second effective address and the second position corresponding to the seventh instruction; determine the eighth instruction of the other processing cores, wherein the third position of the eighth instruction is between the first position and the second position; and determine the adjustment strategy through the eighth instruction, the first effective address, and the second effective address.

[0194] In an exemplary embodiment, the third determination module 1006 is used to: determine the query position corresponding to the target processing core corresponding to the instruction queue in the instruction information table, wherein the multiple processing cores include: the target processing core; the query position includes: a fill position; the fill position is determined by the instruction type of the first instruction in the target type, and the target processing core to which the first instruction belongs; obtain the sixth instruction and the seventh instruction from the query position.

[0195] In an exemplary embodiment, the third determining module 1006 is configured to: traverse the remaining positions in the instruction information table except the query position; and determine the eighth instruction from the remaining positions.

[0196] In an exemplary embodiment, the third determination module 1006 is used to: obtain all instructions in other instruction queues whose positions are between the first position and the second position, wherein the other instruction queues are other instruction queues in the multiple instruction queues except the instruction queue; and determine the instruction belonging to the target type among all the instructions as the eighth instruction.

[0197] In an exemplary embodiment, the third determination module 1006 is used to: determine the third effective address of the eighth instruction through the instruction information table; determine whether the third effective address is consistent with the fourth effective address, wherein the fourth effective address includes at least one of the following: the first effective address, the second effective address; when the third effective address and the fourth effective address are consistent, determine that the adjustment strategy is to allow each processing core to perform the sniffing operation on the other processing cores.

[0198] In an exemplary embodiment, the third determining module 1006 is used to: when the third effective address and the fourth effective address are inconsistent, determine that the adjustment strategy is to prohibit each processing core from performing the sniffing operation on the other processing cores.

[0199] In an exemplary embodiment, after determining the adjustment strategy for the sniffing operation of each processing core based on the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, the device also includes: a fourth determination module, used to: determine whether there is a branch instruction in any two adjacent second instructions when each processing core executes the any two adjacent second instructions; determine the execution result of the branch instruction when there is a branch instruction in any two adjacent second instructions; and determine the execution method of the adjustment strategy through the execution result.

[0200] In an exemplary embodiment, the fourth determination module is used to: determine a ninth instruction and a tenth instruction, wherein the ninth instruction is the first instruction of any two adjacent second instructions, and the tenth instruction is the second instruction of any two adjacent second instructions; when the ninth instruction is a branch instruction, determine whether the tenth instruction is the eleventh instruction indicated by the execution result, or an instruction allowed to be executed after the eleventh instruction; when the tenth instruction is the eleventh instruction or an instruction allowed to be executed after the eleventh instruction, determine that the adjustment policy is allowed to be executed.

[0201] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0202] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0203] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0204] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0205] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0206] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0207] An embodiment of the present application also provides a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0208] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0209] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0210] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for determining an adjustment strategy, characterized in that: include: Determine instruction queues corresponding to the multiple processing cores of the target device, wherein the instruction queues include: first instructions issued by each processing core and not currently executed; Determine an instruction information table corresponding to a plurality of the instruction queues, wherein the instruction information table includes at least: an effective address of a second instruction of a target type in the first instruction, and a position of the second instruction in the instruction queue to which it belongs; An adjustment strategy for the sniffing operation of each processing core is determined according to the effective addresses respectively corresponding to any two adjacent second instructions in the instruction queue and the positions respectively corresponding to the any two adjacent second instructions, wherein the sniffing operation is used to indicate that each processing core is allowed to perform operations on other processing cores between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores other than each processing core among the multiple processing cores, wherein, Determining an adjustment strategy for the sniffing operation of each processing core according to the effective addresses respectively corresponding to any two adjacent second instructions in the instruction queue and the positions respectively corresponding to the any two adjacent second instructions, including: determining the sixth instruction and the seventh instruction in the any two adjacent second instructions through the instruction information table; determining the first effective address and the first position corresponding to the sixth instruction, and determining the second effective address and the second position corresponding to the seventh instruction; determining the eighth instruction of the other processing cores, wherein the third position of the eighth instruction is between the first position and the second position; determining the adjustment strategy through the eighth instruction, the first effective address, and the second effective address, wherein, Determining the sixth instruction and the seventh instruction in any two adjacent second instructions through the instruction information table includes: determining the query position corresponding to the target processing core corresponding to the instruction queue in the instruction information table, wherein the multiple processing cores include: the target processing core; the query position includes: a filling position; the filling position is determined by the instruction type of the first instruction in the target type and the target processing core to which the first instruction belongs; obtaining the sixth instruction and the seventh instruction from the query position, wherein, The adjustment strategy is determined by the eighth instruction, the first effective address, and the second effective address, including: determining the third effective address of the eighth instruction through the instruction information table; determining whether the third effective address is consistent with the fourth effective address, wherein the fourth effective address includes at least one of the following: the first effective address, the second effective address; when the third effective address is consistent with the fourth effective address, determining the adjustment strategy to allow each processing core to perform the sniffing operation on the other processing cores, wherein determining the eighth instruction of the other processing cores includes: traversing the remaining positions in the instruction information table except the query position; and determining the eighth instruction from the remaining positions.

2. The method according to claim 1, characterized in that Determine the instruction queues corresponding to the multiple processing cores of the target device, including: Determine a first-level cache corresponding to each processing core, wherein the first-level cache stores the first instruction corresponding to each processing core; The first instruction is obtained from the first-level cache to obtain the instruction queue, wherein the first-level cache is a cache directly connected to each processing core.

3. The method according to claim 2, characterized in that Acquiring the first instruction from the first-level cache to obtain the instruction queue includes: Determining a first number of the first instructions allowed to be obtained from the first level cache, wherein the first number is determined by a second number of applications running on each processing core; A first number of the first instructions are obtained from the first-level cache, and the first number of the first instructions are sequentially stored in a preset queue corresponding to each processing core to obtain the instruction queue.

4. The method according to claim 2, characterized in that: Acquiring the first instruction from the first-level cache to obtain the instruction queue includes: Determine a preset execution order of W first instructions included in the first level cache, where W is a positive integer; The instruction queue is determined by the preset execution order.

5. The method according to claim 4, characterized in that Determining the instruction queue by the preset execution order includes: Determine a third instruction among the W first instructions by using the preset execution order, wherein the third instruction is the Nth instruction among the W first instructions, and N is an integer greater than 1; The instruction queue corresponding to each processing core is determined by the third instruction.

6. The method according to claim 5, characterized in that Determining the instruction queue corresponding to each processing core by using the third instruction includes: Acquisition step: acquiring the third instruction into a preset queue corresponding to each processing core; Updating step: when it is determined that the third instruction is not a branch instruction, determining a fourth instruction to be executed after the third instruction by the preset execution order, and updating the fourth instruction to the third instruction; when it is determined that the third instruction is a branch instruction, predicting the execution result of the third instruction to obtain a prediction result; updating a fifth instruction indicated by the prediction result in W first instructions to the third instruction; The acquisition step and the update step are executed in a loop M times to obtain the instruction queue, wherein M is used to represent a first number of the first instructions allowed to be obtained from the first-level cache.

7. The method according to claim 1, characterized in that Determining the instruction information tables corresponding to the plurality of instruction queues comprises: Parsing the first instructions included in the plurality of instruction queues to obtain parsing results; The instruction information table is determined according to the analysis result.

8. The method according to claim 7, characterized in that Parsing the first instructions included in the plurality of instruction queues to obtain parsing results includes: Parsing the first instruction according to an instruction architecture of an instruction of a target type to obtain an instruction type of the first instruction and the effective address of the first instruction, wherein the target type includes the instruction type; and, determining a position of the first instruction in an instruction queue to which the first instruction belongs; The instruction type, the effective address, and the position of the first instruction in the instruction queue to which the first instruction belongs are determined as the parsing result.

9. The method according to claim 8, characterized in that Parsing the first instruction according to the instruction architecture of the target type of instruction to obtain the instruction type of the first instruction includes: Parsing the first instruction according to the instruction architecture to obtain an operation code of the first instruction; In a case where the opcode is a first value, determining that the instruction type of the first instruction is a first type; In a case where the operation code is a second value, it is determined that the instruction type of the first instruction is a second type.

10. The method according to claim 8, characterized in that Parsing the first instruction according to the instruction architecture of the target type of instruction to obtain the effective address of the first instruction includes: Parsing the first instruction according to the instruction architecture to obtain an index of a first source register recorded in the first instruction and a K-bit sign-bit extended immediate value of the first instruction, wherein K is a positive integer; The sum of the index and the K-bit immediate value is determined as the effective address.

11. The method according to claim 8, characterized in that Determining the instruction information table according to the parsing result includes: Determine a filling position in the instruction information table according to the instruction type and a target processing core to which the first instruction belongs, wherein the plurality of processing cores include: the target processing core; The effective address and the position of the first instruction in the instruction queue to which the first instruction belongs are filled into the filling position to obtain the instruction information table.

12. The method according to claim 1, characterized in that After determining whether the third effective address is consistent with the fourth effective address, the method further includes: In a case where the third effective address and the fourth effective address are inconsistent, determining the adjustment strategy is to prohibit each processing core from performing the sniffing operation on the other processing cores.

13. The method according to claim 1, characterized in that After determining the adjustment strategy for the sniffing operation of each processing core according to the effective addresses respectively corresponding to any two adjacent second instructions in the instruction queue and the positions respectively corresponding to the any two adjacent second instructions, the method further includes: In the case where each processing core executes the any two adjacent second instructions, determining whether there is a branch instruction in the any two adjacent second instructions; In the case where a branch instruction exists between any two adjacent second instructions, determining an execution result of the branch instruction; The execution method of the adjustment strategy is determined according to the execution result.

14. The method according to claim 13, characterized in that Determining the execution method of the adjustment strategy according to the execution result includes: Determine a ninth instruction and a tenth instruction, wherein the ninth instruction is the first instruction of the any two adjacent second instructions, and the tenth instruction is the second instruction of the any two adjacent second instructions; In the case where the ninth instruction is a branch instruction, determining whether the tenth instruction is the eleventh instruction indicated by the execution result, or an instruction allowed to be executed after the eleventh instruction; In a case where the tenth instruction is the eleventh instruction or an instruction that is allowed to be executed after the eleventh instruction, it is determined that the execution of the adjustment policy is allowed.

15. A device for determining an adjustment strategy, characterized in that: include: A first determining module is used to determine instruction queues corresponding to the multiple processing cores of the target device, wherein the instruction queues include: first instructions issued by each processing core and not currently executed; A second determining module is used to determine an instruction information table corresponding to a plurality of the instruction queues, wherein the instruction information table includes at least: an effective address of a second instruction of a target type in the first instruction, and a position of the second instruction in the instruction queue to which it belongs; The third determination module is used to determine the adjustment strategy of the sniffing operation on each processing core according to the effective addresses corresponding to any two adjacent second instructions in the instruction queue and the positions corresponding to the any two adjacent second instructions, wherein the sniffing operation is used to indicate the operation allowed to be performed on other processing cores by each processing core between the any two adjacent second instructions, so that each processing core maintains cache consistency with the other processing cores, and the other processing cores are processing cores other than each processing core among the multiple processing cores, wherein, The third determination module is further used to: determine the sixth instruction and the seventh instruction of the any two adjacent second instructions through the instruction information table; determine the first effective address and the first position corresponding to the sixth instruction, and determine the second effective address and the second position corresponding to the seventh instruction; determine the eighth instruction of the other processing core, wherein the third position of the eighth instruction is between the first position and the second position; determine the adjustment strategy through the eighth instruction, the first effective address, and the second effective address, wherein, The third determination module is further used to: determine the query position corresponding to the target processing core corresponding to the instruction queue in the instruction information table, wherein the multiple processing cores include: the target processing core; the query position includes: a filling position; the filling position is determined by the instruction type of the first instruction in the target type and the target processing core to which the first instruction belongs; obtain the sixth instruction and the seventh instruction from the query position, wherein, The third determination module is further used to: determine the third effective address of the eighth instruction through the instruction information table; determine whether the third effective address is consistent with the fourth effective address, wherein the fourth effective address includes at least one of the following: the first effective address, the second effective address; when the third effective address and the fourth effective address are consistent, determine the adjustment strategy to allow each processing core to perform the sniffing operation on the other processing cores, wherein the third determination module is further used to traverse the remaining positions in the instruction information table except the query position; and determine the eighth instruction from the remaining positions.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 14 when executed by a processor.

17. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 14 are implemented.

18. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 14 are implemented.

Images