A low-cost and high-performance radio frequency amplifier

Abstract

This application discloses a low-cost and high-performance radio frequency amplifier, which includes an input stage circuit, a common-gate stage circuit, and an output load circuit. The input stage circuit realizes the conversion from a single-ended signal to a differential signal, realizes input impedance matching, and simultaneously converts the input radio frequency voltage signal into a radio frequency current signal. The input stage circuit includes a three-coil transformer 1, which is composed of a main coil, a secondary coil, and a third coil. The common-gate stage circuit transmits the radio frequency current signal output by the input stage circuit to the output load circuit, simultaneously improves the voltage withstand and equivalent output impedance of the circuit, and realizes gain control in at least two modes. The output load circuit converts the radio frequency current signal from the common-gate stage circuit into a radio frequency voltage signal, realizes the conversion from a differential signal to a single-ended signal, and outputs the amplified radio frequency voltage signal. This application provides a radio frequency amplifier with small size, broadband matching, high linearity, large dynamic range, and low design complexity.

Description

Technical Field

[0001] The present application relates to a wireless communication technology, and in particular to a radio frequency amplifier. Background Art

[0002] Please refer to Figure 1 , which is an existing radio frequency amplifier with single-ended to differential conversion and input matching functions. The radio frequency amplifier sequentially includes an input stage circuit and an output load circuit from bottom to top. The input stage circuit includes a transformer Tr1, gate inductors Lg1 and Lg2, a source degeneration inductor Ls, additional capacitors C1 and C2, a differential NMOS pair M1 and M2, and gate bias resistors R1 and R2. The output load stage circuit includes a programmable array capacitor C3, a transformer Tr2, and a load resistor R L . The entire radio frequency amplifier presents a left-right symmetric structure, and the symmetric devices have exactly the same parameters. The transformer Tr1 is used to convert a single-ended signal (input voltage vin) into a differential signal. The combination of all the capacitors and inductors in the input stage circuit matches the input impedance to the value required by the design (usually 50 ohms), and converts the voltage input signal into a current signal through the differential NMOS pair M1 and M2. The transformer Tr2 is used to convert the differential signal into a single-ended signal (output voltage vout). The gain of the entire radio frequency amplifier is greater than 1, so the input signal is amplified and then output.

[0003] Figure 1 The existing radio frequency amplifier shown has the following defects.

[0004] First, the input stage circuit uses a source degeneration common-source structure for impedance matching. Inductors Lg1 and Lg2 are added to the gates of the NMOS pair M1 and M2 respectively, and together with the source degeneration inductor Ls, there are a total of 3 inductors, resulting in too large a layout area, and it is not easy to layout and wire the layout, and the design cost is high.

[0005] Second, the input stage circuit realizes input matching based on the resonance of capacitors and inductors. Among them, Zin is the input impedance, s is the complex frequency, Ls is the inductance value of the source degeneration inductor, Lg is the inductance value of the gate inductor Lg1 of the NMOS transistor M1 (or the inductance value of the gate inductor Lg2 of the NMOS transistor M2, which are the same), C1 is the capacitance value of the capacitor connected across the gate and source of the NMOS transistor M1 (or the capacitance value of the capacitor C2 connected across the gate and source of the NMOS transistor M2, which are the same), and gm is the transconductance of the common-source NMOS pair transistors M1 or M2 (which are the same). When Ls + Lg and C1 resonate, the input impedance Zin only has a real part, which is the value required for the design (usually designed to be 50 ohms). From the above analysis, it can be found that this input matching can only be narrowband, that is, the bandwidth is limited and it can only be used in narrowband communication systems.

[0006] Take Figure 1 as an example. It can be seen that inductors, which are large-area devices, are usually used in RF amplifiers in RF transceivers, and it is easy to increase the manufacturing cost. At the same time, the design difficulties of RF amplifiers are good input matching and linearity, as well as having a certain dynamic range. Therefore, designing a small-size and high-performance RF amplifier circuit will simplify the design of RF circuits and reduce the manufacturing cost. Summary of the Invention

[0007] The technical problem to be solved by this application is how to make the RF amplifier have the characteristics of small size, broadband input matching, high linearity, and a certain dynamic range at the same time.

[0008] To solve the above technical problem, this application proposes a low-cost and high-performance RF amplifier, which includes an input stage circuit, a common-gate stage circuit, and an output load circuit. The input stage circuit realizes the conversion from a single-ended signal to a differential signal, realizes input impedance matching, and at the same time converts the input RF voltage signal into an RF current signal; the input stage circuit includes a three-coil transformer and a common-source transistor, and the three-coil transformer consists of a primary coil, a secondary coil, and a third coil; the coupling inductance between the primary coil and the secondary coil is equivalent to the gate inductance of the common-source transistor; the third coil is equivalent to the first part of the source degeneration inductor of the common-source transistor, and the coupling inductance between the primary coil and the third coil is equivalent to the second part of the source degeneration inductor of the common-source transistor, and the sum of these two parts is equivalent to the source degeneration inductor of the common-source transistor. The common-gate stage circuit transmits the RF current signal output by the input stage circuit to the output load circuit, improves the voltage withstand and equivalent output impedance of the circuit at the same time, and realizes gain control in at least two modes. The output load circuit converts the RF current signal from the common-gate stage circuit into an RF voltage signal, realizes the conversion from a differential signal to a single-ended signal, and outputs the amplified RF voltage signal.

[0009] Furthermore, the entire RF amplifier exhibits a left-right symmetric structure, and the symmetric devices have exactly the same parameters.

[0010] Furthermore, in the triple-coil transformer 1, the primary coil is two large loops, the secondary coil is also two large loops, and the secondary coil is stacked above and below the primary coil; the third coil is two small loops and is surrounded by the large loops of the primary coil and the secondary coil; the center tap of the secondary coil corresponds to the center tap of the third coil vertically, is connected and grounded.

[0011] Furthermore, the input stage circuit further includes a programmable capacitor array C1, two DC-blocking capacitors C2, C3, a differential NMOS pair M1, M2, and two bias resistors R1, R2; the differential NMOS pair M1, M2 serves as a common-source transistor. In the triple-coil transformer 1, one end of the primary coil is connected to the input voltage and the other end is grounded; the secondary coil is connected in parallel with the programmable capacitor array C1, and the two ends of the secondary coil are also respectively connected to the gates of the differential NMOS pair M1, M2 through two DC-blocking capacitors C2, C3; the conversion from a single-ended signal to a differential signal is achieved between the primary coil and the secondary coil; the two ends of the third coil are respectively connected to the sources of the differential NMOS pair M1, M2. The gates of the differential NMOS pair M1, M2 are also respectively connected to a gate bias voltage 1 through two bias resistors R1, R2; the drains of the differential NMOS pair M1, M2 output a differential current signal to the common-gate stage circuit; the differential NMOS pair M1, M2 realizes the conversion from a voltage signal to a current signal. The input stage circuit achieves input impedance matching based on the resonance of all capacitors and all equivalently derived inductors.

[0012] Further, the common-gate stage circuit includes NMOS transistors M3 to M8, gate decoupling capacitors Cg1, Cg2, bias resistors R3, R4. The drain of NMOS transistor M1 is connected to the sources of NMOS transistor M3, NMOS transistor M4, and NMOS transistor M5 simultaneously; the drain of NMOS transistor M2 is connected to the sources of NMOS transistor M6, NMOS transistor M7, and NMOS transistor M8 simultaneously; the gates of NMOS transistor M3 and NMOS transistor M8 are connected to gate bias voltage two through two bias resistors R3, R4 respectively; the gates of NMOS transistor M3 and NMOS transistor M8 are also grounded through two gate decoupling capacitors Cg1, Cg2 respectively; the drains of NMOS transistor M3 and NMOS transistor M4 are connected and then connected to the output load circuit; the drains of NMOS transistor M8 and NMOS transistor M7 are connected and then connected to the output load circuit; the gates of NMOS transistor M4 and NMOS transistor M7 are both connected to the gain control signal; the gain control signal is connected to an inverter and then outputs an inverted gain control signal; the gates of NMOS transistor M5 and NMOS transistor M6 are both connected to the inverted gain control signal; the drains of NMOS transistor M5 and NMOS transistor M6 are both connected to the power supply voltage.

[0013] Further, when the gain control signal is at a high level and the inverted gain control signal is at a low level, NMOS transistors M3, M4, M7, and M8 are turned on, and NMOS transistors M5 and M6 are turned off, and the common-gate stage circuit operates in a high-gain mode. When the gain control signal is at a low level and the inverted gain control signal is at a high level, NMOS transistors M4 and M7 are turned off, and NMOS transistors M3, M5, M6, and M8 are turned on, and part of the current flows to the power supply voltage through NMOS transistors M5 and M6, and the current flowing to the output load circuit becomes smaller, and the common-gate stage circuit operates in a low-gain mode. In the above two gain modes, the current flowing through the differential NMOS pair transistors M1, M2 in the input stage circuit remains unchanged, that is, the transconductance of the differential NMOS pair transistors M1, M2 remains unchanged; the above two gain modes expand the dynamic range of the RF amplifier.

[0014] Further, the common-source transistor in the input stage circuit is stacked with the common-gate stage circuit to form a cascode structure; the common-gate transistor in the cascode structure divides a part of the voltage, so that the voltage across the common-source transistor becomes smaller.

[0015] Further, the common-gate stage circuit is connected in series with the input stage circuit, so that the equivalent output impedance seen from the drain end of the common-gate transistor to the ground increases.

[0016] Further, the common-gate stage circuit includes ten NMOS transistors M3, M4, M41, M5, M51, M6, M61, M7, M71, M8, two inverters B1, B2, two gain control signals GainCtrl1, GainCtrl2, and two inverted gain control signals ENB1, ENB2. When both of the two gain control signals GainCtrl1 and GainCtrl2 are at high level, the NMOS transistors M4, M41, M7, and M71 are turned on, and the NMOS transistors M5, M51, M6, and M61 are turned off, and the common-gate stage circuit operates in the maximum gain mode. When both of the two gain control signals GainCtrl1 and GainCtrl2 are at low level, the common-gate stage circuit operates in the minimum gain mode. When the two gain control signals GainCtrl1 and GainCtrl2 are at one high and one low level or one low and one high level, the common-gate stage circuit operates in two intermediate gain modes. The above four gain modes expand the dynamic range of the RF amplifier.

[0017] Further, the output load circuit includes transformer two, a programmable capacitor array C4, and a load resistor. The primary coil of transformer two is connected in parallel with the programmable capacitor array C4 to cover different frequency bands by adjusting the programmable capacitor array C4; the center tap of the primary coil of transformer two is connected to the power supply voltage; the secondary coil of transformer two is connected in parallel with the load resistor; one end of the load resistor serves as the output voltage, and the other end of the load resistor is grounded. The RF current signal output by the common-gate stage circuit is transmitted to the resonant frequency selection network composed of transformer two and the programmable capacitor array C4. Transformer two not only realizes the conversion from differential signal to single-ended signal, but also transfers the power to the load resistor through the impedance transformation ratio of transformer two to realize signal amplification and output, and the load resistor converts the RF current signal into an RF voltage signal.

[0018] The technical effects achieved by this application are as follows: (1) The gate inductors Lg1 and Lg2 and the source degeneration inductor Ls of the common-source transistors are omitted in the input stage circuit, so the size of the entire RF amplifier is reduced, the complexity of the layout design is reduced, and the manufacturing cost is reduced. (2) Through the layout optimization of the three-coil transformer one, broadband input impedance matching is achieved. (3) The source degeneration inductor Ls of the common-source transistor is equivalent by the three-coil transformer one, and the advantage of high linearity is retained. (4) At least two gain control modes are designed in the common-gate stage circuit to achieve a large dynamic range. Description of the Drawings

[0019] Figure 1 is a schematic circuit structure diagram of an existing RF amplifier.

[0020] Figure 2 is a schematic circuit structure diagram of the low-cost and high-performance RF amplifier proposed by this application.

[0021] Figure 3 is Figure 2 The structural schematic diagram of the three - coil transformer Tr1 in the middle.

[0022] Figure 4 is Figure 2 The layout design schematic diagram of the three - coil transformer Tr1 in the middle.

[0023] Figure 5 is Figure 4 The layout design schematic diagram of the main coil L1 in the middle.

[0024] Figure 6 is Figure 4 The layout design schematic diagram of the secondary coil L2 in the middle.

[0025] Figure 7 is Figure 4 The layout design schematic diagram of the third coil L3 in the middle.

[0026] Figure 8 is the schematic diagram of the input matching of the RF amplifier proposed in this application.

[0027] Figure 9 is the schematic diagram of the common - gate - stage circuit that realizes four gain modes through 2 - bit control bits.

[0028] Explanation of the reference numerals in the figure: vin is the input voltage, vout is the output voltage, Tr1 and Tr2 are transformers, L1 to L3 are coils, Lg1 and Lg2 are gate inductors, Ls is the source - degeneration inductor, C1 and C2 are gate - source bridging capacitors, M1 to M8, M41, M51, M61, M71 are NMOS transistors, R1 to R4 are bias resistors, VBgm and VBcas are gate - bias voltages, Cg1 and Cg2 are gate - terminal decoupling capacitors, C1 to C4 are capacitors, VDD is the power - supply voltage, R L is the load resistor, kg and ks are coupling coefficients, p1p and p1n are the two ends of the main coil, p2p and p2n are the two ends of the secondary coil, p3p and p3n are the two ends of the third coil, GainCtrl, GainCtrl1, GainCtrl2 are gain - control signals, B1 and B2 are inverters, ENB, ENB1, ENB2 are inverting gain - control signals. Detailed implementation manners

[0029] Please refer to Figure 2, the low-cost and high-performance RF amplifier proposed in this application includes an input-stage circuit, a common-gate stage circuit, and an output load circuit. The input-stage circuit realizes the conversion from a single-ended signal to a differential signal, matches the input impedance to the designed required value - for example, 50 ohms, and converts the voltage signal into a current signal. The common-gate stage circuit transmits the RF current signal output by the input-stage circuit to the output load circuit, which is used to improve the reliability of the circuit and prevent the circuit from being broken down. The common-gate stage circuit also increases the equivalent output impedance of the circuit, enabling the circuit to have better reverse isolation. The common-gate stage circuit also realizes the gain control in different modes. The output load circuit converts the RF current signal from the common-gate stage circuit into an RF voltage signal, forms a resonant frequency selection network through the transformer Tr2 and the programmable capacitor array C4, and transfers the power of the primary coil of the transformer Tr2 to the load resistor R of the secondary coil through the appropriate impedance ratio of the transformer Tr2 L to achieve high-power signal output. The gain of the RF amplifier is equal to the product of the equivalent transconductance of the input-stage circuit and the resistance value of the load resistor R L , and this product value is greater than 1, that is, the amplification of the input signal is achieved. The entire RF amplifier presents a left-right symmetric structure, and the symmetric devices have exactly the same parameters.

[0030] Figure 2 The input-stage circuit in includes a three-coil transformer Tr1, a programmable capacitor array C1, DC-blocking capacitors C2 and C3, a differential NMOS pair M1 and M2 (as common-source transistors), and bias resistors R1 and R2. The three-coil transformer Tr1 consists of a primary coil L1, a secondary coil L2, and a third coil L3. One end of the primary coil L1 is connected to the input voltage vin, and the other end is grounded. The secondary coil L2 is connected in parallel with the programmable capacitor array C1, and the programmable capacitor array C1 is used to further increase the flexibility and range of input matching. The two ends of the secondary coil L2 are also respectively connected to the gates of the differential NMOS pair M1 and M2 through the DC-blocking capacitors C2 and C3. The conversion from a single-ended signal (input voltage vin) to a differential signal is realized between the primary coil L1 and the secondary coil L2. The two ends of the third coil L3 are respectively connected to the sources of the NMOS pair M1 and M2. The gates of the differential NMOS pair M1 and M2 are also respectively connected to the gate bias voltage -VBgm through the bias resistors R1 and R2. The drains of the differential NMOS pair M1 and M2 output a differential current signal to the common-gate stage circuit. The differential NMOS pair M1 and M2 realizes the conversion from a voltage signal to a current signal.

[0031] Please refer to Figure 3, in the three - coil transformer Tr1, the coupling coefficient between the primary coil L1 and the secondary coil L2 is kg. The coupling coefficient between the primary coil L1 and the third coil L3 is ks. The center tap of the secondary coil L2 is connected to the center tap of the third coil L3 and grounded.

[0032] Please refer to Figures 4 to 7 , which is an exemplary layout design of the three - coil transformer Tr1. Here, blue represents the top - layer metal, red represents the second (sub - top) layer metal, green represents the third (third - top) layer metal, and the white small squares represent via metals. The primary coil L1 is mainly two large loops. One end P1p is connected to the input voltage vin, and the other end P1n is grounded. The primary coil L1 is mainly implemented in the second - layer metal, and individual parts are realized by vias across to the third - layer metal. The second - layer metal is usually the thickest metal, which can reduce the parasitic resistance. The secondary coil L2 is also mainly two large loops. In order to have a large enough coupling coefficient kg with the primary coil L1, the secondary coil L2 is basically stacked on top of the primary coil L1, and the main part of the secondary coil L2 corresponds to the main part of the primary coil L1 up and down. The secondary coil L2 is mainly implemented in the top - layer metal, and individual parts are realized by vias across to the second - layer metal. The differential voltage signals are output at both ends p2p and p2n of the secondary coil L2. To make the symmetry of the differential signal better, the center tap of the secondary coil L2 is connected to the center tap of the third coil L3 and given a fixed potential, which is grounded in the design. In this way, the potential here is defined, effectively improving the phase and amplitude symmetry of the differential output signal of the secondary coil L2. The third coil L3 is mainly two small loops, surrounded by the large loops of the primary coil L1 and the secondary coil L2. The two ends P3p and P3n of the third coil L3 are respectively connected to the source electrodes of the differential NMOS pair transistors M2 and M1. The third coil L3 is mainly implemented in the second - layer metal, and individual parts are realized by vias across to the third - layer metal, and the center tap is realized by a via across to the top - layer metal.

[0033] In the three - coil transformer Tr1, the mutual inductance between the primary coil L1 and the secondary coil L2 is equivalent to the gate inductance of the differential NMOS pair transistors M1 and M2, that is Figure 1 Lg1 and Lg2 in Figure 1 . In the three - coil transformer Tr1, the third coil L3 is equivalent to the first part of the source - degeneration inductance of the differential NMOS pair transistors M1 and M2, and the mutual inductance between the primary coil L1 and the third coil L3 is equivalent to the second part of the source - degeneration inductance of the differential NMOS pair transistors M1 and M2. The sum of these two parts is equivalent to Figure 2 the source - degeneration inductance Ls of the differential NMOS pair transistors M1 and M2 in Figure 1The input-stage circuit, and realizes input impedance matching based on the resonance of all capacitors and all equivalently-derived inductors. Since the source degeneration inductors of the differential NMOS pair transistors M1 and M2 are integrated in the three-coil transformer Tr1, the present application greatly reduces the area while improving the circuit linearity. And in the layout design, the third coil L3 and the primary coil L1 are far apart, with a low coupling coefficient, realizing broadband input matching. Each coil is designed as a two-turn loop, so that the center taps of the secondary coil L2 and the third coil L3 correspond up and down, facilitating connection together, and greatly simplifying the routing layout. By connecting the center taps of the secondary coil L2 and the third coil L3 and grounding them, a definite common-mode potential is provided, effectively improving the phase and amplitude balance characteristics of the differential signal output by the secondary coil L2, that is, effectively reducing the amplitude error and phase error of the differential signal output by the secondary coil L2. The amplitude error of the differential signal (relative to 0) is very small, and the phase error (relative to 180 degrees) is also very small.

[0034] Figure 2 The common-gate stage circuit in it includes NMOS transistors M3 to M8 (all common-gate stage transistors), gate decoupling capacitors Cg1 and Cg2, and bias resistors R3 and R4. The drain of NMOS transistor M1 is simultaneously connected to the sources of NMOS transistor M3, NMOS transistor M4, and NMOS transistor M5. The drain of NMOS transistor M2 is simultaneously connected to the sources of NMOS transistor M6, NMOS transistor M7, and NMOS transistor M8. The gates of NMOS transistor M3 and NMOS transistor M8 are respectively connected to the gate bias voltage VBcas through bias resistors R3 and R4. The gates of NMOS transistor M3 and NMOS transistor M8 are also respectively grounded through gate decoupling capacitors Cg1 and Cg2. The function of the gate decoupling capacitors Cg1 and Cg2 is to filter out high-frequency harmonics and noise at the gates of NMOS transistor M3 and NMOS transistor M8. The drains of NMOS transistor M3 and NMOS transistor M4 are connected and then connected to the output load circuit. The drains of NMOS transistor M8 and NMOS transistor M7 are connected and then connected to the output load circuit. The gates of NMOS transistor M4 and NMOS transistor M7 are both connected to the gain control signal GainCtrl. The gain control signal GainCtrl is connected to the inverter B1 and then outputs the inverted gain control signal ENB. ENB is opposite to GainCtrl, that is, when GainCtrl is at a high level, ENB is at a low level, and when GainCtrl is at a low level, ENB is at a high level. The gates of NMOS transistor M5 and NMOS transistor M6 are both connected to the inverted gain control signal ENB. The drains of NMOS transistor M5 and NMOS transistor M6 are both connected to the power supply voltage VDD. The present application is in Figure 1A cascode circuit is added to the shown RF amplifier, which includes six NMOS transistors M3 to M8. The added cascode circuit is used to achieve different gain selections, that is, to achieve a higher dynamic range.

[0035] When the gain control signal GainCtrl is at a high level (value equal to the gate bias voltage VBcas), and the inverted gain control signal ENB is at a low level (value is 0), NMOS transistors M3, M4, M7, and M8 operate normally (conduct), and NMOS transistors M5 and M6 are turned off. Figure 2 The shown cascode circuit operates in a high-gain mode.

[0036] When the gain control signal GainCtrl is at a low level (value is 0), and the inverted gain control signal ENB is at a high level (value equal to the gate bias voltage VBcas), NMOS transistors M4 and M7 are turned off, and NMOS transistors M3, M5, M6, and M8 conduct (operate normally). Part of the current flows through NMOS transistors M5 and M6 to the power supply voltage VDD, and the current flowing to the output load circuit becomes smaller. Figure 2 The shown cascode circuit operates in a low-gain mode.

[0037] In the above two gain modes, the current flowing through the differential NMOS pair transistors M1 and M2 in the input stage circuit remains unchanged, which means that the transconductance of the differential NMOS pair transistors M1 and M2 remains unchanged. Therefore, it does not affect the input matching performance of the input stage circuit, and at the same time provides a large dynamic range.

[0038] Figure 2 The input stage circuit in includes a common-source NMOS pair transistors M1 and M2, and after adding the Figure 2 cascode circuit in, a cascode structure is formed. The cascode NMOS transistors in the cascode structure share a part of the voltage, so that the voltage across the common-source NMOS transistors (such as the source-drain voltage Vds) is smaller, which effectively protects the common-source NMOS transistors, improves the reliability of the circuit, and prevents the circuit from being broken down.

[0039] Compared with Figure 1 Figure 2 The newly added cascode circuit is connected in series with the input stage circuit. This series connection increases the equivalent impedance seen from the drain of the cascode NMOS transistors to the ground, which is called the multiplication effect. Figure 1 The output impedance of the common-source NMOS transistor M1 in is ro1. Figure 2The equivalent impedance (output impedance) seen from the drain of the common-gate NMOS transistor M3 to ground is ro1 + ro3 + gm3 * ro3 * ro1, where ro3 is the output impedance of the NMOS transistor M3 and gm3 is the transconductance of the NMOS transistor M3. Obviously Figure 2 The equivalent output impedance of the circuit is increased by the newly added common-gate circuit, making the circuit have better reverse isolation.

[0040] Figure 2 The common-gate circuit in [] has the characteristic of gain controllability. The above two gain modes achieve gain control through a 1-bit control bit, which means that the gain control signal GainCtrl has only 1 bit and can only achieve gain control of low level or high level (i.e., 0 or 1), and only two gain modes can be obtained.

[0041] Based on the same principle, it can be extended to gain control with any number of bits. Please refer to Figure 9 , Figure 9 The shown common-gate circuit includes 10 NMOS transistors, two inverters B1 and B2, two gain control signals GainCtrl1 and GainCtrl2, and two inverted gain control signals ENB1 and ENB2, so that the control of four gain modes can be achieved through 2-bit control bits. When both gain control signals GainCtrl1 and GainCtrl2 are at high level (represented by the binary number 11), the NMOS transistors M4, M41, M7, and M71 are all turned on, and the NMOS transistors M5, M51, M6, and M61 are all turned off, which is the maximum gain. When both gain control signals GainCtrl1 and GainCtrl2 are at low level (represented by the binary number 00), it is the minimum gain. When the two gain control signals GainCtrl1 and GainCtrl2 are one high and one low (represented by the binary number 01) or one low and one high (represented by the binary number 10), they are the two intermediate gain levels.

[0042] Preferably, the substrates of all NMOS transistors M1 and M2 in the input stage circuit and all NMOS transistors M3 to M8 in the common-gate circuit are grounded.

[0043] Figure 2 The output load circuit in [] includes transformer two Tr2, programmable capacitor array C4, and load resistor R L . The primary coil of transformer two Tr2 is connected in parallel with the programmable capacitor array C4. By adjusting the programmable capacitor array C4, different frequency bands (such as a wide frequency band from 4 GHz to 7 GHz) can be covered and can be used in wireless communication systems such as LTE (Long-Term Evolution), Sub-6 GHz, and WIFI. The center tap of the primary coil of transformer two Tr2 is connected to the power supply voltage VDD. The secondary coil of transformer two Tr2 is connected in parallel with the load resistor R L, the load resistor R L One end of is used as the output voltage vout, and the other end of the load resistor R L is grounded; by changing the load, it can also be applied to higher or lower frequency bands. The radio frequency current signal output by the common-gate stage circuit is transmitted to the resonant frequency selection network composed of the transformer two Tr2 and the adjustable capacitor C4, and through the transformer two Tr2, both the conversion from differential signal to single-ended signal is realized, and the power is transmitted to the load resistor R through the appropriate impedance ratio of the transformer two Tr2 L to achieve high-power signal output, and the load stage converts the radio frequency current signal into a radio frequency voltage signal.

[0044] Compared with the prior art, the radio frequency amplifier proposed in this application has the following advantages.

[0045] First, use a simple three-coil transformer one Tr1 to realize the function of converting single-ended signal to differential signal and achieve good input matching. Compared with the traditional circuit, 3 inductors are saved, the layout area is greatly reduced, and the manufacturing cost and layout design complexity are greatly reduced.

[0046] Second, large-bandwidth input matching is achieved. The main coil L1 and the third coil L3 of the three-coil transformer one Tr1 are far apart and the coupling coefficient is low. This is a broadband design technology that can achieve large-bandwidth input matching. Please refer to Figure 8 , which is a schematic diagram of the input matching of the radio frequency amplifier proposed in this application. The abscissa is the frequency and the ordinate is the S parameter. Experiments show that in the frequency range from 3.62 GHz to 11.07 GHz, the input matching of the radio frequency amplifier proposed in this application is better than -10 dB, achieving broadband input matching. If the size of the three-coil transformer one Tr1 is changed, a wider frequency coverage range will be achieved.

[0047] Third, the center tap of the secondary coil L2 of the three-coil transformer one Tr1 is grounded to give a fixed potential, effectively improving the amplitude and phase error of the differential signal output by the secondary coil L2. Through a special layout design, the wiring layout of the center taps of the secondary coil L2 and the third coil L3 is simplified.

[0048] Fourth, the input stage circuit no longer uses a dedicated source degeneration inductor, but integrates it into the three-coil transformer one Tr1. Using a dedicated source degeneration inductor can improve linearity. This application omits the dedicated source degeneration inductor, but the source degeneration inductor is equivalent from the three-coil transformer one Tr1. Therefore, while maintaining the advantage of improving linearity, a large amount of layout area is saved.

[0049] Fifth, by controlling the gain control signal GainCtrl of the common-gate circuit, the common-gate circuit operates in two gain modes, high and low. Assume that the transistor width-to-length ratios of M3 and M8 are three times those of M4, M5, M6, and M7, and the transistor width-to-length ratios of M4 and M7 are the same as those of M5 and M6. In this way, in the high-gain mode, the current flowing to the output load circuit is W4 / L4 + W3 / L3 = 4*W4 / (3L4); in the low-gain mode, the current flowing to the output load circuit is W4 / L4 - W5 / L5 = 2*W4 / (3L4). Thus, the gain ratio between the high-gain and low-gain modes is 2, that is, a 6 dB dynamic range, achieving dynamic tunability and expanding the application scope.

[0050] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A low-cost and high-performance radio frequency amplifier, characterized in that, It includes an input stage circuit, a common-gate stage circuit, and an output load circuit; The input stage circuit realizes the conversion from a single-ended signal to a differential signal, realizes input impedance matching, and simultaneously converts the input radio frequency voltage signal into a radio frequency current signal; the input stage circuit includes a three-coil transformer 1 and a common-source transistor, and the three-coil transformer 1 is composed of a primary coil, a secondary coil, and a third coil; the secondary coil is connected in parallel with a programmable capacitor array; the coupling inductance between the primary coil and the secondary coil is equivalent to the gate inductance of the common-source transistor; the third coil is equivalent to the first part of the source degeneration inductance of the common-source transistor, and the coupling inductance between the primary coil and the third coil is equivalent to the second part of the source degeneration inductance of the common-source transistor, and the sum of these two parts is equivalent to the source degeneration inductance of the common-source transistor; In the three-coil transformer 1, the primary coil is a two-turn large ring, the secondary coil is also a two-turn large ring, and the secondary coil is stacked above and below the primary coil; the third coil is a two-turn small ring and is surrounded by the large rings of the primary coil and the secondary coil; the center tap of the secondary coil corresponds to, is connected to, and grounded with the center tap of the third coil; The common-gate stage circuit transmits the radio frequency current signal output by the input stage circuit to the output load circuit, simultaneously improves the voltage withstand and equivalent output impedance of the circuit, and realizes gain control in at least two modes; The output load circuit converts the radio frequency current signal from the common-gate stage circuit into a radio frequency voltage signal, realizes the conversion from a differential signal to a single-ended signal, and outputs the amplified radio frequency voltage signal.

2. The low-cost and high-performance radio frequency amplifier according to claim 1, wherein The entire radio frequency amplifier presents a left-right symmetric structure, and the symmetric devices have exactly the same parameters.

3. The low-cost and high-performance radio frequency amplifier according to claim 1, characterized in that, The input stage circuit further includes a programmable capacitor array (C1), two DC-blocking capacitors (C2, C3), a differential NMOS pair (M1, M2), and two bias resistors (R1, R2); the differential NMOS pair (M1, M2) serves as the common-source transistor; In the three-coil transformer 1, one end of the primary coil is connected to the input voltage and the other end is grounded; the secondary coil is connected in parallel with a programmable capacitor array (C1), and the two ends of the secondary coil are also respectively connected to the gates of the differential NMOS pair (M1, M2) through two DC-blocking capacitors (C2, C3); the conversion from a single-ended signal to a differential signal is realized between the primary coil and the secondary coil; the two ends of the third coil are respectively connected to the sources of the differential NMOS pair (M1, M2); The gates of the differential NMOS pair (M1, M2) are also respectively connected to a gate bias voltage 1 through two bias resistors (R1, R2); the drains of the differential NMOS pair (M1, M2) output a differential current signal to the common-gate stage circuit; the differential NMOS pair (M1, M2) realizes the conversion from a voltage signal to a current signal; The input stage circuit realizes input impedance matching based on the resonance of all capacitors and all equivalently derived inductors.

4. The low-cost and high-performance radio frequency amplifier according to claim 3, characterized in that, The common-gate stage circuit includes NMOS transistors (M3 to M8), gate decoupling capacitors (Cg1, Cg2), and bias resistors (R3, R4); The drain of NMOS transistor one (M1) is connected to the sources of NMOS transistor three (M3), NMOS transistor four (M4), and NMOS transistor five (M5) simultaneously; the drain of NMOS transistor two (M2) is connected to the sources of NMOS transistor six (M6), NMOS transistor seven (M7), and NMOS transistor eight (M8) simultaneously; the gates of NMOS transistor three (M3) and NMOS transistor eight (M8) are connected to gate bias voltage two through two bias resistors (R3, R4) respectively; the gates of NMOS transistor three (M3) and NMOS transistor eight (M8) are also grounded through two gate terminal decoupling capacitors (Cg1, Cg2) respectively; the drains of NMOS transistor three (M3) and NMOS transistor four (M4) are connected and then connected to the output load circuit; the drains of NMOS transistor eight (M8) and NMOS transistor seven (M7) are connected and then connected to the output load circuit; the gates of NMOS transistor four (M4) and NMOS transistor seven (M7) are both connected to the gain control signal; the gain control signal is connected to an inverter and then outputs an inverted gain control signal; the gates of NMOS transistor five (M5) and NMOS transistor six (M6) are both connected to the inverted gain control signal; the drains of NMOS transistor five (M5) and NMOS transistor six (M6) are both connected to the power supply voltage.

5. The low-cost and high-performance radio frequency amplifier according to claim 4, wherein When the gain control signal is at a high level and the inverted gain control signal is at a low level, NMOS transistor three (M3), NMOS transistor four (M4), NMOS transistor seven (M7), and NMOS transistor eight (M8) are turned on, and NMOS transistor five (M5) and NMOS transistor six (M6) are turned off, and the cascode circuit operates in a high-gain mode; When the gain control signal is at a low level and the inverted gain control signal is at a high level, NMOS transistor four (M4) and NMOS transistor seven (M7) are turned off, and NMOS transistor three (M3), NMOS transistor five (M5), NMOS transistor six (M6), and NMOS transistor eight (M8) are turned on, and part of the current flows to the power supply voltage through NMOS transistor five (M5) and NMOS transistor six (M6), and the current flowing to the output load circuit becomes smaller, and the cascode circuit operates in a low-gain mode; In the above two gain modes, the current flowing through the differential NMOS pair transistors (M1, M2) in the input stage circuit remains unchanged, that is, the transconductance of the differential NMOS pair transistors (M1, M2) remains unchanged; the above two gain modes expand the dynamic range of the RF amplifier.

6. The low-cost and high-performance radio frequency amplifier according to claim 1, wherein The cascode transistor in the input stage circuit is stacked with the cascode circuit to form a cascode structure; part of the voltage is divided by the cascode transistor in the cascode structure, so that the voltage across the cascode transistor becomes smaller.

7. The low-cost and high-performance radio frequency amplifier according to claim 1, characterized in that, The cascode circuit is connected in series with the input stage circuit, so that the equivalent output impedance seen from the drain terminal of the cascode transistor to the ground increases.

8. The low-cost and high-performance radio frequency amplifier according to claim 1, wherein, The common-gate circuit includes ten NMOS transistors (M3, M4, M41, M5, M51, M6, M61, M7, M71, M8), two inverters (B1, B2), two gain control signals (GainCtrl1, GainCtrl2), and two inverted gain control signals (ENB1, ENB2); When both of the two gain control signals (GainCtrl1, GainCtrl2) are at high level, the NMOS transistors (M4, M41, M7, M71) are turned on, and the NMOS transistors (M5, M51, M6, M61) are turned off, and the common-gate circuit operates in the maximum gain mode; When both of the two gain control signals (GainCtrl1, GainCtrl2) are at low level, the common-gate circuit operates in the minimum gain mode; When the two gain control signals (GainCtrl1, GainCtrl2) are at one high and one low level or one low and one high level, the common-gate circuit operates in the intermediate two gain modes; The above four gain modes expand the dynamic range of the radio frequency amplifier.

9. The low-cost and high-performance radio frequency amplifier according to claim 1, characterized in that, The output load circuit includes transformer two, a programmable capacitor array (C4), and a load resistor; The primary coil of transformer two is connected in parallel with the programmable capacitor array (C4), and different frequency bands are covered by adjusting the programmable capacitor array (C4); the center tap of the primary coil of transformer two is connected to the power supply voltage; the secondary coil of transformer two is connected in parallel with the load resistor; one end of the load resistor is used as the output voltage, and the other end of the load resistor is grounded; The radio frequency current signal output by the common-gate circuit is transmitted to the resonant frequency selection network composed of transformer two and the programmable capacitor array (C4). Transformer two not only realizes the conversion from differential signal to single-ended signal, but also transfers the power to the load resistor through the impedance transformation ratio of transformer two to realize signal amplification and output. The load resistor converts the radio frequency current signal into a radio frequency voltage signal.

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