An enabling circuit and a chip applied to a high-voltage process

Abstract

The present invention provides an enabling circuit applied to a high-voltage process, which includes: the input end of a first conversion module is connected to a first signal, and by performing a conversion operation on the first signal, a second signal and a third signal are generated; a second conversion module generates a second enabling signal by performing a conversion operation on a first enabling signal; a reference module generates a reference signal based on the electric energy provided by the second signal; the input end of a comparison module generates a corresponding third enabling signal through a comparison operation between the second enabling signal and the reference signal; a shaping module generates a fourth enabling signal for controlling the activation of a subsequent load through a shaping operation on the third enabling signal. It can accurately and stably convert a 40-volt enabling signal into an enabling signal for activating a chip or a circuit, and at the same time can resist the interference of glitch signals in the high-voltage signal to the subsequent chip or circuit. It has a simple structure, is easy to operate, and has wide applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and application, and particularly to an enable circuit and a chip applied to a high-voltage process. Background Art

[0002] The enable circuit is responsible for controlling the input and output of the enable signal, and is usually connected to the enable terminal of the chip or circuit. The enable circuit controls the on state of the chip or circuit based on the enable signal. When the voltage of the enable signal approaches a high voltage of 40 volts, how to accurately and stably convert the 40-volt enable signal into an enable signal for turning on the chip or circuit, while avoiding the negative impact of glitch interference on the safety of the subsequent chip or circuit, is the focus of the design and application of the enable circuit.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide an enable circuit and a chip applied to a high-voltage process, which are used to solve the problem that it is relatively difficult to accurately and stably convert a high-voltage enable signal into an enable signal for turning on a chip or circuit in the prior art.

[0005] To achieve the above purpose and other related purposes, the present invention provides an enable circuit applied to a high-voltage process. The enable circuit applied to the high-voltage process at least includes: a first conversion module, a second conversion module, a reference module, a comparison module, and a shaping module, wherein:

[0006] The input end of the first conversion module is connected to a first signal, and by performing a conversion operation on the first signal, a second signal for providing electric energy and a third signal for providing drive are generated;

[0007] The input end of the second conversion module is connected to a first enable signal and the third signal, and by performing a conversion operation on the first enable signal, a second enable signal is generated;

[0008] The input end of the reference module is connected to the output end of the first conversion module, and a reference signal is generated based on the electric energy provided by the second signal;

[0009] The input end of the comparison module is connected to the output end of the reference module and the output end of the second conversion module, and by performing a comparison operation on the second enable signal and the reference signal, a corresponding third enable signal is generated;

[0010] The input end of the shaping module is connected to the output end of the comparison module, and a fourth enable signal for controlling the activation of the subsequent load is generated through the shaping operation of the third enable signal.

[0011] Optionally, the first conversion module includes: a first resistor, a first NMOS power transistor, a first zener diode, and a first capacitor, where: the first end of the first resistor is connected to the first signal, and based on the second end of the first resistor, the third signal is generated; the drain of the first NMOS power transistor is connected to the first end of the first resistor, the gate of the first NMOS power transistor is connected to the second end of the first resistor, and based on the source of the first NMOS power transistor, the second signal is generated; the cathode of the first zener diode is connected to the gate of the first NMOS power transistor, and the anode of the first zener diode is connected to the reference ground; the first capacitor is connected between the source of the first NMOS power transistor and the reference ground.

[0012] Optionally, the voltage range of the first signal includes greater than 0 volts and less than or equal to 40 volts.

[0013] Optionally, the breakdown voltage value of the first NMOS power transistor is greater than 40 volts.

[0014] Optionally, the reference module includes: a second resistor and a second NMOS power transistor, where: the drain of the second NMOS power transistor is connected to the gate, the source of the second NMOS power transistor is connected to the reference ground, and based on the gate of the second NMOS power transistor, the reference signal is generated; the second resistor is connected between the second signal and the drain of the second NMOS power transistor.

[0015] Optionally, the second conversion module includes: a third NMOS power transistor and a fourth NMOS power transistor, where: the drain of the third NMOS power transistor is connected to the first enable signal, the gate of the third NMOS power transistor is connected to the third signal, and based on the source of the third NMOS power transistor, the second enable signal is generated; the drain of the fourth NMOS power transistor is connected to the source of the third NMOS power transistor, the gate of the fourth NMOS power transistor is connected to the gate of the second NMOS power transistor, and the source of the fourth NMOS power transistor is connected to the reference ground.

[0016] Optionally, the voltage range of the first enable signal includes greater than 0 volts and less than or equal to 40 volts.

[0017] Optionally, the breakdown voltage value of the third NMOS power transistor is greater than 40 volts.

[0018] Optionally, the comparison module includes: a first PMOS power transistor, a second PMOS power transistor, a fifth NMOS power transistor, a sixth NMOS power transistor, a seventh NMOS power transistor, an eighth NMOS power transistor, and a first NOT gate, where: the source of the first PMOS power transistor is connected to the second signal; the source of the second PMOS power transistor is connected to the source of the first PMOS power transistor, the gate of the second PMOS power transistor is connected to the gate of the first PMOS power transistor, and the drain of the second PMOS power transistor is connected to the gate of the second PMOS power transistor; the drain of the fifth NMOS power transistor is connected to the drain of the first PMOS power transistor, and the gate of the fifth NMOS power transistor is connected to the source of the third NMOS power transistor; the drain of the sixth NMOS power transistor is connected to the source of the fifth NMOS power transistor, the gate of the sixth NMOS power transistor is connected to the gate of the fifth NMOS power transistor, and the source of the sixth NMOS power transistor is connected to the reference ground; the drain of the seventh NMOS power transistor is connected to the drain of the sixth NMOS power transistor, and the source of the seventh NMOS power transistor is connected to the reference ground; the drain of the eighth NMOS power transistor is connected to the drain of the second PMOS power transistor, the gate of the eighth NMOS power transistor is connected to the gate of the fourth NMOS power transistor, and the source of the eighth NMOS power transistor is connected to the reference ground; the input terminal of the first NOT gate is connected to the drain of the fifth NMOS power transistor, and the output terminal of the first NOT gate is connected to the gate of the seventh NMOS power transistor, where the third enable signal is generated based on the output terminal of the first NOT gate.

[0019] Optionally, the shaping module includes a second NOT gate and a third NOT gate, where: the input terminal of the second NOT gate is connected to the third enable signal; the input terminal of the third NOT gate is connected to the output terminal of the second NOT gate.

[0020] To achieve the above and other related objectives, the present invention provides a chip, which includes the enable circuit applied to the high-voltage process, and the chip outputs the fourth enable signal for controlling the turn-on of the subsequent load.

[0021] As described above, an enable circuit and a chip applied to the high-voltage process according to the present invention have the following beneficial effects:

[0022] 1) The enable circuit and the chip applied to the high-voltage process according to the present invention can accurately and stably convert a 40-volt enable signal into an enable signal for turning on the chip or the circuit, and at the same time can resist the interference of the glitch signal in the high-voltage signal to the subsequent chip or circuit.

[0023] 2) The enabling circuit and chip applied in the high-voltage process of the present invention have a simple structure, are easy to operate, and have wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It shows a schematic structural diagram of the enabling circuit applied in the high-voltage process of the present invention.

[0025] Figure 2 It shows an exemplary circuit schematic diagram of the enabling circuit applied in the high-voltage process of the present invention.

[0026] Figure 3 It shows a timing schematic diagram of each signal in the enabling circuit applied in the high-voltage process of the present invention.

[0027] DESCRIPTION OF THE REFERENCE NUMERALS

[0028] 1 Enabling circuit applied in the high-voltage process

[0029] 11 First conversion module

[0030] 12 Second conversion module

[0031] 13 Reference module

[0032] 14 Comparison module

[0033] 15 Shaping module DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] The following uses specific specific examples to illustrate the embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Please refer to Figures 1 to 3 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0036] As Figure 1 shown, this embodiment provides an enabling circuit 1 applied in the high-voltage process. The enabling circuit 1 applied in the high-voltage process at least includes: a first conversion module 11, a second conversion module 12, a reference module 13, a comparison module 14, and a shaping module 15, wherein:

[0037] AsFigure 1 As shown, the input terminal of the first conversion module 11 is connected to the first signal VDDH. Through the conversion operation of the first signal VDDH, a second signal VDDL for providing electrical energy and a third signal VDDH_L for providing drive are generated.

[0038] Specifically, as an example, as Figure 2 shown, the first conversion module 11 includes: a first resistor R1, a first NMOS power transistor N1, a first zener diode D1, and a first capacitor C1, where: the first end of the first resistor R1 is connected to the first signal VDDH, and based on the second end of the first resistor R1, the third signal VDDH_L is generated; the drain of the first NMOS power transistor N1 is connected to the first end of the first resistor R1, and the gate of the first NMOS power transistor N1 is connected to the second end of the first resistor R1, and based on the source of the first NMOS power transistor N1, the second signal VDDL is generated; the negative electrode of the first zener diode D1 is connected to the gate of the first NMOS power transistor N1, and the positive electrode of the first zener diode D1 is connected to the reference ground GND; the first capacitor C1 is connected between the source of the first NMOS power transistor N1 and the reference ground GND. More specifically, the voltage range of the first signal VDDH includes greater than 0 volts and less than or equal to 40 volts. Further, the breakdown voltage value of the first NMOS power transistor N1 is greater than 40 volts.

[0039] It should be noted that the first signal VDDH is usually provided by a DC power supply. Among them, the voltage range of the first signal VDDH is (0, 40 volts], and the first conversion module 11 performs a DC / DC conversion operation (Direct Current, abbreviated as DC) to step down the first signal VDDH to generate two signals, namely the second signal VDDL and the third signal VDDH_L. In this embodiment, the first signal VDDH generates the third signal VDDH_L through the voltage division operation of the first resistor R1. The first signal VDDH is connected to the drain of the first NMOS power transistor N1, and the third signal VDDH_L is connected to the gate of the first NMOS power transistor N1. By applying signals to the gate and source of the first NMOS power transistor N1, the first NMOS power transistor N1 is turned on, and based on the source of the first NMOS power transistor N1, the second signal VDDL is generated. The second signal VDDL is used to supply power to the next-stage devices (the next-stage devices include: a reference module 13, a comparison module 14, and a shaping module 15. These devices are usually low-voltage devices, and their operating voltages usually do not exceed 5 volts); the third signal VDDH_L is used to provide drive to the second conversion module 12.

[0040] It should be noted that the first conversion module 11 can also be set as an application specific integrated circuit (ASIC), or can be set using an IP core (IP core, short for Intellectual Property core, is a hardware description language program with specific circuit functions. This program is independent of the integrated circuit process and can be transplanted to different semiconductor processes to produce integrated circuit chips. Using an IP core for electronic system design has the characteristics of convenient reference and easy modification of the functions of basic components. IP cores with complex functions and commercial value have intellectual property attributes. Although the market activities of IP cores are not yet standardized, there are still many integrated circuit design companies engaged in the design, development, and marketing of IP cores. There are two types of IP cores. The hardware description language program independent of the process is called a soft core; the integrated circuit layout with specific circuit functions is called a hard core. Hard cores are generally not allowed to be modified. Using a hard core for integrated circuit design is difficult, but the success rate of tape-out will increase significantly). As long as it can perform the conversion operation on the first signal VDDH to generate the second signal VDDL for supplying electrical energy and the third signal VDDH_L for providing drive, any setting form of the first conversion module 11 is applicable, and it is not limited to this embodiment.

[0041] As Figure 1 shown, the input end of the second conversion module 12 is connected to the first enable signal EN and the third signal VDDH_L, and generates the second enable signal EN_L through the conversion operation on the first enable signal EN.

[0042] Specifically, as an example, as Figure 2 shown, the second conversion module 12 includes: a third NMOS power transistor N3 and a fourth NMOS power transistor N4, where: the drain of the third NMOS power transistor N3 is connected to the first enable signal EN, the gate of the third NMOS power transistor N3 is connected to the third signal VDDH_L, and the second enable signal EN_L is generated based on the source of the third NMOS power transistor N3; the drain of the fourth NMOS power transistor N4 is connected to the source of the third NMOS power transistor N3, the gate of the fourth NMOS power transistor N4 is connected to the gate of the second NMOS power transistor N2, and the source of the fourth NMOS power transistor N4 is connected to the reference ground GND. Specifically, the voltage range of the first enable signal EN includes greater than 0 volts and less than or equal to 40 volts. Further, the breakdown voltage value of the third NMOS power transistor N3 is greater than 40 volts.

[0043] It should be noted that the voltage range of the first enable signal EN is (0, 40 volts]. The second conversion module 12 performs a step-down operation on the first enable signal EN to generate a second enable signal EN_L. In this embodiment, the first enable signal EN is connected to the drain of the third NMOS power transistor N3, and the third signal VDDH_L is connected to the gate of the third NMOS power transistor N3. By applying signals to the gate and source of the third NMOS power transistor N3, the third NMOS power transistor N3 is turned on, and the second enable signal EN_L is generated based on the source of the third NMOS power transistor N3. The gate of the fourth NMOS power transistor N4 is connected to the gate of the second NMOS power transistor N2, and the fourth NMOS power transistor N4 generates a mirror current based on the reference current generated by the second resistor R2 and the second NMOS power transistor N2.

[0044] It should be further noted that the second conversion module 12 can also be set as an application-specific integrated circuit or can be set using an IP core. As long as it can perform the conversion operation on the first enable signal EN to generate the second enable signal EN_L, any setting form of the second conversion module 12 is applicable and is not limited to this embodiment.

[0045] As Figure 1 shown, the input end of the reference module 13 is connected to the output end of the first conversion module 11, and a reference signal VBN is generated based on the electric energy provided by the second signal VDDL.

[0046] Specifically, as an example, as Figure 2 shown, the reference module 13 includes: a second resistor R2 and a second NMOS power transistor N2, where: the drain of the second NMOS power transistor N2 is connected to the gate, the source of the second NMOS power transistor N2 is connected to the reference ground GND, and the reference signal VBN is generated based on the gate of the second NMOS power transistor N2; the second resistor R2 is connected between the second signal VDDL and the drain of the second NMOS power transistor N2.

[0047] It should be noted that the second signal VDDL is divided by the second resistor R2 and connected to the drain of the second NMOS power transistor N2, and a reference current is generated by turning on the second NMOS power transistor N2. It should be further noted that the reference module 13 can also be set as an application-specific integrated circuit or can be set using an IP core. As long as it can generate a reference current, any setting form of the reference module 13 is applicable and is not limited to this embodiment.

[0048] As Figure 1 shown, the input end of the comparison module 14 is connected to the output end of the reference module 13 and the output end of the second conversion module 12, and a corresponding third enable signal ENFB is generated by comparing the second enable signal EN_L with the reference signal VBN.

[0049] Specifically, as an example, as Figure 2 shown, the comparison module 14 includes: a first PMOS power transistor P1, a second PMOS power transistor P2, a fifth NMOS power transistor N5, a sixth NMOS power transistor N6, a seventh NMOS power transistor N7, an eighth NMOS power transistor N8, and a first NOT gate NOT1, where: the source of the first PMOS power transistor P1 is connected to the second signal VDDL; the source of the second PMOS power transistor P2 is connected to the source of the first PMOS power transistor P1, the gate of the second PMOS power transistor P2 is connected to the gate of the first PMOS power transistor P1, and the drain of the second PMOS power transistor P2 is connected to the gate of the second PMOS power transistor P2; the drain of the fifth NMOS power transistor N5 is connected to the drain of the first PMOS power transistor P1, the gate of the fifth NMOS power transistor N5 is connected to the source of the third NMOS power transistor N3, where the gate of the fifth NMOS power transistor N5 is connected to the second enable signal EN_L; the drain of the sixth NMOS power transistor N6 is connected to the source of the fifth NMOS power transistor N5, the gate of the sixth NMOS power transistor N6 is connected to the gate of the fifth NMOS power transistor N5, and the source of the sixth NMOS power transistor N6 is connected to the reference ground GND; the drain of the seventh NMOS power transistor N7 is connected to the drain of the sixth NMOS power transistor N6, and the source of the seventh NMOS power transistor N7 is connected to the reference ground GND; the drain of the eighth NMOS power transistor N8 is connected to the drain of the second PMOS power transistor P2, the gate of the eighth NMOS power transistor N8 is connected to the gate of the fourth NMOS power transistor N4, and the source of the eighth NMOS power transistor N8 is connected to the reference ground GND, where the eighth NMOS power transistor N8 generates an image current based on the reference current generated by the second resistor R2 and the second NMOS power transistor N2; the input terminal of the first NOT gate NOT1 is connected to the drain of the fifth NMOS power transistor N5, and the output terminal of the first NOT gate NOT1 is connected to the gate of the seventh NMOS power transistor N7, where the third enable signal ENFB is generated based on the output terminal of the first NOT gate NOT1.

[0050] It should be noted that the voltage range of the first enable signal EN is (0, 40 volts]. When the voltage of the first enable signal EN gradually increases from low, when the voltage of the first enable signal EN rises to the turn-on threshold of the fifth NMOS power transistor N5 and the sixth NMOS power transistor N6, the conduction current I of the fifth NMOS power transistor N5 and the sixth NMOS power transistor N6 N56 is greater than or equal to the conduction current I of the first PMOS power transistor P1 P1 , that is, I N56 ≥I P1, the third enable signal ENFB is at a high level. When the voltage of the first enable signal EN gradually decreases from a high level, when the voltage of the first enable signal EN drops below the turn-on thresholds of the fifth NMOS power transistor N5 and the sixth NMOS power transistor N6, then I N56 <I P1 , the third enable signal ENFB is at a low level. It should be further noted that the comparison module 14 can also be set as an application-specific integrated circuit or can be set using an IP core. As long as it can perform the comparison operation between the second enable signal EN_L and the reference signal VBN to generate the corresponding third enable signal ENFB, any setting form of the comparison module 14 is applicable and is not limited to this embodiment.

[0051] Such as Figure 1 shown, the input end of the shaping module 15 is connected to the output end of the comparison module 14. By performing a shaping operation on the third enable signal ENFB, a fourth enable signal ENBB for controlling the turn-on of the subsequent load is generated.

[0052] Specifically, as an example, as Figure 2 shown, the shaping module 15 includes a second NOT gate NOT2 and a third NOT gate NOT3, where: the input end of the second NOT gate NOT2 is connected to the third enable signal ENFB; the input end of the third NOT gate NOT3 is connected to the output end of the second NOT gate NOT2. It should be noted that by performing a shaping operation on the third enable signal ENFB by the shaping module 15, a fourth enable signal ENBB for controlling the turn-on of the subsequent load is generated.

[0053] It should be noted that the voltage range of the first enable signal EN is (0, 40 volts]. When the voltage of the first enable signal EN gradually increases from a low level, when the voltage of the first enable signal EN rises to the turn-on thresholds of the fifth NMOS power transistor N5 and the sixth NMOS power transistor N6, the second enable signal EN_L also gradually increases from a low level. When the voltage of the first enable signal EN gradually decreases from a high level, when the voltage of the first enable signal EN drops below the turn-on thresholds of the fifth NMOS power transistor N5 and the sixth NMOS power transistor N6, the second enable signal EN_L also gradually decreases from a high level. And the second enable signal EN_L undergoes a comparison operation by the comparison module 14 to generate the corresponding third enable signal ENFB, and the third enable signal ENFB changes with the change of the second enable signal EN_L; after further performing a shaping operation on the third enable signal ENFB by the shaping module 15, the timing of the fourth enable signal ENBB meets the timeliness requirements for the turn-on of the subsequent load. Among them, for the timing of the first signal VDDH, the second signal VDDL, the second enable signal EN_L, and the fourth enable signal ENBB, please refer to Figure 3 shown.

[0054] This embodiment also provides a chip, which includes: an enabling circuit applied to a high-voltage process as described in this embodiment, and the chip outputs a fourth enabling signal for controlling the activation of a subsequent load.

[0055] In summary, an enabling circuit applied to a high-voltage process according to the present invention at least includes: a first conversion module, a second conversion module, a reference module, a comparison module, and a shaping module, where: the input end of the first conversion module is connected to a first signal, and by performing a conversion operation on the first signal, a second signal for providing electrical energy and a third signal for providing drive are generated; the input end of the second conversion module is connected to a first enabling signal and the third signal, and by performing a conversion operation on the first enabling signal, a second enabling signal is generated; the input end of the reference module is connected to the output end of the first conversion module, and a reference signal is generated based on the electrical energy provided by the second signal; the input end of the comparison module is connected to the output end of the reference module and the output end of the second conversion module, and by performing a comparison operation on the second enabling signal and the reference signal, a corresponding third enabling signal is generated; the input end of the shaping module is connected to the output end of the comparison module, and by performing a shaping operation on the third enabling signal, a fourth enabling signal for controlling the activation of a subsequent load is generated. The enabling circuit and chip applied to a high-voltage process according to the present invention can accurately and stably convert a 40-volt enabling signal into an enabling signal for activating a chip or a circuit, and at the same time can resist the interference of glitch signals in the high-voltage signal to the subsequent chip or circuit. The enabling circuit and chip applied to a high-voltage process according to the present invention have a simple structure and convenient operation, and have wide applicability. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0056] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An enabling circuit applied in a high-voltage process, characterized in that, The enabling circuit applied to the high-voltage process at least includes: a first conversion module, a second conversion module, a reference module, a comparison module, and a shaping module, where: The input end of the first conversion module is connected to a first signal. By performing a conversion operation on the first signal, a second signal for providing electric energy and a third signal for providing drive are generated; The input end of the reference module is connected to the output end of the first conversion module, and a reference signal is generated based on the electric energy provided by the second signal. The reference module includes: a second resistor and a second NMOS power transistor, where: the drain of the second NMOS power transistor is connected to its gate, the source of the second NMOS power transistor is connected to the reference ground, and the reference signal is generated based on the gate of the second NMOS power transistor; the second resistor is connected between the second signal and the drain of the second NMOS power transistor; The input end of the second conversion module is connected to a first enabling signal and the third signal. By performing a conversion operation on the first enabling signal, a second enabling signal is generated. The second conversion module includes: a third NMOS power transistor and a fourth NMOS power transistor, where: the drain of the third NMOS power transistor is connected to the first enabling signal, the gate of the third NMOS power transistor is connected to the third signal, and the second enabling signal is generated based on the source of the third NMOS power transistor; the drain of the fourth NMOS power transistor is connected to the source of the third NMOS power transistor, the gate of the fourth NMOS power transistor is connected to the gate of the second NMOS power transistor, and the source of the fourth NMOS power transistor is connected to the reference ground; The input end of the comparison module is connected to the output end of the reference module and the output end of the second conversion module. By performing a comparison operation on the second enabling signal and the reference signal, a corresponding third enabling signal is generated; The input end of the shaping module is connected to the output end of the comparison module. By performing a shaping operation on the third enabling signal, a fourth enabling signal for controlling the activation of the subsequent load is generated.

2. The enabling circuit applied to the high-voltage process according to claim 1, characterized in that: The first conversion module includes: a first resistor, a first NMOS power transistor, a first zener diode, and a first capacitor, where: the first end of the first resistor is connected to the first signal, and the third signal is generated based on the second end of the first resistor; the drain of the first NMOS power transistor is connected to the first end of the first resistor, the gate of the first NMOS power transistor is connected to the second end of the first resistor, and the second signal is generated based on the source of the first NMOS power transistor; the negative electrode of the first zener diode is connected to the gate of the first NMOS power transistor, and the positive electrode of the first zener diode is connected to the reference ground; the first capacitor is connected between the source of the first NMOS power transistor and the reference ground.

3. The enabling circuit applied to the high-voltage process according to claim 1, wherein: The voltage range of the first signal includes greater than 0 volts and less than or equal to 40 volts.

4. The enabling circuit applied to a high-voltage process according to claim 2, wherein: The breakdown voltage value of the first NMOS power transistor is greater than 40 volts.

5. The enabling circuit applied to the high-voltage process according to claim 1, wherein: The voltage range of the first enabling signal includes greater than 0 volts and less than or equal to 40 volts.

6. The enabling circuit applied to the high-voltage process according to claim 1, characterized in that: The breakdown voltage value of the third NMOS power transistor is greater than 40 volts.

7. The enabling circuit applied to the high-voltage process according to claim 1, wherein: The comparison module includes: a first PMOS power transistor, a second PMOS power transistor, a fifth NMOS power transistor, a sixth NMOS power transistor, a seventh NMOS power transistor, an eighth NMOS power transistor, and a first NOT gate, where: the source of the first PMOS power transistor is connected to the second signal; the source of the second PMOS power transistor is connected to the source of the first PMOS power transistor, the gate of the second PMOS power transistor is connected to the gate of the first PMOS power transistor, and the drain of the second PMOS power transistor is connected to the gate of the second PMOS power transistor; the drain of the fifth NMOS power transistor is connected to the drain of the first PMOS power transistor, and the gate of the fifth NMOS power transistor is connected to the source of the third NMOS power transistor; the drain of the sixth NMOS power transistor is connected to the source of the fifth NMOS power transistor, the gate of the sixth NMOS power transistor is connected to the gate of the fifth NMOS power transistor, and the source of the sixth NMOS power transistor is connected to the reference ground; the drain of the seventh NMOS power transistor is connected to the drain of the sixth NMOS power transistor, and the source of the seventh NMOS power transistor is connected to the reference ground; the drain of the eighth NMOS power transistor is connected to the drain of the second PMOS power transistor, the gate of the eighth NMOS power transistor is connected to the gate of the fourth NMOS power transistor, and the source of the eighth NMOS power transistor is connected to the reference ground; the input terminal of the first NOT gate is connected to the drain of the fifth NMOS power transistor, and the output terminal of the first NOT gate is connected to the gate of the seventh NMOS power transistor, where the third enabling signal is generated based on the output terminal of the first NOT gate.

8. The enabling circuit applied to a high-voltage process according to claim 1, characterized in that: The shaping module includes a second NOT gate and a third NOT gate, where: the input terminal of the second NOT gate is connected to the third enabling signal; the input terminal of the third NOT gate is connected to the output terminal of the second NOT gate.

9. A chip, characterized in that: The chip includes: an enabling circuit applied to a high-voltage process according to any one of claims 1-8, and the chip outputs the fourth enabling signal for controlling the turn-on of a subsequent load.

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