Test generation method, device, equipment and storage medium for eliminating redundant faults

Abstract

The present invention relates to the field of chip testing technology, and in particular to a test generation method, device, equipment and storage medium for eliminating redundant faults, wherein the method determines whether redundant fault elimination is currently required through system operation data, thereby increasing the success rate of dynamic streamlining in test generation, reducing the generated test vectors, and when the test vector is generated, all faults in a fault list are judged through a single fault test generator, and when the selected main fault cannot generate a test cube, the main fault is eliminated, and when the main fault can generate a test cube, a test cube is generated for the main fault, and a fault is randomly selected from the remaining faults in the fault list as a secondary fault, and bits are filled in the test cube through the secondary fault to generate a test vector, thereby solving the current test generation scheme. Since redundant faults are not eliminated, the system has a low ability to streamline vectors, resulting in a long running time and a large number of test vectors.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a test generation method, device, equipment and storage medium for eliminating redundant faults. Background Art

[0002] With the increasing scale of chips, Electronic Design Automation (EDA) tools are indispensable in the field of chip design. In the actual chip generation process, defects are inevitable. In order to detect defects in chip manufacturing as early as possible, the Design for Testability (DFT) method has become an important process in chip design. Among them, the Automatic Test Pattern Generation (ATPG) method generates test vectors for the chip to be tested in the design stage. After the chip is manufactured, it will be loaded on the Automatic Test Equipment (ATE), and the previously generated vectors will be applied to the machine to detect defects in the chip. Test Application Time (TAT) and Test Volume (TV) are important indicators for evaluating the quality of test vectors generated by ATPG. In order to generate high-quality test vectors and reduce test costs, many test vector generation methods for test simplification have been proposed in recent years.

[0003] The structured ATPG method will generate a test cube for a single fault. The test cube is a test vector containing X bits. The mainstream method of test reduction aims to explore how to fill test cubes of multiple different faults into a simplified test cube. Among them, incremental test vector generation is widely used.

[0004] The incremental test vector generation method first selects a major fault and generates a test cube for it, then selects secondary faults by some method. The test generation of secondary faults is performed under the condition that the existing test cube is used as input constraint. If the test vector generation of the secondary fault is successful, the process continues until all the faults to be tested have been tried as secondary faults or there is no X in the test cube. Incremental test vector generation can generate a very compact test vector set.

[0005] However, incremental test generation only focuses on the generation of a single test vector, and does not optimize the generation of vectors from the perspective of the entire ATPG system. In the actual test generation process, there is a phenomenon that the ATPG system often generates a large number of test vectors for the remaining very small number of faults at the end of the test generation, that is, when all the faults to be tested are about to be classified, and these faults are often difficult to test. The existing dynamic reduction technology does not take into account that the distribution of fault types will change as the test generation proceeds, that is, the probability of redundant faults being selected at the end will increase significantly, and thus does not fully utilize this feature to further improve the ability of the ATPG system to reduce vectors. Summary of the invention

[0006] In view of this, the purpose of the present invention is to provide a test generation method, device, equipment and storage medium for eliminating redundant faults, so as to overcome the current test generation scheme, which does not eliminate redundant faults, has low ability to streamline vectors in the system, resulting in long running time and a large number of test vectors.

[0007] To achieve the above objectives, the present invention adopts the following technical solutions:

[0008] In a first aspect, the present application provides a test generation method for eliminating redundant faults, comprising:

[0009] Obtain a netlist in Verilog format, and parse the netlist using a netlist parser;

[0010] Analyze the parsed netlist by a fault list analyzer to generate a fault list;

[0011] Randomly select a fault from the fault list as a main fault, test the main fault through a single fault test generator, obtain system operation data, and determine whether the current system performs redundant fault elimination according to the system operation data;

[0012] If yes, determine whether the main fault can generate a test cube;

[0013] If yes, a test cube is generated for the primary fault, and a fault is randomly selected from the remaining faults in the fault list as a secondary fault, and bits are filled for the test cube through the secondary fault to generate a test vector;

[0014] If not, eliminate the major fault and reselect the major fault in the fault list.

[0015] Furthermore, in the above method, the obtaining of system operation data and determining whether the current system is performing redundant fault troubleshooting according to the system operation data include:

[0016] Obtain system operation data;

[0017] According to the system operation data, the remaining ATPG operation cost is calculated by a first formula, and the cost of performing redundancy identification at the current moment is calculated by a second formula;

[0018] Whether the current system performs redundant fault elimination is determined by determining whether the ratio of the remaining ATPG operation cost to the cost of performing redundant identification at the current moment exceeds a preset parameter.

[0019] Further, the method described above, generating a test cube for the primary fault, and randomly selecting a fault from the remaining faults in the fault list as a secondary fault, filling bits for the test cube with the secondary fault, and generating a test vector, includes:

[0020] generating a test cube for the major fault by the single fault test generator;

[0021] Randomly selecting a secondary fault for the primary fault in the fault list;

[0022] Determining whether the secondary fault can generate a test by the single fault test generator;

[0023] If yes, filling bits for the test cube according to the test generated by the secondary fault to generate a test vector;

[0024] If not, a secondary fault is reselected, and the secondary fault failure count of the primary fault is increased by one. After the secondary fault failure count reaches a preset number, the primary fault is abandoned and a new primary fault is reselected.

[0025] Further, in the method described above, the test generated according to the secondary fault is to fill bits in the test cube to generate a test vector, including:

[0026] Filling bits for the test cube according to the test generated by the minor fault, and determining whether there is an uncertain bit in the filled test cube;

[0027] If it exists, the uncertain bits are randomly filled and a complete test vector is generated.

[0028] Furthermore, the above method further includes:

[0029] Obtaining the number of the generated test vectors;

[0030] When the number of the test vectors exceeds a preset number, all the test vectors are simulated by a fault simulator to determine the tested faults, and the tested faults are removed from the fault list.

[0031] Furthermore, the above method further includes:

[0032] When there is no fault that can be tried in the fault list, the number and generation time of the generated test vectors are reported.

[0033] Furthermore, in the above method, the first formula is:

[0034]

[0035] The second formula is:

[0036]

[0037] in, represents the remaining ATPG run cost, represents the cost of redundant identification at the current moment, It represents the average number of newly detected faults per test vector in the last simulation under the current state of the system. It indicates the average running time of each test vector ATPG in the last simulation under the current state of the system. It represents the average running time of all classified major faults in the current state of the system. Indicates the number of vectors for each simulation of the system;

[0038]

[0039] in, represents the proportion of major faults in the most recent set of tests on the system that were classified as testable and redundant; Indicates the total number of faults remaining.

[0040] In a second aspect, the present application provides a test generation device for eliminating redundant faults, comprising:

[0041] A fault list generation module is used to obtain a netlist in a Verilog format, parse the netlist through a netlist parser, analyze the parsed netlist through a fault list analyzer, and generate a fault list;

[0042] Starting the judgment module, randomly selecting a fault from the fault list as the main fault, testing the main fault through a single fault test generator, acquiring system operation data, and judging whether the current system performs redundant fault elimination according to the system operation data;

[0043] A test vector generation module is used to determine whether a test cube can be generated for the main fault when redundant fault troubleshooting is required; if so, a test cube is generated for the main fault, and a fault is randomly selected from the remaining faults in the fault list as a secondary fault, bits are filled in the test cube through the secondary fault to generate a test vector; if not, the main fault is eliminated and a main fault is reselected in the fault list.

[0044] In a third aspect, the present application provides a test generation device for eliminating redundant faults, including a processor and a memory, wherein the processor is connected to the memory:

[0045] Wherein, the processor is used to call and execute the program stored in the memory;

[0046] The memory is used to store the program, and the program is used to execute at least any one of the above test generation methods for eliminating redundant faults.

[0047] In a fourth aspect, the present application provides a computer-readable medium having a non-volatile program code executable by a processor, wherein the program code enables the processor to execute any of the above-described test generation methods for eliminating redundant faults.

[0048] The beneficial effects of the present invention are:

[0049] The present application first obtains a netlist in a Verilog format, and parses the netlist through a netlist parser, analyzes the parsed netlist through a fault list analyzer, generates a fault list, randomly selects a fault from the fault list as a major fault, tests the major fault through a single fault test generator, obtains system operation data, determines whether the current system performs redundant fault elimination according to the system operation data, and if so, determines whether a test cube can be generated for the major fault. If so, a test cube is generated for the major fault, and randomly selects a fault from the remaining faults in the fault list as a secondary fault, fills bits for the test cube through the secondary fault, and generates a test vector. If not, the major fault is eliminated and the major fault is reselected in the fault list. In the present application, whether redundant fault elimination is currently required is determined through system operation data, thereby increasing the success rate of dynamic streamlining in test generation, reducing the generated test vectors, and when the test vector is generated, all faults in the fault list are judged through a single fault test generator. When the selected main fault cannot generate a test cube, the main fault is eliminated. When the main fault can generate a test cube, a test cube is generated for the main fault, and a fault is randomly selected from the remaining faults in the fault list as a secondary fault. Bits are filled in the test cube through the secondary fault to generate a test vector, thereby solving the current test generation scheme. Since redundant faults are not eliminated, the system's ability to streamline vectors is low, resulting in long running time and a large number of test vectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 It is a flow chart provided by an embodiment of a test generation method for eliminating redundant faults of the present invention;

[0052] Figure 2 It is a structural schematic diagram provided by an embodiment of a test generation device for eliminating redundant faults of the present invention;

[0053] Figure 3 It is a structural schematic diagram provided by an embodiment of a test generation device for eliminating redundant faults of the present invention. DETAILED DESCRIPTION

[0054] To make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described in detail below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other implementation methods obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0055] Figure 1 This is a flow chart provided by an embodiment of a test generation method for eliminating redundant faults of the present invention. Figure 1 , this embodiment may include the following steps:

[0056] S1, obtain the netlist in Verilog format and parse the netlist through a netlist parser;

[0057] S2, analyzing the parsed netlist through a fault list analyzer to generate a fault list;

[0058] S3. Randomly select a fault from the fault list as the main fault, test the main fault through the single fault test generator, obtain system operation data, and determine whether the current system performs redundant fault elimination according to the system operation data;

[0059] S4. If yes, determine whether the main fault can generate a test cube;

[0060] S5. If yes, generate a test cube for the primary fault, and randomly select a fault from the remaining faults in the fault list as a secondary fault, fill bits for the test cube with the secondary fault, and generate a test vector;

[0061] S6. If not, eliminate the main fault and reselect the main fault in the fault list.

[0062] It can be understood that the present application first obtains a netlist in a Verilog format, and parses the netlist through a netlist parser, analyzes the parsed netlist through a fault list analyzer, generates a fault list, randomly selects a fault from the fault list as the main fault, and tests the main fault through a single fault test generator, and obtains system operation data, and determines whether the current system performs redundant fault elimination according to the system operation data. If so, it determines whether a test cube can be generated for the main fault. If so, a test cube is generated for the main fault, and randomly selects a fault from the remaining faults in the fault list as a secondary fault, fills bits for the test cube through the secondary fault, and generates a test vector. If not, the main fault is eliminated and the main fault is reselected in the fault list. In the present application, whether redundant fault elimination is currently required is determined through system operation data, thereby increasing the success rate of dynamic streamlining in test generation, reducing the generated test vectors, and when the test vector is generated, all faults in the fault list are judged through a single fault test generator. When the selected main fault cannot generate a test cube, the main fault is marked as a redundant fault and eliminated. When the main fault can generate a test cube, a test cube is generated for the main fault, and a fault is randomly selected from the remaining faults in the fault list as a secondary fault. Bits are filled in the test cube through the secondary fault to generate a test vector, thereby solving the current test generation scheme. Since redundant faults are not eliminated, the system's ability to streamline vectors is low, resulting in long running time and a large number of test vectors.

[0063] Preferably, obtaining system operation data and determining whether the current system is performing redundant fault troubleshooting according to the system operation data includes:

[0064] Obtain system operation data;

[0065] According to the system operation data, the remaining ATPG operation cost is calculated by the first formula, and the cost of performing redundancy identification at the current moment is calculated by the second formula;

[0066] Whether the current system performs redundant fault elimination is determined by determining whether the ratio of the remaining ATPG operation cost to the cost of performing redundant identification at the current moment exceeds a preset parameter.

[0067] Preferably, the first formula is:

[0068]

[0069] The second formula is:

[0070]

[0071] in, represents the remaining ATPG run cost, represents the cost of redundant identification at the current moment, It represents the average number of newly detected faults per test vector in the last simulation under the current state of the system. It indicates the average running time of each test vector ATPG in the last simulation under the current state of the system. It represents the average running time of all classified major faults in the current state of the system. Indicates the number of vectors for each simulation of the system;

[0072]

[0073] in, represents the proportion of major faults in the most recent set of tests on the system that were classified as testable and redundant; Indicates the total number of faults remaining.

[0074] It is understandable that the analysis of ATPG system operation data is used to find a reasonable time to perform global redundancy identification. Global redundancy identification is to use some methods, such as single fault test generation, Boolean satisfiability methods, redundancy analysis tools, etc. to identify as many redundant faults as possible among the currently unclassified faults. The analysis of operation data is to evaluate the cost function we defined, including estimating the remaining ATPG operation cost. and estimate the cost of redundant identification at the current time In the parameters of the ATPG system, we set a reduction intensity To control the start time of global redundancy identification, global redundancy identification is started when the following conditions are met:

[0075]

[0076] parameter The larger the value, the earlier the global redundancy identification is started, thus achieving a stronger vector reduction effect. However, in actual applications, it is necessary to set the parameters reasonably to balance the running time of the ATPG system and the vector reduction capability.

[0077] Preferably, S5 includes:

[0078] Generate test cubes for major faults through single fault test generator;

[0079] Randomly select a secondary fault for a primary fault in the fault list;

[0080] Determine whether a test can be generated for a minor fault using a single fault test generator;

[0081] If possible, fill bits into the test cube according to the test generated by the secondary fault to generate a test vector;

[0082] If not, reselect the secondary fault and increase the secondary fault failure count of the primary fault by one. After the secondary fault failure count reaches the preset number, abandon the primary fault and reselect a new primary fault.

[0083] It can be understood that the ATPG system reads the netlist in Verilog format from the outside, parses it and stores it in the internal structure. The fault list analyzer will analyze the read netlist to generate a simplified fault list. The ATPG system will randomly select a fault from the fault list as the main fault. The single fault test generator generates a test cube for the main fault. If the current test cube still has an uncertain bit X, then a secondary fault is randomly selected from the fault list. The single fault test generation will generate a test for the secondary fault under the constraints of the current test cube, that is, fill new bits for the test cube. If the secondary fault cannot successfully generate a test, the test cube will not change, and the secondary fault will be discarded. Whenever a secondary fault is discarded, the number of secondary fault failures will increase by 1. If it exceeds the given maximum number of secondary fault failures, it will stop filling bits for the current test cube. After a certain number of secondary fault test generation failures, it will stop, and the system will select another primary fault to generate a new test cube.

[0084] The success rate of minor fault test generation, that is, the probability of the test cube being filled with new bits, can reflect the degree of compression of the test vectors generated by the ATPG system, that is, the vector reduction capability of the ATPG system. This is because both major and minor faults are randomly selected to generate tests, so the vector reduction capability of the ATPG system can be improved by improving the success rate under a given maximum number of minor fault failures.

[0085] Preferably, the test generated according to the secondary fault is to fill bits in the test cube to generate a test vector, including:

[0086] Filling bits into the test cube according to the test generated by the minor fault, and determining whether there is an uncertain bit in the filled test cube;

[0087] If it exists, the uncertain bits are randomly filled and a complete test vector is generated.

[0088] Preferably, it also includes:

[0089] Get the number of generated test vectors;

[0090] When the number of test vectors exceeds a preset number, all test vectors are simulated by a fault simulator to determine the tested faults, and the tested faults are removed from the fault list.

[0091] It can be understood that after a single test cube is generated, if there are still X bits, then these X bits are randomly filled to generate a complete test vector, which will be saved. When a certain number of test vectors are generated, the fault simulator will simulate these test vectors. If the faults to be tested in the fault list can be detected by these test vectors, then the status of these faults to be tested is set to detected. When there are no more faults to be tried in the fault list, the system will report the number of all generated test vectors and the time of test generation.

[0092] Preferably, it also includes:

[0093] When there are no faults in the fault list to try, the number of test vectors generated and the generation time are reported.

[0094] In specific practice, the present application first analyzes the ATPG system operation data to find a reasonable time to perform global redundancy identification, that is, to determine the remaining ATPG operation cost by real-time analysis of the ATPG system operation data. and the cost of redundant identification at the current time ,exist When the netlist in Verilog format is read from the outside, it is parsed and stored in the internal structure. The fault list analyzer will analyze the read netlist to generate a simplified fault list, and then randomly select a fault in the fault list as the main fault, generate a test cube for the main fault through the single fault test generator, mark the fault that cannot generate the test cube as a redundant fault and exclude it. When there is an uncertain bit X in the test cube of the main fault, randomly select a fault in the fault list as a secondary fault, and generate a test for the secondary fault under the constraint of the current test cube through the single fault test generator, that is, fill the test cube with new bits. When the current secondary fault cannot fill the test cube, reselect the secondary fault for the main fault, and reselect the main fault when the main fault filling fails to reach a preset number of times. After the main fault is filled by the secondary fault, if there is still an uncertain bit X in the test cube, the uncertain bit X is randomly filled, and a test vector is generated after filling. When the generated test vectors reach the preset number, the fault simulator will simulate these test vectors. If the faults to be tested in the fault list can be detected by these test vectors, the status of these faults to be tested will be set to detected, and the remaining faults will continue to be detected until there are no more faults to be tried in the fault list. The system will report the number of all generated test vectors and the time of test generation.

[0095] The present invention also provides a test generation device for eliminating redundant faults, which is used to implement the above method embodiment. Figure 2FIG. 1 is a schematic diagram of a structure of an embodiment of a test generation device for eliminating redundant faults according to the present invention. Figure 2 As shown, including:

[0096] The fault list generation module 1 is used to obtain a netlist in a Verilog format, parse the netlist through a netlist parser, analyze the parsed netlist through a fault list analyzer, and generate a fault list;

[0097] Start judgment module 2, randomly select a fault from the fault list as the main fault, test the main fault through the single fault test generator, obtain system operation data, and judge whether the current system should perform redundant fault elimination according to the system operation data;

[0098] The test vector generation module 3 is used to determine whether a test cube can be generated for the main fault when redundant fault troubleshooting is required. If so, a test cube is generated for the main fault, and a fault is randomly selected from the remaining faults in the fault list as a secondary fault. Bits are filled in the test cube with the secondary fault to generate a test vector. If not, the main fault is eliminated and the main fault is reselected in the fault list.

[0099] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0100] The present invention also provides a test generation device for eliminating redundant faults, which is used to implement the above method embodiment. Figure 3 FIG. 1 is a schematic diagram of a structure of an embodiment of a test generation device for eliminating redundant faults according to the present invention. Figure 3 As shown, the test generation device for eliminating redundant faults in this embodiment includes a processor 21 and a memory 22, and the processor 21 is connected to the memory 22. The processor 21 is used to call and execute the program stored in the memory 22; the memory 22 is used to store the program, and the program is at least used to execute the test generation method for eliminating redundant faults in the above embodiment.

[0101] The specific implementation scheme of the test generation device for eliminating redundant faults provided in the embodiment of the present application can refer to the implementation scheme of the test generation method for eliminating redundant faults in any of the above embodiments, which will not be repeated here.

[0102] The present invention also provides a computer-readable medium having a non-volatile program code executable by a processor, wherein the program code enables the processor to execute any one of the test generation methods for eliminating redundant faults.

[0103] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0104] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0105] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present invention belong.

[0106] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0107] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0108] In addition, each functional unit in each embodiment of the present invention may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0109] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0110] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0111] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A test generation method for eliminating redundant faults, characterized in that: include: Obtain a netlist in Verilog format, and parse the netlist using a netlist parser; Analyze the parsed netlist by a fault list analyzer to generate a fault list; Randomly select a fault from the fault list as a main fault, test the main fault through a single fault test generator, obtain system operation data, and determine whether the current system performs redundant fault elimination according to the system operation data; If yes, determine whether the main fault can generate a test cube; If yes, a test cube is generated for the primary fault, and a fault is randomly selected from the remaining faults in the fault list as a secondary fault, and bits are filled for the test cube through the secondary fault to generate a test vector; If not, eliminate the main fault and reselect the main fault in the fault list; The obtaining of system operation data and judging whether the current system performs redundant fault elimination according to the system operation data include: obtaining system operation data; calculating the remaining ATPG operation cost according to the system operation data by a first formula, and calculating the cost of performing redundant identification at the current moment by a second formula; judging whether the current system performs redundant fault elimination according to whether the ratio of the remaining ATPG operation cost to the cost of performing redundant identification at the current moment exceeds a preset parameter; The first formula is: The second formula is: in, represents the remaining ATPG run cost, represents the cost of redundant identification at the current moment, It represents the average number of newly detected faults per test vector in the last simulation under the current state of the system. It indicates the average running time of each test vector ATPG in the last simulation under the current state of the system. It represents the average running time of all classified major faults in the current state of the system. Indicates the number of vectors for each simulation of the system; in, represents the proportion of major faults in the most recent set of tests on the system that were classified as testable and redundant; Indicates the total number of faults remaining.

2. The method according to claim 1, characterized in that Generating a test cube for the primary fault, and randomly selecting a fault from the remaining faults in the fault list as a secondary fault, filling bits for the test cube with the secondary fault, and generating a test vector, including: generating a test cube for the major fault by the single fault test generator; Randomly selecting a secondary fault for the primary fault in the fault list; Determining whether the secondary fault can generate a test by the single fault test generator; If yes, filling bits for the test cube according to the test generated by the secondary fault to generate a test vector; If not, a secondary fault is reselected, and the secondary fault failure count of the primary fault is increased by one. After the secondary fault failure count reaches a preset number, the primary fault is abandoned and a new primary fault is reselected.

3. The method according to claim 2, characterized in that The test generated according to the secondary fault is to fill bits in the test cube to generate a test vector, including: Filling bits for the test cube according to the test generated by the minor fault, and determining whether there is an uncertain bit in the filled test cube; If it exists, the uncertain bits are randomly filled and a complete test vector is generated.

4. The method according to claim 3, characterized in that Also includes: Obtaining the number of the generated test vectors; When the number of the test vectors exceeds a preset number, all the test vectors are simulated by a fault simulator to determine the tested faults, and the tested faults are removed from the fault list.

5. The method according to claim 4, characterized in that Also includes: When there is no fault that can be tried in the fault list, the number and generation time of the generated test vectors are reported.

6. A test generation device for eliminating redundant faults, applicable to the test generation method for eliminating redundant faults as claimed in any one of claims 1 to 5, characterized in that: include: A fault list generation module is used to obtain a netlist in a Verilog format, parse the netlist through a netlist parser, analyze the parsed netlist through a fault list analyzer, and generate a fault list; Starting the judgment module, randomly selecting a fault from the fault list as the main fault, testing the main fault through a single fault test generator, acquiring system operation data, and judging whether the current system performs redundant fault elimination according to the system operation data; A test vector generation module is used to determine whether a test cube can be generated for the main fault when redundant fault troubleshooting is required; if so, a test cube is generated for the main fault, and a fault is randomly selected from the remaining faults in the fault list as a secondary fault, bits are filled in the test cube through the secondary fault to generate a test vector; if not, the main fault is eliminated and a main fault is reselected in the fault list.

7. A test generation device for eliminating redundant faults, characterized in that: The invention comprises a processor and a memory, wherein the processor is connected to the memory: Wherein, the processor is used to call and execute the program stored in the memory; The memory is used to store the program, and the program is at least used to execute the test generation method for eliminating redundant faults as described in any one of claims 1-5.

8. A computer-readable storage medium having a non-volatile program code executable by a processor, characterized in that: The program code enables the processor to execute the test generation method for eliminating redundant faults as described in any one of claims 1-5.

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