ATPG dynamic test streamlining method, device, equipment and computer readable medium
By dynamically adjusting the failure penalty factor and priority, and optimizing the generation of ATPG test vectors, the problem of low adaptability of test streamlined methods in the prior art is solved, and the testing efficiency and fault positioning accuracy are improved.
Patent Information
- Application Number
- CN202411037331.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-31
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2044-07-31
AI Technical Summary
The existing ATPG dynamic testing streamlining methods rely highly on predefined static heuristic rules and cannot be flexibly adjusted based on specific circuit characteristics and feedback information during the dynamic streamlining process, resulting in low adaptability.
By initializing the failure penalty factor and test vector set of all potential secondary faults in the circuit, combining a priori heuristic rules to determine the comprehensive priority, dynamically adjust the failure penalty factor and test vector generation, iteratively optimize the test vector until the failure threshold is reached.
It improves the flexibility and adaptability of the testing streamlining process, reduces invalid attempts, improves testing efficiency and fault positioning accuracy, and reduces testing resources and costs.
Smart Images
Figure CN118566700B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testability design, and in particular to an ATPG dynamic test streamlining method, device, equipment and computer-readable medium. Background Art
[0002] With the increasing scale of chips, electronic design automation tools are indispensable in the field of chip design. In the actual chip generation process, defects are inevitable. In order to detect defects in chip manufacturing as early as possible, the testability design method has become an important process in chip design. Among them, the automatic test vector generation method generates test vectors for the chip to be tested in the design stage. After the chip is manufactured, it will be loaded on the automatic tester, and the previously generated vectors will be applied to the machine to detect defects in the chip. Test application time and test volume are important indicators for evaluating the quality of test vectors generated by ATPG. In order to generate high-quality test vectors and reduce test costs, many test-compact test vector generation methods have been proposed in recent years. In the test stage of chip design, automatic test vector generation (ATPG) is an important part, and its goal is to automatically generate high-quality test vectors that can detect chip defects. The original test vectors generated by ATPG usually contain a lot of redundancy, and test simplification is required to reduce test costs.
[0003] The existing technology mainly uses the method of dynamic test simplification to perform test simplification, incrementally generating test vectors by gradually introducing minor faults, and detecting new faults generated after the introduction of minor faults. However, since the minor faults are selected based on the existing test vectors, the selection strategy of the minor faults has an important impact on the simplification effect. When selecting minor faults, the existing methods usually design heuristic rules based on prior knowledge, such as selecting the most difficult faults to detect, weighted random selection based on fault characteristics, etc., which are highly dependent on predefined heuristic rules. These rules are usually static and fixed, and cannot be flexibly adjusted according to the characteristics of the specific circuit and the feedback information in the dynamic simplification process. They lack flexibility and adaptability.
[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention
[0005] The present application provides an ATPG dynamic test simplification method to solve the technical problem that the above-mentioned dynamic test simplification method is highly dependent on predefined static heuristic rules and cannot be flexibly adjusted according to the characteristics of the specific circuit and the feedback information in the dynamic simplification process, resulting in low adaptability.
[0006] According to one aspect of an embodiment of the present application, the present application provides an ATPG dynamic test streamlining method, including:
[0007] Initialize failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, wherein the failure penalty factor is the number of failures generated by the test vector;
[0008] Determine the comprehensive priority of each potential minor fault based on the failure penalty factor combined with a priori heuristic rules, and determine the current minor fault based on the comprehensive priority;
[0009] Generate a test vector corresponding to the current minor fault based on the ATPG algorithm, and determine the test vector generation result;
[0010] If the test vector is generated successfully, the generated test vector is added to the test vector set, and the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed;
[0011] If the test vector generation fails, the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed until the number of test vector generation failures reaches a failure number threshold.
[0012] Optionally, initializing the failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, including:
[0013] Determine potential minor faults based on the main fault set of the circuit, and construct a corresponding potential minor fault set;
[0014] Setting the corresponding failure penalty factors of all potential minor faults in the potential minor fault set to 0;
[0015] A corresponding initial test vector set is set based on the potential secondary fault set.
[0016] Optionally, determining a comprehensive priority of each potential minor fault based on the failure penalty factor in combination with a priori heuristic rules, and determining a current minor fault based on the comprehensive priority includes:
[0017] Based on the failure penalty factor combined with a priori heuristic rules, the comprehensive priority corresponding to each potential minor fault in the potential minor fault set is calculated. The calculation formula of the comprehensive priority is:
[0018] P = T × (1 / F );
[0019] Where: P Indicates comprehensive priority; T represents the measurability estimate; F represents the failure penalty factor;
[0020] Sorting each potential minor fault in the potential minor fault set based on the comprehensive priority from high to low to obtain a priority order;
[0021] The potential secondary fault with the highest comprehensive priority is selected as the current secondary fault based on the priority order.
[0022] Optionally, generating a test vector corresponding to the current minor fault based on an ATPG algorithm, and determining a result of generating the test vector, includes:
[0023] Perform fault state simulation according to the current minor fault to build a minor fault model;
[0024] Analyze the fault nodes in the secondary fault model based on the ATPG algorithm to generate an initial test vector;
[0025] Calculating the test coverage rate corresponding to the initial test vector, and determining whether the test coverage rate reaches a corresponding threshold, wherein the test coverage rate is the ratio of the number of actually detected faults to the total number of faults;
[0026] If the test coverage does not reach the preset coverage value, returning to the step of generating an initial test vector;
[0027] If the test coverage reaches a preset coverage value, updating the initial test vector set to obtain a final test vector;
[0028] A test vector generation result is determined based on the final test vector, where the test vector generation result includes a test vector generation success and a test vector generation failure.
[0029] Optionally, analyzing the faulty nodes in the secondary fault model based on an ATPG algorithm to generate an initial test vector includes:
[0030] Determine the fault node type corresponding to each potential secondary fault and the logic gates and paths before and after the fault node based on the secondary fault model;
[0031] Performing logic function simulation based on the fault node type combined with logic gates and paths before and after the fault node to determine potential secondary faults that can cause actual faults;
[0032] generating a first test vector corresponding to the potential secondary fault that can generate an actual fault;
[0033] The first test vector is loaded into the circuit model for verification, and the first test vector that passes the verification is used as an initial test vector.
[0034] Optionally, the generated test vector is added to the test vector set, the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed, including:
[0035] Add the generated test vector to the test vector set;
[0036] updating a failure penalty factor of a current minor fault based on the generated test vector;
[0037] The integrated priority is updated in combination with the failure penalty factor, the current minor fault is updated based on the updated integrated priority, and a test vector of the updated current minor fault is generated based on ATPG.
[0038] Optionally, updating the failure penalty factor of the current minor fault and iteratively performing the above steps until the number of test vector generation failures reaches a failure number threshold includes:
[0039] The failure penalty factor of the current minor fault is updated based on an iterative update formula, wherein the iterative update formula is:
[0040] ;
[0041] Where: represents the failure penalty factor; Indicates the upper limit of the failure penalty factor;
[0042] Set the failure threshold for test vector generation based on historical data;
[0043] The comprehensive priority is updated based on the updated failure penalty factor, and the test vector is further generated based on the updated comprehensive priority until the number of test vector generation failures reaches a failure number threshold, thereby obtaining a final test vector set.
[0044] According to another aspect of the embodiments of the present application, the present application provides a device, including:
[0045] An initialization module, used to initialize the failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, wherein the failure penalty factor is the number of failures generated by the test vector;
[0046] A minor fault determination module, used to determine the comprehensive priority of each potential minor fault based on a failure penalty factor combined with a priori heuristic rules, and determine the current minor fault based on the comprehensive priority;
[0047] A test vector generation module is used to generate a test vector corresponding to the current minor fault based on the ATPG algorithm and determine the test vector generation result;
[0048] A test vector generation success processing module is used to add the generated test vector to the test vector set when the test vector is generated successfully, update the failure penalty factor of the current minor fault, and iterate the above steps;
[0049] The test vector generation failure processing module is used to update the failure penalty factor of the current minor fault when the test vector generation fails, and iteratively execute the above steps until the number of test vector generation failures reaches the failure number threshold.
[0050] According to another aspect of an embodiment of the present application, the present application provides an electronic device, including a memory, a processor, a communication interface and a communication bus, wherein the memory stores a computer program that can be run on the processor, the memory and the processor communicate through the communication bus and the communication interface, and the steps of the above method are implemented when the processor executes the computer program.
[0051] According to another aspect of an embodiment of the present application, the present application also provides a computer-readable medium having a non-volatile program code executable by a processor, and the program code enables the processor to execute the above method.
[0052] The above technical solution provided by the embodiment of the present application has the following advantages compared with the related art:
[0053] The present application introduces a dynamically adjusted failure penalty factor and combines a priori heuristic rules to determine the comprehensive priority of potential minor faults, thereby solving the problem of lack of flexibility and adaptability of the test reduction method in the prior art. In the test vector generation process, the failure penalty factor of the current minor fault is dynamically adjusted according to the test vector generation result, and then the comprehensive priority of the current minor fault is updated, so that those minor faults that are more likely to successfully generate test vectors can be tried first in subsequent iterations. This dynamic adjustment strategy enables the test reduction process to better adapt to the characteristics of specific circuits and feedback information in the dynamic reduction process, thereby improving the flexibility and adaptability of test reduction. By dynamically adjusting the priority of potential minor faults, priority is given to faults that are more likely to successfully generate test vectors, thereby accelerating the test vector generation process, reducing invalid attempts, and improving test efficiency. The test vectors generated by the ATPG algorithm are combined with the test coverage evaluation to ensure that the generated test vectors can cover as many faults as possible, thereby improving the comprehensiveness and effectiveness of the test. By introducing a failure penalty factor and dynamically adjusting the factor based on the test vector generation results, the system can intelligently identify and prioritize faults that are easy to generate test vectors for, while reducing excessive attempts at faults that are difficult to generate test vectors. In an iterative manner, the strategy is automatically adjusted when test vector generation fails and attempts are continued until the preset failure threshold is reached. This adaptive mechanism enhances the robustness and flexibility of the system. By streamlining the test vector set, unnecessary test vectors are removed, thereby reducing the resources and costs required for testing. Prioritizing faults with high comprehensive priority helps to discover and locate key problems in the circuit earlier, improving the accuracy and timeliness of fault location. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0056] Figure 1 A schematic diagram of a hardware environment of an ATPG dynamic test streamlining method provided according to an embodiment of the present application;
[0057] Figure 2 A schematic diagram of a flow chart of an ATPG dynamic test streamlining method provided according to an embodiment of the present application;
[0058] Figure 3 A schematic block diagram of the structure of an ATPG dynamic test streamlining device provided according to an embodiment of the present application;
[0059] Figure 4 A schematic diagram of an optional electronic device structure provided in an embodiment of the present application. DETAILED DESCRIPTION
[0060] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0061] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application and have no specific meaning. Therefore, "module" and "component" can be used interchangeably.
[0062] In the related art, in the test reduction process after automatic test vector generation, the selection of secondary faults mainly relies on static and fixed heuristic rules, and lacks the ability to flexibly adjust according to specific circuit characteristics and dynamic reduction process feedback, resulting in insufficient flexibility and adaptability of test reduction.
[0063] In order to solve the problem mentioned in the background technology, according to one aspect of an embodiment of the present application, an embodiment of an ATPG dynamic test streamlining method is provided.
[0064] Optionally, in the embodiment of the present application, the above method can be applied to Figure 1 In the hardware environment composed of the terminal 101 and the server 103 shown in FIG. Figure 1 As shown, the server 103 is connected to the terminal 101 via a network, and can be used to provide services for the terminal or a client installed on the terminal. A database 105 can be set on the server or independently of the server to provide data storage services for the server 103. The above-mentioned network includes but is not limited to: a wide area network, a metropolitan area network or a local area network, and the terminal 101 includes but is not limited to a PC, a mobile phone, a tablet computer, etc.
[0065] A method in the embodiment of the present application can be executed by the server 103, or can be executed by the server 103 and the terminal 101 together, such as Figure 2 As shown, the method may include the following steps:
[0066] S201, initializing failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, wherein the failure penalty factor is the number of failures generated by the test vector.
[0067] Specifically, the failure penalty factor is the number of failures of test vector generation.
[0068] Specifically, S201 includes:
[0069] Determine potential minor faults based on the main fault set of the circuit, and construct a corresponding potential minor fault set;
[0070] Setting the corresponding failure penalty factors of all potential minor faults in the potential minor fault set to 0;
[0071] The corresponding initial test vector set is set based on the potential minor fault set.
[0072] In the above specific implementation, the main fault set of the circuit is first obtained, and based on the main fault set, potential minor faults that may be caused by these main faults are identified, and the minor faults include, for example, signal delays, logic errors, or circuit performance degradation caused by the main faults. All the identified potential minor faults are sorted into a set, and each fault has a unique identifier in the set. For each fault in the potential minor fault set, the corresponding failure penalty factor is initialized to 0, indicating that before the test vector is generated, there is no attempt to fail to generate any test vector. For each potential minor fault, an empty test vector set corresponding to it is created. This set will be used to store the test vectors generated for the fault in the future. For example, the potential minor fault set of this embodiment includes three potential minor faults, and the corresponding identifiers are Fault1, Fault2, and Fault3, respectively, and the failure penalty factors corresponding to the potential minor faults Fault1, Fault2, and Fault3 are all 0.
[0073] S202, determining the comprehensive priority of each potential minor fault based on the failure penalty factor combined with a priori heuristic rules, and determining the current minor fault based on the comprehensive priority.
[0074] Specifically, S202 includes:
[0075] Based on the failure penalty factor combined with the prior heuristic rule, the comprehensive priority corresponding to each potential minor fault in the potential minor fault set is calculated. The calculation formula of the comprehensive priority is:
[0076] P = T × (1 / F );
[0077] Where: P Indicates comprehensive priority;T represents the measurability estimate; F represents the failure penalty factor;
[0078] Sorting each potential minor fault in the potential minor fault set in descending order of comprehensive priority to obtain a priority order;
[0079] The potential secondary fault with the highest comprehensive priority is selected as the current secondary fault based on the priority order.
[0080] In the above specific implementation, it is assumed that the potential minor fault Fault1 is located in a circuit area that is easy to detect, and its testability estimation value is set to T1=10; Fault2 is located in a circuit area that is difficult to detect, and its testability estimation value is set to T2=5; Fault3 is uncommon but easy to detect, and its testability estimation value is set to T3=8. Because the failure penalty factors corresponding to the potential minor faults Fault1, Fault2, and Fault3 are all 0, the testability evaluation value is directly used. T To determine the comprehensive priority of potential minor faults Fault1, Fault2 and Fault3, the potential minor fault Fault1 has the highest comprehensive priority, followed by the potential minor fault Fault3, and the lowest is the potential minor fault Fault2, so the priority order is [Fault1, Fault3, Fault2]. The potential minor fault Fault1 with the highest comprehensive priority is taken as the current minor fault.
[0081] S203, generating a test vector corresponding to the current minor fault based on the ATPG algorithm, and determining a test vector generation result.
[0082] Specifically, S203 includes:
[0083] Conduct fault state simulation according to the current minor fault to build a minor fault model;
[0084] Analyze the fault nodes in the minor fault model based on the ATPG algorithm and generate initial test vectors;
[0085] Calculate the test coverage corresponding to the initial test vector and determine whether the test coverage reaches the corresponding threshold, where the test coverage is the ratio of the actual number of detected faults to the total number of faults;
[0086] If the test coverage does not reach the preset coverage value, return to the step of generating the initial test vector;
[0087] If the test coverage reaches the preset coverage value, the initial test vector set is updated to obtain the final test vector;
[0088] A test vector generation result is determined based on the final test vector, and the test vector generation result includes a test vector generation success and a test vector generation failure.
[0089] In the above specific implementation, the selected current minor fault is first analyzed to determine the current minor fault characteristics. According to the current minor fault characteristics, a fault model is constructed using a fault simulation tool. In the model, the fault node is set to a fault state to simulate the circuit behavior when the fault occurs. The ATPG algorithm is used to analyze the fault node in the minor fault model, and the test vector that can activate and detect the fault is automatically searched, and the initial test vector is generated according to the search results. The test coverage corresponding to the initial test vector is calculated. The test coverage is the ratio of the actual number of detected faults to the total number of faults. The calculated test coverage is compared with the preset coverage threshold. If the test coverage reaches the preset coverage value, the initial test vector set is updated, and the test vector that meets the conditions is used as the final test vector set. The test vector generation result is determined based on the final test vector set. If the final test vector can successfully detect the current minor fault, the test vector generation is successful; if the fault cannot be detected or there are other problems, the test vector generation fails.
[0090] Specifically, the fault nodes in the secondary fault model are analyzed based on the ATPG algorithm to generate initial test vectors, including:
[0091] Determine the fault node type corresponding to each potential secondary fault, and the logic gates and paths before and after the fault node based on the secondary fault model;
[0092] Perform logic function simulation based on the fault node type and the logic gates and paths before and after the fault node to determine potential secondary faults that can cause actual faults;
[0093] generating a first test vector corresponding to a potential secondary fault capable of generating an actual fault;
[0094] The first test vector is loaded into the circuit model for verification, and the first test vector that passes the verification is used as an initial test vector.
[0095] In the above specific implementation, the minor fault model is first analyzed to identify all potential minor fault nodes, where the fault nodes include, for example, a certain element (such as a transistor, a gate circuit, etc.) or a connection point in the circuit. Assuming that the fault node is a gate circuit in the circuit, for each potential minor fault, the corresponding fault node type is determined, and the fault node type includes, for example, open circuit, short circuit, fixed fault (such as fixed to 0 or 1), delay fault, etc. For each fault node, the logic gates before and after it and the paths between them are analyzed, including determining the flow direction of the signal, the type of logic gate (such as AND gate, OR gate, NOT gate, etc.) and the connection mode between each logic gate. Based on the fault node type and the logic gates and paths before and after it, a logic function simulation is performed to predict potential minor faults that can produce observable fault phenomena in the actual circuit, and through the logic function simulation, potential minor faults that can produce actual faults are screened out. For each potential minor fault that can produce an actual fault, the ATPG algorithm is used to generate a first test vector, and the ATPG algorithm automatically searches for a test vector that can activate and detect the fault according to the characteristics of the fault node and the constraints of the logic gates and paths. The generated first test vector is loaded into the circuit model for verification, and the behavior of the circuit under the test vector is simulated by simulation software. The output of the circuit model under the test vector is observed to verify whether the test vector can be correctly activated and detect potential minor faults, and all the verified initial test vectors are organized into an initial test vector set.
[0096] S204, if the test vector is generated successfully, the generated test vector is added to the test vector set, and the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed.
[0097] Specifically, the generated test vector is added to the test vector set, the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed, including:
[0098] Add the generated test vector to the test vector set;
[0099] updating a failure penalty factor of the current minor fault based on the generated test vector;
[0100] The synthesis priority is updated in combination with the failure penalty factor, the current minor fault is updated based on the updated synthesis priority, and a test vector of the updated current minor fault is generated based on ATPG.
[0101] In the above specific implementation, the generated test vector is first added to the test vector set, and the detection difficulty of the current minor fault is evaluated according to the actual test result of the test vector. Based on the evaluation result, the failure penalty factor F of the current minor fault is updated. If the fault is difficult to detect or has a significant impact on the circuit function, its failure penalty factor is increased; conversely, if the fault is easy to detect or has a small impact on the circuit function, its failure penalty factor is reduced. Combined with the failure penalty factor F of the current minor fault, the comprehensive priority is calculated, and according to the comprehensive priority, the next minor fault to be processed is selected as the current minor fault, and S201 to S204 are iteratively executed based on the updated current minor fault.
[0102] S205, if the test vector generation fails, the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed until the number of test vector generation failures reaches a failure number threshold.
[0103] Specifically, the failure penalty factor of the current minor fault is updated, and S201 to S205 are iterated until the number of test vector generation failures reaches the failure number threshold, including:
[0104] The failure penalty factor of the current minor fault is updated based on the iterative update formula. The iterative update formula is:
[0105] ;
[0106] Where: represents the failure penalty factor; Indicates the upper limit of the failure penalty factor;
[0107] Set the failure threshold for test vector generation based on historical data;
[0108] The comprehensive priority is updated based on the updated failure penalty factor, and the test vector is further generated based on the updated comprehensive priority until the number of test vector generation failures reaches a failure number threshold, thereby obtaining a final test vector set.
[0109] In the above specific implementation, the upper limit of the failure penalty factor is first set, and the failure penalty factor determines the maximum growth range of the failure penalty factor. Then, a threshold value of the number of test vector generation failures is set based on history. When the number of test vector generation failures reaches this threshold, the iteration process will stop. During the iteration process, the failure penalty factor is updated once according to the number of failures, and then S201 to S205 are iteratively executed until the number of test vector generation failures reaches the failure threshold, and the final test vector is obtained.
[0110] According to another aspect of the embodiment of the present application, Figure 3 As shown, an ATPG dynamic test simplified device is provided, including:
[0111] Initialization module 301, used to initialize failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, wherein the failure penalty factor is the number of failures generated by the test vector;
[0112] A minor fault determination module 302, configured to determine the comprehensive priority of each potential minor fault based on the failure penalty factor combined with a priori heuristic rules, and determine the current minor fault based on the comprehensive priority;
[0113] A test vector generation module 303 is used to generate a test vector corresponding to the current minor fault based on the ATPG algorithm and determine the test vector generation result;
[0114] The test vector generation success processing module 304 is used to add the generated test vector to the test vector set if the test vector is generated successfully, update the failure penalty factor of the current minor fault, and iterate the above steps;
[0115] The test vector generation failure processing module 305 is used to update the failure penalty factor of the current minor fault when the test vector generation fails, and iteratively execute the above steps until the number of test vector generation failures reaches the failure number threshold.
[0116] It should be noted that the initialization module 301 in this embodiment can be used to execute step S201 in the embodiment of the present application, the secondary fault determination module 302 in this embodiment can be used to execute step S202 in the embodiment of the present application, the test vector generation module 303 in this embodiment can be used to execute step S203 in the embodiment of the present application, the test vector generation success processing module 304 in this embodiment can be used to execute step S204 in the embodiment of the present application, and the test vector generation failure processing module 305 in this embodiment can be used to execute step S205 in the embodiment of the present application.
[0117] It should be noted that the examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments. It should be noted that the above modules as part of the device can be run in Figure 1 In the hardware environment shown, it can be implemented by software or by hardware.
[0118] According to another aspect of the embodiments of the present application, the present application provides an electronic device, such as Figure 4As shown, it includes a memory 401, a processor 403, a communication interface 405 and a communication bus 407. The memory 401 stores a computer program that can be run on the processor 403. The memory 401 and the processor 403 communicate through the communication interface 405 and the communication bus 407. When the processor 403 executes the computer program, the steps of the above method are implemented.
[0119] The memory and processor in the above electronic device communicate through the communication bus and the communication interface. The communication bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus can be divided into an address bus, a data bus, a control bus, etc.
[0120] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.
[0121] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
[0122] According to another aspect of the embodiments of the present application, a computer program product or a computer program is provided, the computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of any of the above embodiments.
[0123] Optionally, in an embodiment of the present application, the computer-readable medium is configured to store program codes for the processor to execute the following steps:
[0124] S201, initializing failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, wherein the failure penalty factor is the number of failures generated by the test vector.
[0125] S202, determining the comprehensive priority of each potential minor fault based on the failure penalty factor combined with a priori heuristic rules, and determining the current minor fault based on the comprehensive priority.
[0126] S203, generating a test vector corresponding to the current minor fault based on the ATPG algorithm, and determining a test vector generation result.
[0127] S204, if the test vector is generated successfully, the generated test vector is added to the test vector set, and the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed.
[0128] S205, if the test vector generation fails, the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed until the number of test vector generation failures reaches a failure number threshold.
[0129] Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments, and this embodiment will not be described in detail here.
[0130] When the embodiments of the present application are specifically implemented, reference may be made to the above-mentioned embodiments, which have corresponding technical effects.
[0131] It is understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit may be implemented in one or more application specific integrated circuits (ASIC), digital signal processors (DSP), digital signal processing devices (DSPD), programmable logic devices (PLD), field programmable gate arrays (FPGA), general purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions of the present application, or a combination thereof.
[0132] For software implementation, the technology of this article can be implemented by a unit that performs the functions of this article. The software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.
[0133] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0134] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0135] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.
[0136] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0137] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0138] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk. It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such a process, method, article or device. Without more constraints, an element defined by the phrase "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.
[0139] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.
Claims
1. An ATPG dynamic test streamlining method, characterized in that: include: Initialize failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, wherein the failure penalty factor is the number of failures generated by the test vector; Determine the comprehensive priority of each potential minor fault based on the failure penalty factor combined with a priori heuristic rules, and determine the current minor fault based on the comprehensive priority; Generate a test vector corresponding to the current minor fault based on the ATPG algorithm, and determine the test vector generation result; If the test vector is generated successfully, the generated test vector is added to the test vector set, and the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed; If the test vector generation fails, the failure penalty factor of the current minor fault is updated, and the above steps are iteratively performed until the number of test vector generation failures reaches a failure number threshold; The updating of the failure penalty factor of the current minor fault and iteratively performing the above steps until the number of test vector generation failures reaches a failure number threshold comprises: The failure penalty factor of the current minor fault is updated based on an iterative update formula, wherein the iterative update formula is: ； Where: represents the failure penalty factor; Indicates the upper limit of the failure penalty factor; Set the failure threshold for test vector generation based on historical data; The comprehensive priority is updated based on the updated failure penalty factor, and the test vector is further generated based on the updated comprehensive priority until the number of test vector generation failures reaches a failure number threshold, thereby obtaining a final test vector set.
2. The ATPG dynamic test streamlining method according to claim 1, characterized in that: Initialize the failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, including: Determine potential minor faults based on the main fault set of the circuit, and construct a corresponding potential minor fault set; Setting the corresponding failure penalty factors of all potential minor faults in the potential minor fault set to 0; A corresponding initial test vector set is set based on the potential secondary fault set.
3. The ATPG dynamic test streamlining method according to claim 1, characterized in that: Determining the comprehensive priority of each potential minor fault based on the failure penalty factor combined with a priori heuristic rules, and determining the current minor fault based on the comprehensive priority, including: Based on the failure penalty factor combined with a priori heuristic rules, the comprehensive priority corresponding to each potential minor fault in the potential minor fault set is calculated. The calculation formula of the comprehensive priority is: P = T × (1 / F )； Where: P Indicates comprehensive priority; T represents the measurability estimate; F represents the failure penalty factor; Sorting each potential minor fault in the potential minor fault set based on the comprehensive priority from high to low to obtain a priority order; The potential secondary fault with the highest comprehensive priority is selected as the current secondary fault based on the priority order.
4. The ATPG dynamic test streamlining method according to claim 1, characterized in that: Generating a test vector corresponding to the current minor fault based on the ATPG algorithm, and determining a result of generating the test vector, including: Perform fault state simulation according to the current minor fault to build a minor fault model; Analyze the fault nodes in the secondary fault model based on the ATPG algorithm to generate an initial test vector; Calculating the test coverage rate corresponding to the initial test vector, and determining whether the test coverage rate reaches a corresponding threshold, wherein the test coverage rate is the ratio of the number of actually detected faults to the total number of faults; If the test coverage does not reach the preset coverage value, return to the step of generating an initial test vector; If the test coverage reaches a preset coverage value, updating the initial test vector set to obtain a final test vector; A test vector generation result is determined based on the final test vector, where the test vector generation result includes a test vector generation success and a test vector generation failure.
5. The ATPG dynamic test streamlining method according to claim 4, characterized in that: Analyze the fault nodes in the secondary fault model based on the ATPG algorithm to generate an initial test vector, including: Determine the fault node type corresponding to each potential secondary fault and the logic gates and paths before and after the fault node based on the secondary fault model; Performing logic function simulation based on the fault node type combined with logic gates and paths before and after the fault node to determine potential secondary faults that can cause actual faults; generating a first test vector corresponding to the potential secondary fault that can generate an actual fault; The first test vector is loaded into the circuit model for verification, and the first test vector that passes the verification is used as an initial test vector.
6. The ATPG dynamic test streamlining method according to claim 1, characterized in that: Add the generated test vector to the test vector set, update the failure penalty factor of the current minor fault, and iterate the above steps, including: Add the generated test vector to the test vector set; updating a failure penalty factor of a current minor fault based on the generated test vector; The integrated priority is updated in combination with the failure penalty factor, the current minor fault is updated based on the updated integrated priority, and a test vector of the updated current minor fault is generated based on ATPG.
7. An ATPG dynamic test simplification device, applicable to the ATPG dynamic test simplification method according to any one of claims 1 to 6, characterized in that: include: An initialization module, used to initialize the failure penalty factors and test vector sets corresponding to all potential minor faults in the circuit, wherein the failure penalty factor is the number of failures generated by the test vector; A minor fault determination module, used to determine the comprehensive priority of each potential minor fault based on a failure penalty factor combined with a priori heuristic rules, and determine the current minor fault based on the comprehensive priority; A test vector generation module is used to generate a test vector corresponding to the current minor fault based on the ATPG algorithm and determine the test vector generation result; A test vector generation success processing module is used to add the generated test vector to the test vector set when the test vector is successfully generated, update the failure penalty factor of the current minor fault, and iterate the above steps; The test vector generation failure processing module is used to update the failure penalty factor of the current minor fault when the test vector generation fails, and iteratively execute the above steps until the number of test vector generation failures reaches the failure number threshold.
8. An electronic device, comprising a memory, a processor, a communication interface and a communication bus, wherein the memory stores a computer program that can be run on the processor, and the memory and the processor communicate through the communication bus and the communication interface, characterized in that: When the processor executes the computer program, the ATPG dynamic test streamlining method according to any one of claims 1 to 6 is implemented.
9. A computer-readable medium having a non-volatile program code executable by a processor, characterized in that: The program code enables the processor to execute the ATPG dynamic test reduction method according to any one of claims 1 to 6.