A method, device and electronic device for determining defects in a failed chip

Abstract

The embodiments of the present application disclose a method, device and electronic device for determining defects in a failed chip, which relates to the technical field of integrated circuit failure analysis and is invented to improve the efficiency of determining defects in failed chips. The method comprises: obtaining a current image diagram of a suspected signal path of a failed chip; wherein the current image diagram includes current images of suspected signal paths in at least two metal layers of the failed chip; correcting the current image diagram of the suspected signal path of the failed chip to obtain a corrected current image diagram of the suspected signal path of the failed chip; wherein the recognition of the corrected current image diagram is higher than the recognition of the current image diagram before correction; comparing the corrected current image diagram of the suspected signal path of the failed chip with the signal path design layout of the failed chip to determine the defect corresponding to the suspected signal path of the failed chip. The present application is applicable to occasions for determining defects in failed chips.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit failure analysis, and in particular to a method, device, electronic device and readable storage medium for determining defects in a failed chip. Background Art

[0002] Defect detection for failed chips usually requires physical failure analysis (PFA) after electrical failure analysis such as EFA SCAN (Electrical Failure Analysis SCAN) diagnosis. In recent years, the emergence of a test scheme that uses electron beams to irradiate failed chips and obtain current image diagrams has provided a more direct means to help further narrow the defect location. However, in the current image diagram obtained by this test scheme, the effect of each metal layer is not clear enough, and further, the efficiency is low when determining whether there is a defect. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a method, device, electronic device and readable storage medium for determining defects in a failed chip, so as to improve the efficiency of determining defects in a failed chip.

[0004] In a first aspect, an embodiment of the present application provides a method for determining defects in a failed chip, comprising: obtaining a current image diagram of a suspected signal path of a failed chip; wherein the current image diagram includes current images of suspected signal paths in at least two metal layers in the failed chip; correcting the current image diagram of the suspected signal path of the failed chip to obtain a corrected current image diagram of the suspected signal path of the failed chip; wherein the recognition of the corrected current image diagram is higher than the recognition of the current image diagram before correction; comparing the corrected current image diagram of the suspected signal path of the failed chip with the signal path design layout of the failed chip to determine the defect corresponding to the suspected signal path of the failed chip.

[0005] According to a specific implementation method of an embodiment of the present application, the current image diagram of the suspicious signal path of the failed chip is corrected to obtain a corrected current image diagram of the suspicious signal path of the failed chip, including: determining the pixel attribute value of the current image of the suspicious signal path of each metal layer in the at least two metal layers based on the current image of the suspicious signal path in at least two metal layers in the failed chip; determining the pixel attribute value interval to which the pixel attribute value of the current image of the suspicious signal path of each metal layer belongs; wherein different pixel attribute value intervals correspond to different path states of the suspicious signal path; determining the path state of the suspicious signal path in each metal layer according to the pixel attribute value interval to which the pixel attribute value of the current image of the suspicious signal path of each metal layer belongs; based on the path state of the suspicious signal path in each metal layer, correcting the pixel attribute value of the current image of the suspicious signal path in at least one of the metal layers to a target pixel attribute value to obtain a corrected current image diagram of the suspicious signal path of the failed chip.

[0006] According to a specific implementation method of an embodiment of the present application, at least two metal layers in the failed chip include a first metal layer and a second metal layer; wherein, based on the path state of the suspicious signal path in the metal layers, the pixel attribute value of the current image of the suspicious signal path in at least one of the metal layers is corrected to a target pixel attribute value, including: based on the path state of the suspicious signal path in the first metal layer, the pixel attribute value of the current image of the suspicious signal path in the first metal layer is corrected to a target pixel attribute value; and / or, based on the path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to a target pixel attribute value.

[0007] According to a specific implementation method of an embodiment of the present application, the pixel attribute value of the current image of the suspicious signal path in the first metal layer is corrected to a target pixel attribute value based on the path state of the suspicious signal path in the first metal layer, including: based on the first path state of the suspicious signal path in the first metal layer, the pixel attribute value of the current image of the suspicious signal path in the first metal layer is corrected to a first target pixel attribute value; or, based on the second path state of the suspicious signal path in the first metal layer, the pixel attribute value of the current image of the suspicious signal path in the first metal layer is corrected to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

[0008] According to a specific implementation method of an embodiment of the present application, based on the path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to the target pixel attribute value, including: based on the first path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to the first target pixel attribute value; or, based on the second path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to the second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

[0009] According to a specific implementation manner of an embodiment of the present application, before determining the pixel attribute value intervals to which the pixel attribute values ​​of the current images of the suspicious signal paths of the respective metal layers belong, the method further includes: determining a first path state and a second path state of a signal path in the same metal layer in a reference chip, determining the pixel attribute value of the current image of the first path state of the signal path in the same metal layer, and the pixel attribute value of the current image of the second path state of the signal path in the same metal layer; wherein the reference chip and the failed chip are different chips produced under the same process; based on the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state, according to a preset partitioning rule, dividing the pixel attribute value interval between the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state into two or more pixel attribute value intervals.

[0010] According to a specific implementation method of an embodiment of the present application, the corrected current image diagram of the suspected signal path of the failed chip is compared with the signal path design layout of the failed chip to determine the defect corresponding to the suspected signal path of the failed chip, including: extracting image features of the corrected current image diagram of the suspected signal path of the failed chip through image recognition; comparing the image features of the corrected current image diagram of the suspected signal path with the image features of the suspected signal path design layout; and determining whether there is a defect in the failed chip based on the comparison operation.

[0011] According to a specific implementation method of an embodiment of the present application, the extracting of image features of the corrected current image diagram of the suspected signal path of the failed chip through image recognition includes: extracting the contour line or central axis of the corrected current image diagram of the suspected signal path of the failed chip through image recognition; wherein, the comparing operation of the image features of the corrected current image diagram of the suspected signal path with the image features of the design layout of the suspected signal path includes: comparing the contour line of the corrected current image diagram of the suspected signal path with the contour line of the design layout of the suspected signal path; or, comparing the central axis of the corrected current image diagram of the suspected signal path with the central axis of the design layout of the suspected signal path.

[0012] According to a specific implementation method of an embodiment of the present application, the image features of the corrected current image diagram of the suspicious signal path are compared with the image features of the design layout of the suspicious signal path, including: performing an XOR operation on the pixel attribute value of each pixel point of the image features of the corrected current image diagram of the suspicious signal path and the pixel attribute value of each pixel point of the image features of the design layout of the suspicious signal path.

[0013] According to a specific implementation method of an embodiment of the present application, the current image of the suspicious signal path of the failed chip is a grayscale image; the pixel attribute value is the grayscale value of the pixel point; the target pixel attribute value is a target grayscale value, or a target color value other than black, white and gray.

[0014] According to a specific implementation of the embodiment of the present application, the path state includes an on state and at least one of the following three states: a low resistance state, a high resistance state, and an off state.

[0015] In a second aspect, an embodiment of the present application provides a device for determining defects in a failed chip, comprising: an acquisition module, used to acquire a current image diagram of a suspected signal path of a failed chip; wherein the current image diagram includes current images of suspected signal paths in at least two metal layers in the failed chip; a correction module, used to correct the current image diagram of the suspected signal path of the failed chip to obtain a corrected current image diagram of the suspected signal path of the failed chip; wherein the recognition of the corrected current image diagram is higher than the recognition of the current image diagram before correction; a comparison module, used to compare the corrected current image diagram of the suspected signal path of the failed chip with the signal path design layout of the failed chip to determine the defect corresponding to the suspected signal path of the failed chip.

[0016] According to a specific implementation method of an embodiment of the present application, the correction module includes: a first determination submodule, which is used to determine the pixel attribute value of the current image of the suspicious signal path of each metal layer in the at least two metal layers in the failed chip based on the current image of the suspicious signal path in at least two metal layers; a second determination submodule, which is used to determine the pixel attribute value interval to which the pixel attribute value of the current image of the suspicious signal path of each metal layer belongs; wherein different pixel attribute value intervals correspond to different path states of the suspicious signal path; a third determination submodule, which is used to determine the path state of the suspicious signal path in each metal layer according to the pixel attribute value interval to which the pixel attribute value of the current image of the suspicious signal path of each metal layer belongs; and a correction submodule, which is used to correct the pixel attribute value of the current image of the suspicious signal path in at least one of the metal layers to a target pixel attribute value based on the path state of the suspicious signal path in each metal layer, so as to obtain a corrected current image diagram of the suspicious signal path of the failed chip.

[0017] According to a specific implementation method of an embodiment of the present application, at least two metal layers in the failed chip include a first metal layer and a second metal layer; wherein the correction submodule includes: a first correction unit, used to correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a target pixel attribute value based on the path state of the suspicious signal path in the first metal layer; and / or, a second correction unit, used to correct the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a target pixel attribute value based on the path state of the suspicious signal path in the second metal layer.

[0018] According to a specific implementation method of an embodiment of the present application, the first correction unit is specifically used to: based on a first path state of the suspicious signal path in the first metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a first target pixel attribute value; or, based on a second path state of the suspicious signal path in the first metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

[0019] According to a specific implementation method of an embodiment of the present application, the second correction unit is specifically used to: based on the first path state of the suspicious signal path in the second metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a first target pixel attribute value; or, based on the second path state of the suspicious signal path in the second metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

[0020] According to a specific implementation method of an embodiment of the present application, the device is also used to: determine the first path state and the second path state of the signal path in the same metal layer in the reference chip before the second determination submodule determines the pixel attribute value interval to which the pixel attribute values ​​of the current image of the suspicious signal path of each metal layer respectively belong, determine the pixel attribute value of the current image of the first path state of the signal path in the same metal layer, and determine the pixel attribute value of the current image of the second path state of the signal path in the same metal layer; wherein the reference chip and the failed chip are different chips produced under the same process; based on the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state, according to a preset partitioning rule, divide the pixel attribute value interval between the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state into two or more pixel attribute value intervals.

[0021] According to a specific implementation method of an embodiment of the present application, the comparison module includes: an extraction submodule, used to extract image features of the corrected current image diagram of the suspected signal path of the failed chip through image recognition; a comparison submodule, used to compare the image features of the corrected current image diagram of the suspected signal path with the image features of the suspected signal path design layout; and a determination submodule, used to determine whether there is a defect in the failed chip based on the comparison operation.

[0022] According to a specific implementation method of an embodiment of the present application, the extraction submodule is specifically used to: extract the contour line or central axis of the corrected current image diagram of the suspected signal path of the failed chip through image recognition; wherein the comparison submodule is specifically used to: compare the contour line of the corrected current image diagram of the suspected signal path with the contour line of the design layout of the suspected signal path; or, compare the central axis of the corrected current image diagram of the suspected signal path with the central axis of the design layout of the suspected signal path.

[0023] According to a specific implementation method of an embodiment of the present application, the comparison submodule is specifically used to: perform an XOR operation on the pixel attribute value of each pixel point of the image feature of the corrected current image diagram of the suspicious signal path and the pixel attribute value of each pixel point of the image feature of the design layout of the suspicious signal path.

[0024] According to a specific implementation method of an embodiment of the present application, the current image of the suspicious signal path of the failed chip is a grayscale image; the pixel attribute value is the grayscale value of the pixel point; the target pixel attribute value is a target grayscale value, or a target color value other than black, white and gray.

[0025] According to a specific implementation of the embodiment of the present application, the path state includes an on state and at least one of the following three states: a low resistance state, a high resistance state, and an off state.

[0026] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the method for determining defects in a failed chip described in any of the aforementioned implementation methods.

[0027] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for determining defects in a failed chip as described in any of the aforementioned implementation methods.

[0028] The method, device, electronic device and readable storage medium for determining defects in a failed chip of the present embodiment correct the current image diagram of the suspected signal path of the failed chip to obtain the corrected current image diagram of the suspected signal path of the failed chip, and the corrected current image diagram has a higher recognition than the current image diagram before correction. The corrected current image diagram with higher recognition is compared with the signal path design layout of the failed chip to determine the defect corresponding to the suspected signal path of the failed chip. Since the recognition of the corrected current image diagram is higher than that of the current image diagram before correction, the defect with higher recognition can be identified more quickly. In this way, based on the corrected current image diagram with higher recognition, the defect corresponding to the suspected signal path of the failed chip can be determined more quickly, that is, the efficiency of determining the defect corresponding to the suspected signal path of the failed chip is improved. . BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A schematic diagram of a flow chart of a method for determining defects in a failed chip provided in an embodiment of the present application;

[0031] Figure 2 A current image diagram before correction provided by a specific embodiment of the present application;

[0032] Figure 3 A corrected current image diagram provided by a specific embodiment of the present application;

[0033] Figure 4 A schematic diagram of comparing the contour line of the suspicious signal path design layout and the contour line of the corrected current image diagram of the suspicious signal path provided by a specific embodiment of the present application;

[0034] Figure 5 A schematic diagram of comparing the contour line of the suspicious signal path design layout and the contour line of the corrected current image diagram of the suspicious signal path provided by another specific embodiment of the present application;

[0035] Figure 6 A schematic diagram of comparing the central axis of a suspicious signal path design layout provided by a specific embodiment of the present application with the central axis of a corrected current image diagram of the suspicious signal path;

[0036] Figure 7 A schematic diagram of a comparison operation between a central axis of a suspicious signal path design layout and a central axis of a corrected current image diagram of the suspicious signal path provided by another specific embodiment of the present application;

[0037] Figure 8 A schematic diagram of the structure of a device for determining defects in a failed chip provided in an embodiment of the present application;

[0038] Fig. 9 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0039] The embodiments of the present application are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0040] In order to enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present application, specific embodiments are described in detail below.

[0041] Figure 1 A flow chart of a method for determining defects in a failed chip provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the method for determining defects in a failed chip in this embodiment may include:

[0042] S101, obtaining a current image diagram of a suspicious signal path of a failed chip; wherein the current image diagram includes current images of suspicious signal paths in at least two metal layers in the failed chip.

[0043] The failed chip of this embodiment may be a crystal grain, and the crystal grain includes a substrate and a metal layer on the substrate. At least two metal layers in the failed chip of this embodiment may be metal layers on the substrate.

[0044] In some cases, the current image can be obtained through the principle of electron beam absorbed current (EBAC). Specifically, the electron beam can be irradiated on the failed chip and scanned to a certain point. If there is a metal wire here and it is connected through the probe, the electrons will be absorbed by the metal wire in the component and then exported to the amplifier (Amp) through the probe (Nano-Probe), and then the absorbed current at that position can be obtained. The current image can be formed through signal processing. The current image can be a grayscale image or a color image.

[0045] In the specific embodiment, the electron beam absorption current is an application of a scanning electron microscope, that is, a scanning electron microscope is used to scan a failed chip to obtain a suspicious signal path, namely, a NET suspect point. The suspicious signal path includes a signal path composed of a metal layer and / or a via.

[0046] S102, correcting the current image of the suspicious signal path of the failed chip to obtain a corrected current image of the suspicious signal path of the failed chip; wherein the corrected current image has a higher recognition degree than the current image before correction.

[0047] Recognition can be the degree of recognition or identification. If the recognition is high, it is easier to distinguish and differentiate.

[0048] The recognition degree of the corrected current image diagram is higher than that of the current image diagram before correction. Therefore, compared with the current image diagram before correction, the corrected current image diagram is easier to be quickly identified. In addition, it is convenient to improve the accuracy of defect detection in the future.

[0049] S103 : comparing the corrected current image of the suspicious signal path of the failed chip with the signal path design layout of the failed chip to determine the defect corresponding to the suspicious signal path of the failed chip.

[0050] The signal path design layout of the failed chip includes a standard signal path. When the corrected current image diagram deviates from the design layout, the suspected signal path of the failed chip has defects.

[0051] In this embodiment, the current image diagram of the suspected signal path of the failed chip is corrected to obtain a corrected current image diagram of the suspected signal path of the failed chip, and the recognition degree of the corrected current image diagram is higher than that of the current image diagram before correction. The corrected current image diagram with higher recognition degree is compared with the signal path design layout of the failed chip to determine the defect corresponding to the suspected signal path of the failed chip. Since the recognition degree of the corrected current image diagram is higher than that of the current image diagram before correction, and the defect with higher recognition degree can be identified more quickly, thus, based on the corrected current image diagram with higher recognition degree, the defect corresponding to the suspected signal path of the failed chip can be determined more quickly, that is, the efficiency of determining the defect corresponding to the suspected signal path of the failed chip is improved.

[0052] Another embodiment of the present application is basically the same as the above embodiment, except that, in step S103 of the present embodiment, correcting the current image diagram of the suspicious signal path of the failed chip to obtain the corrected current image diagram of the suspicious signal path of the failed chip may include:

[0053] S103a, determining pixel attribute values ​​of the current images of the suspicious signal paths in the at least two metal layers in the failed chip based on the current images of the suspicious signal paths in the at least two metal layers.

[0054] The pixel attribute value in this embodiment may be a grayscale value or a color value other than black, white or gray.

[0055] S103b, determining the pixel attribute value intervals to which the pixel attribute values ​​of the current image of the suspicious signal path of each metal layer belong; wherein different pixel attribute value intervals correspond to different path states of the suspicious signal path.

[0056] The path state includes an on state and at least one of the following three states: a low resistance state, a high resistance state, and an off state. Each path state corresponds to a pixel attribute value interval, ie, a pixel attribute value range.

[0057] S103c, determining the path status of the suspicious signal path in each metal layer according to the pixel attribute value intervals to which the pixel attribute values ​​of the current image of the suspicious signal path in each metal layer belong.

[0058] S103d. Based on the path status of the suspicious signal path in each metal layer, the pixel attribute value of the current image of the suspicious signal path in at least one metal layer in each metal layer is corrected to the target pixel attribute value to obtain a corrected current image of the suspicious signal path of the failed chip.

[0059] The target pixel attribute values ​​of the current images of the suspicious signal paths in each metal layer may be the same or different.

[0060] In one embodiment, the target pixel attribute value is a target grayscale value, or a target color value other than black, white, and gray.

[0061] For example, the pixel attribute value of the current image of the suspicious signal path of one metal layer is modified to the gray value corresponding to white, and the pixel attribute value of the current image of the suspicious signal path of another metal layer is modified to the gray value corresponding to gray.

[0062] In this embodiment, based on the path state of the suspicious signal path in each metal layer, the pixel attribute value of the current image of the suspicious signal path in at least one metal layer in each metal layer is corrected to a target pixel attribute value. In this way, the corrected target pixel attribute value is combined with the path state, which not only has a higher recognition, but also has the attributes of the path state.

[0063] In one embodiment, the at least two metal layers in the failed chip include a first metal layer and a second metal layer.

[0064] In step S103d of this embodiment, based on the path state of the suspicious signal path in each metal layer, the pixel attribute value of the current image of at least one of the metal layers of the suspicious signal path is corrected to the target pixel attribute value, including:

[0065] A1. Based on the path state of the suspicious signal path in the first metal layer, the pixel attribute value of the current image of the suspicious signal path in the first metal layer is corrected to a target pixel attribute value.

[0066] In a specific example, when the path state of the suspicious signal path in the first metal layer is the first path state, for the path state of the suspicious signal path in the first metal layer in step A1, correcting the pixel attribute value of the current image of the suspicious signal path in the first metal layer to the target pixel attribute value includes:

[0067] A11. Based on a first path state of the suspicious signal path in the first metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a first target pixel attribute value.

[0068] As an alternative, in some examples, when the path state of the suspicious signal path in the first metal layer is the second path state, for the path state of the suspicious signal path in the first metal layer in step A1, correcting the pixel attribute value of the current image of the suspicious signal path in the first metal layer to the target pixel attribute value includes:

[0069] A12. Based on the second path state of the suspicious signal path in the first metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a second target pixel attribute value.

[0070] In this embodiment, the second target pixel attribute value is different from the first target pixel attribute value.

[0071] In this embodiment, when the path state of the suspicious signal path in the first metal layer is different, the pixel attribute value of the current image of the suspicious signal path in the first metal layer can be set to different target pixel attribute values, that is, in the first path state, it is corrected to the first target pixel attribute value, and in the second path state, it is corrected to the second target pixel attribute value. Different path states use different target pixel attribute values, which can make it easier to distinguish different path states.

[0072] A2. Based on the path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to the target pixel attribute value.

[0073] The target pixel attribute value in this step may be the same as or different from the target pixel attribute value in step A1.

[0074] In a specific example, when the path state of the suspicious signal path in the second metal layer is the first path state, for the path state of the suspicious signal path in the second metal layer in step A2, correcting the pixel attribute value of the current image of the suspicious signal path in the second metal layer to the target pixel attribute value includes:

[0075] A21. Based on the first path state of the suspicious signal path in the second metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a first target pixel attribute value.

[0076] As an alternative, in some examples, when the path state of the suspicious signal path in the second metal layer is the second path state, for the path state of the suspicious signal path in the second metal layer in step A2, correcting the pixel attribute value of the current image of the suspicious signal path in the second metal layer to the target pixel attribute value includes:

[0077] Based on the second path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to a second target pixel attribute value.

[0078] In this embodiment, the second target pixel attribute value is different from the first target pixel attribute value.

[0079] In this embodiment, when the path state of the suspicious signal path in the second metal layer is different, the pixel attribute value of the current image of the suspicious signal path in the second metal layer can be set to different target pixel attribute values, that is, in the first path state, it is corrected to the first target pixel attribute value, and in the second path state, it is corrected to the second target pixel attribute value. Different path states use different target pixel attribute values, which can make it easier to distinguish different path states.

[0080] In some examples, before determining the pixel attribute value intervals to which the pixel attribute values ​​of the current images of the suspicious signal paths of each metal layer belong in step S103b, the method of this embodiment may further include:

[0081] S103e, determining a first path state and a second path state of a signal path in the same metal layer in a reference chip, determining a pixel attribute value of a current image of the first path state of the signal path in the same metal layer, and determining a pixel attribute value of a current image of the second path state of the signal path in the same metal layer.

[0082] In this embodiment, the reference chip and the failed chip are different chips produced by the same process.

[0083] The reference chip in this embodiment is also a defective chip. In the reference chip, the via state of each metal layer is known.

[0084] A failed chip A can be selected as a reference chip from other failed chips produced under the same process as the failed chip. At the beginning of the test, if the path state of the highest metal layer of the reference chip is the first path state, the current image diagram of the highest metal layer is obtained, and the pixel attribute value of the current image of the first path state of the signal path in the highest metal layer is determined; if the path state of the metal layer adjacent to the highest metal layer (the second highest metal layer) is the second path state, the second highest metal layer can be used as the new highest metal layer by removing the existing highest metal layer, and the current image diagram of the new highest metal layer is obtained to determine the pixel attribute value of the current image of the second path state of the signal path in the new highest metal layer, thereby determining the pixel attribute value of the current image of the first path state of the signal path in the highest metal layer and the pixel attribute value of the current image of the second path state of the signal path in the highest metal layer.

[0085] According to the method of obtaining the pixel attribute values ​​of the current image of the first path state and the second path state of the signal path in the highest metal layer, the pixel attribute values ​​of the current image of the first path state and the second path state of the signal path in the next highest metal layer and the metal layer adjacent to the next highest metal layer can be obtained.

[0086] It can be understood that, according to the above method, the pixel attribute values ​​of the current images of the first path state and the second path state of the signal path in more metal layers can also be obtained.

[0087] It is understandable that multiple failed chips can also be selected as reference chips from other failed chips produced under the same process as the failed chip, and the pixel attribute values ​​of the current image of the first path state of the signal path in the same metal layer and the pixel attribute values ​​of the current image of the second path state of the signal path in the same metal layer can be obtained from the multiple reference chips.

[0088] S103f. Based on the pixel attribute values ​​of the current image in the first path state and the pixel attribute values ​​of the current image in the second path state, divide the pixel attribute value interval between the pixel attribute values ​​of the current image in the first path state and the pixel attribute values ​​of the current image in the second path state into two or more pixel attribute value intervals according to a preset partitioning rule.

[0089] The preset partitioning rule in this embodiment may include the number of partitioning intervals, and the starting pixel attribute value and the ending pixel attribute value of each interval. In one embodiment, the preset partitioning rule may divide the pixel attribute value range between the pixel attribute value of the current image in the first path state and the pixel attribute value of the current image in the second path state into a preset number of portions.

[0090] In a specific example, if the pixel attribute value of the current image of the first path state corresponding to the highest metal layer is A, and the pixel attribute value of the current image of the second path state is B, the pixel attribute value interval between A and B can be divided into two intervals, such as the pixel attribute value interval [A-(A+B) / 2]:A as the conduction interval, and the pixel attribute value interval B: [A-(A+B) / 2] as the disconnection interval; for another example, the pixel attribute value interval between A and B can be divided into three intervals, such as the pixel attribute value interval [A-(AB) / 3]:A as the conduction interval, the pixel attribute value interval B: [A-(AB)×2 / 3] as the disconnection interval, and [A-(AB)×2 / 3]: [A-(AB) / 3] as an interval of an intermediate state between the conduction interval and the disconnection interval.

[0091] In order to improve the efficiency of determining the defects existing in the failed chip, in some examples, comparing the corrected current image of the suspected signal path of the failed chip with the signal path design layout of the failed chip in step S103 to determine the defect corresponding to the suspected signal path of the failed chip may include:

[0092] S103g. Extracting image features of the corrected current image of the suspicious signal path of the failed chip through image recognition.

[0093] The image feature may be a contour line or a central axis of the modified current image.

[0094] S103h, comparing the image features of the corrected current image diagram of the suspicious signal path with the image features of the design layout of the suspicious signal path.

[0095] The suspicious signal path design layout includes standard metal layers corresponding to at least two metal layers in step S101, and the path states of the standard metal layers in the design layout are all on.

[0096] S103i. Based on the comparison operation, determine whether there is a defect in the failed chip.

[0097] In this embodiment, image features of a corrected current image diagram of a suspected signal path of a failed chip are extracted through image recognition, and the image features of the corrected current image diagram of the suspected signal path are compared with the image features of a design layout of the suspected signal path. Based on the comparison operation, it is determined whether there are defects in the failed chip, thereby realizing automated defect finding and improving the efficiency of defect determination, thereby avoiding the problem in the prior art of manually comparing the acquired current image diagram with the design layout, which makes it difficult to find defects.

[0098] In some examples, the image feature may be a contour line of the modified current image diagram. The image feature of the modified current image diagram of the suspected signal path of the failed chip may be extracted through image recognition in step S103g, which may include:

[0099] B1. Extract the contour of the corrected current image of the suspected signal path of the failed chip through image recognition.

[0100] In some examples, the image feature may be the central axis of the corrected current image diagram. Extracting the image feature of the corrected current image diagram of the suspicious signal path of the failed chip through image recognition in step S103g may include:

[0101] B2. Extract the central axis of the corrected current image of the suspected signal path of the failed chip through image recognition.

[0102] In order to further improve the efficiency of defect determination, in the case where the image feature is a contour line, the operation of comparing the image feature of the corrected current image of the suspicious signal path with the image feature of the design layout of the suspicious signal path in step S103h may include:

[0103] C1. Compare the contour line of the corrected current image diagram of the suspicious signal path with the contour line of the design layout of the suspicious signal path.

[0104] In order to further improve the efficiency of defect determination, in the case where the image feature is the central axis, the operation of comparing the image feature of the corrected current image of the suspicious signal path with the image feature of the design layout of the suspicious signal path in step S103h may include:

[0105] C2. Compare the central axis of the corrected current image diagram of the suspicious signal path with the central axis of the design layout of the suspicious signal path.

[0106] In some examples, the operation of comparing the image features of the corrected current image of the suspicious signal path with the image features of the design layout of the suspicious signal path in step S103h may include:

[0107] D1. Performing an XOR operation on the pixel attribute value of each pixel point of the image feature of the corrected current image diagram of the suspicious signal path and the pixel attribute value of each pixel point of the image feature of the design layout of the suspicious signal path.

[0108] The solution of the present application is described in detail below with a specific embodiment.

[0109] In the prior art, due to the influence of the penetration depth of the electron beam, the electron absorption at different depths is different, which leads to a large difference in the display of different metal layers obtained by EBAC.

[0110] During the failure analysis process, the failed chip needs to be tested and SCAN diagnostic analysis is performed to obtain the EFA failure path (suspicious signal path), which is the signal path SCAN Net composed of metal (metal layer) / via (via), and relevant suspicious points of the failure path are selected for PFA analysis preparation.

[0111] The method for determining defects in a failed chip of this embodiment may include:

[0112] 1. Perform EBAC test on the SCAN Net area of ​​the failed chip.

[0113] When a chip product encounters a major failure, it is often necessary to conduct a failure analysis to further locate the fault location and find the physical cause of the failure in order to improve the process or correct the design.

[0114] In this embodiment, the SCAN Net area is tested by EBAC, and a current image grayscale map of the suspicious signal path is obtained according to the current size. The obtained current image grayscale map of the suspicious signal path includes grayscale maps of suspicious signal paths of at least two metal layers.

[0115] See also Figure 2 , from left to right, the grayscale color gradually darkens, corresponding to high-level-low-level-lower-level metal layers respectively.

[0116] 2. Correct the current image grayscale image of the suspicious signal path of the failed chip to obtain a corrected current image grayscale image of the suspicious signal path.

[0117] Determine the grayscale value interval to which the grayscale values ​​of the suspicious signal paths of each metal layer belong, and each grayscale value interval corresponds to a different target grayscale value. In this way, based on the target grayscale value corresponding to each metal layer in at least two metal layers, if all metal layers are electrically connected, each metal layer will be displayed as the target grayscale value, that is, when all metal layers are electrically connected, the display effect is consistent.

[0118] It can be understood that if the metal layer is of low resistance, high resistance or disconnected, the pixel value of the grayscale image obtained is different from the case where the metal layer is conductive. Furthermore, the target grayscale value corresponding to the low resistance, high resistance or disconnection in the corrected grayscale image may be different from the target grayscale value when the metal layer is conductive.

[0119] See also Figure 3 , the high-level Metal, the low-level Metal1 and the low-level Metal2 are turned on, and the grayscale value corresponding to each metal layer is modified to the grayscale value corresponding to white in the corrected grayscale map.

[0120] In this embodiment, the path state (conduction-high resistance-disconnection) of each metal layer can be displayed in a normalized manner to facilitate subsequent automated processing.

[0121] 3. Align the corrected grayscale image with the design layout.

[0122] Align the corrected grayscale image with the design layout to facilitate subsequent comparison of the grayscale values ​​of the corresponding pixels.

[0123] 4. Compare the corrected grayscale image with the design layout to determine the defects corresponding to the suspicious signal paths in at least two metal layers.

[0124] The contour line or the central axis in the corrected grayscale image is extracted; then an XOR operation is performed on it and the design layout to achieve accurate fault judgment and search.

[0125] See also Figure 4 and Figure 5 , extract the contour lines in the corrected grayscale image; then perform an XOR operation on it and the design layout to accurately find the open and short circuit locations.

[0126] See also Figure 6 and Figure 7 , extract the central axis in the corrected grayscale image; then perform an XOR operation on it and the design layout to accurately find the open and short circuit locations.

[0127] The grayscale value interval in the above embodiment can be determined by the following process:

[0128] For other failed chips produced under the same process conditions as the failed chip as reference chips, a grayscale image of the reference chip is obtained, and grayscale values ​​of the on and off states corresponding to each metal layer in the grayscale image are extracted.

[0129] In one embodiment, the on grayscale value and the off grayscale value of the high-level metal layer Metal, the on grayscale value and the off grayscale value of the low-level metal layer Metal1, and the on grayscale value and the off grayscale value of the low-level metal layer Metal2 are obtained, see Table 1 for details.

[0130]

[0131] The high-level Metal in Table 1 is the metal layer farthest from the substrate in the grain, the low-level Metal1 is the metal layer adjacent to the high-level Metal, and the low-level Metal2 is the metal layer adjacent to the low-level Metal1.

[0132] According to the data in Table 1, the grayscale value intervals corresponding to the path states are on, high resistance and off, please refer to Table 2 for details.

[0133]

[0134] Figure 8 A schematic diagram of a structure of a device for determining defects in a failed chip provided in an embodiment of the present application is shown in FIG. Figure 8As shown, the device for determining defects in a failed chip of the present embodiment includes: an acquisition module 11, used to obtain a current image diagram of a suspected signal path of the failed chip; wherein the current image diagram includes current images of suspected signal paths in at least two metal layers in the failed chip; a correction module 12, used to correct the current image diagram of the suspected signal path of the failed chip to obtain a corrected current image diagram of the suspected signal path of the failed chip; wherein the recognition degree of the corrected current image diagram is higher than the recognition degree of the current image diagram before correction; a comparison module 13, used to compare the corrected current image diagram of the suspected signal path of the failed chip with the signal path design layout of the failed chip to determine the defect corresponding to the suspected signal path of the failed chip.

[0135] The device of this embodiment can be used to perform Figure 1 The technical solution of the method embodiment shown has similar implementation principles and technical effects, which will not be repeated here.

[0136] The device of this embodiment corrects the current image diagram of the suspicious signal path of the failed chip to obtain a corrected current image diagram of the suspicious signal path of the failed chip, and the recognition degree of the corrected current image diagram is higher than that of the current image diagram before correction. The corrected current image diagram with higher recognition degree is compared with the signal path design layout of the failed chip to determine the defect corresponding to the suspicious signal path of the failed chip. Since the recognition degree of the corrected current image diagram is higher than that of the current image diagram before correction, and the defect with higher recognition degree can be identified more quickly, thus, based on the corrected current image diagram with higher recognition degree, the defect corresponding to the suspicious signal path of the failed chip can be determined more quickly, that is, the efficiency of determining the defect corresponding to the suspicious signal path of the failed chip is improved.

[0137] As an optional embodiment, the correction module includes: a first determination submodule, which is used to determine the pixel attribute value of the current image of the suspicious signal path of each metal layer in the at least two metal layers in the failed chip based on the current image of the suspicious signal path in at least two metal layers; a second determination submodule, which is used to determine the pixel attribute value interval to which the pixel attribute value of the current image of the suspicious signal path of each metal layer belongs; wherein different pixel attribute value intervals correspond to different path states of the suspicious signal path; a third determination submodule, which is used to determine the path state of the suspicious signal path in each metal layer according to the pixel attribute value interval to which the pixel attribute value of the current image of the suspicious signal path of each metal layer belongs; and a correction submodule, which is used to correct the pixel attribute value of the current image of the suspicious signal path in at least one of the metal layers to the target pixel attribute value based on the path state of the suspicious signal path in each metal layer, so as to obtain a corrected current image diagram of the suspicious signal path of the failed chip.

[0138] As an optional embodiment, at least two metal layers in the failed chip include a first metal layer and a second metal layer; wherein the correction submodule includes: a first correction unit, used to correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a target pixel attribute value based on the path state of the suspicious signal path in the first metal layer; and / or, a second correction unit, used to correct the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a target pixel attribute value based on the path state of the suspicious signal path in the second metal layer.

[0139] As an optional embodiment, the first correction unit is specifically used to: based on the first path state of the suspicious signal path in the first metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a first target pixel attribute value; or, based on the second path state of the suspicious signal path in the first metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

[0140] As an optional embodiment, the second correction unit is specifically used to: based on the first path state of the suspicious signal path in the second metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a first target pixel attribute value; or, based on the second path state of the suspicious signal path in the second metal layer, correct the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

[0141] As an optional embodiment, the device is also used to: determine the first path state and the second path state of the signal path in the same metal layer in the reference chip before the second determination submodule determines the pixel attribute value interval to which the pixel attribute values ​​of the current image of the suspicious signal path of each metal layer respectively belong, determine the pixel attribute value of the current image of the first path state of the signal path in the same metal layer, and determine the pixel attribute value of the current image of the second path state of the signal path in the same metal layer; wherein the reference chip and the failed chip are different chips produced under the same process; based on the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state, according to a preset partitioning rule, divide the pixel attribute value interval between the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state into two or more pixel attribute value intervals.

[0142] As an optional implementation, the comparison module includes: an extraction submodule, used to extract image features of the corrected current image diagram of the suspected signal path of the failed chip through image recognition; a comparison submodule, used to compare the image features of the corrected current image diagram of the suspected signal path with the image features of the suspected signal path design layout; and a determination submodule, used to determine whether there is a defect in the failed chip based on the comparison operation.

[0143] As an optional implementation, the extraction submodule is specifically used to: extract the contour line or central axis of the corrected current image diagram of the suspected signal path of the failed chip through image recognition; wherein the comparison submodule is specifically used to: compare the contour line of the corrected current image diagram of the suspected signal path with the contour line of the design layout of the suspected signal path; or, compare the central axis of the corrected current image diagram of the suspected signal path with the central axis of the design layout of the suspected signal path.

[0144] As an optional implementation, the comparison submodule is specifically used to: perform an XOR operation on the pixel attribute value of each pixel point of the image feature of the corrected current image diagram of the suspicious signal path and the pixel attribute value of each pixel point of the image feature of the design layout of the suspicious signal path.

[0145] As an optional implementation, the current image of the suspected signal path of the failed chip is a grayscale image; the pixel attribute value is the grayscale value of the pixel point; the target pixel attribute value is a target grayscale value, or a target color value other than black, white or gray.

[0146] As an optional implementation manner, the path state includes an on state and at least one of the following three states: a low resistance state, a high resistance state, and an off state.

[0147] The device of the above embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effect are similar and will not be repeated here.

[0148] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Fig. 9As shown, it may include: a shell 61, a processor 62, a memory 63, a circuit board 64 and a power supply circuit 65, wherein the circuit board 64 is placed inside the space enclosed by the shell 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; the power supply circuit 65 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 63 is used to store executable program codes; the processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, so as to execute any of the methods for determining defects in failed chips provided in the aforementioned embodiments, and thus can also achieve corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0149] The above electronic devices exist in many forms, including but not limited to:

[0150] (1) Ultra-mobile personal computer devices: These devices fall into the category of personal computers and have computing and processing capabilities. They also generally have mobile Internet access. These terminals include PDAs, MIDs, and UMPC devices, such as the iPad.

[0151] (2) Server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to a general-purpose computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0152] (3) Other electronic devices with data interaction functions.

[0153] Correspondingly, an embodiment of the present application also provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement any method for determining defects in a failed chip provided in the aforementioned embodiments, thereby also achieving the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0154] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0155] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0156] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0157] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present application, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0158] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0159] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for determining defects in a failed chip, characterized in that: The failed chip is a crystal grain, including: Acquire a current image of a suspicious signal path of a failed chip; wherein the current image includes current images of suspicious signal paths in at least two metal layers in the failed chip; Correcting the current image of the suspected signal path of the failed chip to obtain a corrected current image of the suspected signal path of the failed chip; wherein the corrected current image has a higher recognition degree than the current image before correction; The corrected current image of the suspicious signal path of the failed chip is compared with the signal path design layout of the failed chip to determine the defect corresponding to the suspicious signal path of the failed chip.

2. The method for determining defects in a failed chip according to claim 1, characterized in that: The step of correcting the current image diagram of the suspicious signal path of the failed chip to obtain the corrected current image diagram of the suspicious signal path of the failed chip includes: Determining pixel attribute values ​​of the current images of the suspicious signal paths in the at least two metal layers in the failed chip based on the current images of the suspicious signal paths in the at least two metal layers in the failed chip; Determine the pixel attribute value intervals to which the pixel attribute values ​​of the current images of the suspicious signal paths of the metal layers belong; wherein different pixel attribute value intervals correspond to different path states of the suspicious signal paths; Determining the path status of the suspicious signal paths in the respective metal layers according to the pixel attribute value intervals to which the pixel attribute values ​​of the current images of the suspicious signal paths in the respective metal layers belong; Based on the path status of the suspicious signal path in each metal layer, the pixel attribute value of the current image of the suspicious signal path in at least one metal layer in the metal layers is corrected to the target pixel attribute value to obtain a corrected current image of the suspicious signal path of the failed chip.

3. The method for determining defects in a failed chip according to claim 2, characterized in that: The at least two metal layers in the failed chip include a first metal layer and a second metal layer; The method of correcting the pixel attribute value of the current image of the suspicious signal path in at least one of the metal layers to a target pixel attribute value based on the path state of the suspicious signal path in each metal layer includes: Based on the path state of the suspicious signal path in the first metal layer, the pixel attribute value of the current image of the suspicious signal path in the first metal layer is corrected to a target pixel attribute value; and / or, Based on the path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to a target pixel attribute value.

4. The method for determining defects in a failed chip according to claim 3, characterized in that: The step of correcting the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a target pixel attribute value based on the path state of the suspicious signal path in the first metal layer includes: Based on a first path state of a suspicious signal path in the first metal layer, correcting a pixel attribute value of a current image of a suspicious signal path in the first metal layer to a first target pixel attribute value; or, Based on the second path state of the suspicious signal path in the first metal layer, the pixel attribute value of the current image of the suspicious signal path in the first metal layer is corrected to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

5. The method for determining defects in a failed chip according to claim 3, characterized in that: The step of correcting the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a target pixel attribute value based on the path state of the suspicious signal path in the second metal layer includes: Based on the first path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to a first target pixel attribute value; or, based on the second path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

6. The method for determining defects in a failed chip according to claim 2, characterized in that: Before determining the pixel attribute value intervals to which the pixel attribute values ​​of the current images of the suspicious signal paths of the metal layers belong, the method further includes: Determine a first path state and a second path state of a signal path in the same metal layer in a reference chip, determine a pixel attribute value of a current image of the first path state of the signal path in the same metal layer, and determine a pixel attribute value of a current image of the second path state of the signal path in the same metal layer; wherein the reference chip and the failed chip are different chips produced under the same process; Based on the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state, according to a preset partitioning rule, a pixel attribute value interval between the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state is divided into two or more pixel attribute value intervals.

7. The method for determining defects in a failed chip according to claim 1, characterized in that: The comparing the corrected current image of the suspicious signal path of the failed chip with the signal path design layout of the failed chip to determine the defect corresponding to the suspicious signal path of the failed chip includes: Extracting image features of a corrected current image of a suspicious signal path of the failed chip through image recognition; Comparing the image features of the corrected current image diagram of the suspicious signal path with the image features of the design layout of the suspicious signal path; Based on the comparison operation, it is determined whether there is a defect in the failed chip.

8. The method for determining defects in a failed chip according to claim 7, characterized in that: The extracting the image features of the corrected current image of the suspicious signal path of the failed chip through image recognition includes: Extracting the contour line or the central axis of the corrected current image of the suspicious signal path of the failed chip through image recognition; The operation of comparing the image features of the corrected current image diagram of the suspicious signal path with the image features of the design layout of the suspicious signal path includes: Comparing the contour of the corrected current image of the suspicious signal path with the contour of the design layout of the suspicious signal path; or, A comparison operation is performed on the central axis of the corrected current image diagram of the suspicious signal path and the central axis of the design layout of the suspicious signal path.

9. The method for determining defects in a failed chip according to claim 7, characterized in that: The operation of comparing the image features of the corrected current image diagram of the suspicious signal path with the image features of the design layout of the suspicious signal path includes: An exclusive OR operation is performed on the pixel attribute value of each pixel point of the image feature of the corrected current image diagram of the suspicious signal path and the pixel attribute value of each pixel point of the image feature of the design layout of the suspicious signal path.

10. The method for determining defects in a failed chip according to claim 2, characterized in that: The current image of the suspected signal path of the failed chip is a grayscale image; the pixel attribute value is the grayscale value of the pixel point; the target pixel attribute value is a target grayscale value, or a target color value other than black, white or gray.

11. The method for determining defects in a failed chip according to claim 2, characterized in that: The path state includes an on state and at least one of the following three states: a low resistance state, a high resistance state, and an off state.

12. A device for determining defects in a failed chip, characterized in that: The failed chip is a crystal grain, including: An acquisition module, used to acquire a current image of a suspicious signal path of a failed chip; wherein the current image includes current images of suspicious signal paths in at least two metal layers in the failed chip; A correction module, used for correcting the current image diagram of the suspicious signal path of the failed chip to obtain a corrected current image diagram of the suspicious signal path of the failed chip; wherein the recognition degree of the corrected current image diagram is higher than the recognition degree of the current image diagram before correction; The comparison module is used to compare the corrected current image of the suspicious signal path of the failed chip with the signal path design layout of the failed chip to determine the defect corresponding to the suspicious signal path of the failed chip.

13. The device for determining defects in a failed chip according to claim 12, characterized in that: The correction module comprises: A first determination submodule is used to determine the pixel attribute value of the current image of the suspicious signal path of each metal layer in the at least two metal layers based on the current image of the suspicious signal path in the at least two metal layers in the failed chip; A second determination submodule is used to determine the pixel attribute value intervals to which the pixel attribute values ​​of the current images of the suspicious signal paths of the metal layers belong; wherein different pixel attribute value intervals correspond to different path states of the suspicious signal paths; A third determination submodule, configured to determine the path status of the suspicious signal paths in each metal layer according to the pixel attribute value intervals to which the pixel attribute values ​​of the current images of the suspicious signal paths in each metal layer belong; A correction submodule is used to correct the pixel attribute value of the current image of the suspicious signal path in at least one of the metal layers to a target pixel attribute value based on the path status of the suspicious signal path in each metal layer, so as to obtain a corrected current image of the suspicious signal path of the failed chip.

14. The device for determining defects in a failed chip according to claim 13, characterized in that: The at least two metal layers in the failed chip include a first metal layer and a second metal layer; Wherein, the correction submodule includes: A first correction unit is configured to correct the pixel attribute value of the current image of the suspicious signal path in the first metal layer to a target pixel attribute value based on the path state of the suspicious signal path in the first metal layer; and / or The second correction unit is used to correct the pixel attribute value of the current image of the suspicious signal path in the second metal layer to a target pixel attribute value based on the path state of the suspicious signal path in the second metal layer.

15. The device for determining defects in a failed chip according to claim 14, characterized in that: The first correction unit is specifically used to: Based on a first path state of a suspicious signal path in the first metal layer, correcting a pixel attribute value of a current image of a suspicious signal path in the first metal layer to a first target pixel attribute value; or, Based on the second path state of the suspicious signal path in the first metal layer, the pixel attribute value of the current image of the suspicious signal path in the first metal layer is corrected to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

16. The device for determining defects in a failed chip according to claim 14, characterized in that: The second correction unit is specifically used for: Based on the first path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to a first target pixel attribute value; or, based on the second path state of the suspicious signal path in the second metal layer, the pixel attribute value of the current image of the suspicious signal path in the second metal layer is corrected to a second target pixel attribute value; wherein the second target pixel attribute value is different from the first target pixel attribute value.

17. The device for determining defects in a failed chip according to claim 13, characterized in that: The device is also used for: Before the second determination submodule determines the pixel attribute value intervals to which the pixel attribute values ​​of the current images of the suspicious signal paths of the respective metal layers belong, a first path state and a second path state of the signal path in the same metal layer in the reference chip are determined, and the pixel attribute value of the current image of the first path state of the signal path in the same metal layer and the pixel attribute value of the current image of the second path state of the signal path in the same metal layer are determined; wherein the reference chip and the failed chip are different chips produced under the same process; Based on the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state, according to a preset partitioning rule, a pixel attribute value interval between the pixel attribute value of the current image of the first path state and the pixel attribute value of the current image of the second path state is divided into two or more pixel attribute value intervals.

18. The device for determining defects in a failed chip according to claim 12, characterized in that: The comparison module comprises: An extraction submodule, used for extracting image features of a corrected current image of a suspicious signal path of the failed chip through image recognition; A comparison submodule, used for comparing the image features of the corrected current image diagram of the suspicious signal path with the image features of the design layout of the suspicious signal path; The determination submodule is used to determine whether there is a defect in the failed chip based on the comparison operation.

19. The device for determining defects in a failed chip according to claim 18, characterized in that: The extraction submodule is specifically used for: Extracting the contour line or the central axis of the corrected current image of the suspicious signal path of the failed chip through image recognition; Wherein, the comparison submodule is specifically used for: Comparing the contour of the corrected current image of the suspicious signal path with the contour of the design layout of the suspicious signal path; or, A comparison operation is performed on the central axis of the corrected current image diagram of the suspicious signal path and the central axis of the design layout of the suspicious signal path.

20. The device for determining defects in a failed chip according to claim 18, characterized in that: The comparison submodule is specifically used for: An exclusive OR operation is performed on the pixel attribute value of each pixel point of the image feature of the corrected current image diagram of the suspicious signal path and the pixel attribute value of each pixel point of the image feature of the design layout of the suspicious signal path.

21. The device for determining defects in a failed chip according to claim 13, characterized in that: The current image of the suspected signal path of the failed chip is a grayscale image; the pixel attribute value is the grayscale value of the pixel point; the target pixel attribute value is a target grayscale value, or a target color value other than black, white or gray.

22. The device for determining defects in a failed chip according to claim 13, characterized in that: The path state includes an on state and at least one of the following three states: a low resistance state, a high resistance state, and an off state.

23. An electronic device, characterized in that: The electronic device comprises: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program codes; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the method described in any one of the preceding claims 1-11.

24. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method described in any one of claims 1 to 11.

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