Chip testing screening method and device, testing equipment and storage medium

Abstract

The application relates to the chip testing technical field and provides a chip testing and screening method and device, a testing equipment and a storage medium. The application tests a wafer through a test program prepared in advance, can quickly and automatically acquire test data and a MAP graph of the wafer, reduces manual intervention, improves test efficiency, dynamically generates a test parameter range according to the test data, and updates the MAP graph according to the test parameter range, so that the performance and defect conditions of each chip on the wafer can be more accurately reflected, and when the chips on the wafer are screened based on the updated MAP graph, it can be ensured that the screened chips meet predetermined performance and quality requirements, the screening accuracy is improved, and powerful support is provided for chip quality control in large-scale production.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip testing technical field, and in particular to a quality testing method and device for chips in mass production, a testing equipment and a storage medium. BACKGROUND

[0002] In order to verify the performance and reliability of each die (i.e. chip) on a wafer, the chip needs to be tested on a wafer. Since each die on the wafer is unique, the performance and reliability will be affected by various factors, therefore, the test machine system cannot predict the test data of the whole wafer, so it cannot evaluate the test result of the current die according to the performance distribution of the whole wafer. In this case, the test machine system can only determine whether the current die is qualified according to the pre-set test parameter range and threshold, which cannot accurately reflect the actual performance and reliability of the die, and reduces the accuracy of chip screening. SUMMARY

[0003] Therefore, the present application provides a chip testing and screening method, device, testing equipment and storage medium, which can dynamically adjust the test parameter range according to the real-time test data of the wafer, so as to accurately screen the chip.

[0004] The first aspect of the present application provides a chip testing and screening method, which comprises:

[0005] testing the wafer using a pre-written test program to obtain test data and a MAP graph of the wafer;

[0006] generating a test parameter range according to the test data;

[0007] updating the MAP graph according to the test parameter range;

[0008] screening the chip on the wafer according to the updated MAP graph.

[0009] Optionally, the generating of the test parameter range according to the test data comprises:

[0010] calculating a statistical value according to the test data;

[0011] generating a test parameter range according to the statistical value and a preset coefficient.

[0012] Optionally, the updating of the MAP graph according to the test parameter range comprises:

[0013] traversing each coordinate value in the test data and determining whether the traversed coordinate value is within the test parameter range;

[0014] identifying a position corresponding to the coordinate in the MAP graph as a first mark when the coordinate value is within the test parameter range;

[0015] identifying a position corresponding to the coordinate in the MAP graph as a second mark when the coordinate value is not within the test parameter range;

[0016] updating the MAP graph is completed at the end of the iteration.

[0017] Optionally, the method further comprises:

[0018] For a target position point identified as the second mark in the MAP graph, obtaining K neighbor position points of the target position point;

[0019] According to the identification corresponding to the K neighbor position points, the chip corresponding to the target position point is classified by performance level.

[0020] Optionally, the classification of the chip corresponding to the target position point by performance level according to the identification corresponding to the K neighbor position points comprises:

[0021] determining whether each of the K neighbor position points is a boundary position point or a central position point;

[0022] When the neighbor position point is the boundary position point, a first weighted value is calculated according to the number of boundary position points and a preset first weight;

[0023] When the neighbor position point is the central position point, it is determined whether the central position point is a straight line position point or an inclined line position point of the target position point;

[0024] When the central position point is the straight line position point of the target position point, a second weighted value is calculated according to the identification corresponding to the straight line position point and a preset second weight;

[0025] When the central position point is the inclined line position point of the target position point, a third weighted value is calculated according to the identification corresponding to the inclined line position point and a preset third weight;

[0026] A weighted sum value is calculated according to the first weighted value, the second weighted value and the third weighted value;

[0027] According to the weighted sum value, the chip corresponding to the target position point is classified by performance level.

[0028] Optionally, the classification of the chip corresponding to the target position point by performance level according to the weighted sum value comprises:

[0029] obtaining a range of level thresholds corresponding to each preset performance level;

[0030] comparing the weighted sum value with the range of level thresholds corresponding to each preset performance level;

[0031] when the weighted sum value is in a target range of level thresholds, determining a preset performance level corresponding to the target range of level thresholds as the performance level of the chip corresponding to the target position point.

[0032] Optionally, the screening the chips on the wafer according to the updated MAP map comprises:

[0033] determining a first target chip position corresponding to the first mark and a second target chip position corresponding to the second mark in the updated MAP map in the wafer;

[0034] picking out the chip corresponding to the first target chip position and reserving the chip corresponding to the second target chip position.

[0035] A second aspect of the present application provides a chip testing and screening device, the device comprising:

[0036] a testing module configured to test a wafer using a pre-written test program to obtain test data and a MAP map of the wafer;

[0037] a generating module configured to generate a test parameter range according to the test data;

[0038] an updating module configured to update the MAP map according to the test parameter range;

[0039] a screening module configured to screen the chips on the wafer according to the updated MAP map.

[0040] A third aspect of the present application provides a testing device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the chip testing and screening method when executing the computer program.

[0041] A fourth aspect of the present application provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executable on a processor to implement the steps of the chip testing and screening method.

[0042] The chip test screening method, device, test equipment and storage medium provided by the embodiments of the present application can quickly and automatically obtain test data and a MAP graph of a wafer by testing the wafer through a test program prepared in advance, reduce manual intervention, and improve test efficiency; the test parameter range is dynamically generated according to the test data, and the MAP graph is updated according to the test parameter range, which can more accurately reflect the performance and defect condition of each chip on the wafer, so that when the chips on the wafer are screened based on the updated MAP graph, it can be ensured that the screened chips meet the predetermined performance and quality requirements, improving the screening accuracy and providing strong support for chip quality control in large-scale production. Compared with using a fixed test parameter range, the test parameter range is dynamically generated, which is more flexible and adaptive, and can better cope with the differences and changes between different wafers. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a flowchart of the chip test screening method shown in the embodiments of the present application;

[0044] Figure 2 is a MAP graph shown in the embodiments of the present application;

[0045] Figure 3 is a functional module diagram of the chip test screening device shown in the embodiments of the present application;

[0046] Figure 4 is a structural diagram of the test equipment shown in the embodiments of the present application. DETAILED DESCRIPTION

[0047] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to be limiting to the present application. As used in the specification of the present application, the singular expression "one", "a", "said", "the above", "the", and "this" are intended to include the plural expression, unless there is clear indication to the contrary in the context. It should also be understood that the term "and / or" used in the present application means any or all possible combinations of one or more listed items.

[0048] Hereinafter, the terms "first" and "second" are only for the purpose of description, and cannot be understood as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features, and in the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0049] Reference Figure 1As shown, a flowchart of a chip test screening method is shown. The chip test screening method is mainly applied to dynamic part average testing of a vehicle-grade chip. Through the chip test screening method provided in the embodiment, the test parameter range can be dynamically adjusted according to the actual test data of the wafer, so as to realize accurate screening of the chip. The chip test screening method mainly includes the following steps.

[0050] S11, testing the wafer by using a pre-written test program to obtain test data and a MAP diagram of the wafer.

[0051] The wafer is a basic material in semiconductor manufacturing, and a wafer contains multiple chips. The chip in the embodiment can be a vehicle-grade chip conforming to the automotive industry standard (usually AEC-Q100 standard).

[0052] In order to automatically test the wafer, a test program needs to be pre-written, and in the automatic test process, the wafer is subjected to specific signals (such as voltage signals, current signals, etc.) by an automatic test equipment (ATE), and the test data and the MAP diagram about the performance or defects of the wafer are collected by the test program. The test data can include DC parameters and AC parameters, wherein the DC parameters can include output voltage, output current, maximum current, leakage current, and start-up level, and the AC parameters can include transmission delay, setup and hold time, speed test, and access time. The MAP (Manufacturing Process Analysis Map) diagram is a manufacturing process analysis diagram, which is used to show the data distribution and performance in the manufacturing process.

[0053] S12, generating a test parameter range according to the test data.

[0054] Before generating the test parameter range according to the test data, the test data can be cleaned and pre-processed. The cleaning can include removing invalid data, error data or repeated data in the test data. The pre-processing can include data format conversion, data standardization, etc. of the test data. Through cleaning and preprocessing of the test data, the quality of the test data can be improved, the consistency of the test data is ensured, and more accurate test parameter range can be generated.

[0055] The test parameter range in the embodiment can be a dynamic part average testing parameter range (DPAT).

[0056] Different wafers have different test data. According to the test data of each wafer, different test parameter ranges are adjusted, so that the problem chips can be found and excluded in time according to the test parameter range, and the quality and reliability of the product are ensured.

[0057] In an optional embodiment, the generating a test parameter range according to the test data comprises:

[0058] According to the test data, a statistical value is calculated;

[0059] According to the statistical value and a preset coefficient, a test parameter range is generated.

[0060] Since a wafer usually integrates multiple dies (chips), each die needs to be strictly tested to ensure its performance and quality. Therefore, during the wafer test process, the test data of each chip needs to be collected as the basis for subsequent analysis. The test data of a wafer is a collection of test data of multiple chips.

[0061] Based on the collected test data of multiple chips, statistical analysis is performed to obtain a representative statistical value, such as median, mean, and standard deviation (Sigma). Since the standard deviation (Sigma) can measure the dispersion of data, it is important for identifying abnormal values in test data and evaluating the stability of test data. Therefore, the standard deviation (Sigma) is used as the statistical value of the test data of the wafer in the embodiments of the present application.

[0062] After the statistical value is calculated, a parameter error range needs to be generated according to the statistical value. The parameter error range is determined by multiplying the upper and lower limits of the statistical value by a preset coefficient. The preset coefficient is a number greater than 1, which is used to consider the volatility of data and the uncertainty of testing. For example, assuming that Sigma is calculated according to the test data of the wafer, and the preset coefficient is 3, then the test parameter range is [-3Sigma, 3Sigma]. Through the preset coefficient, it can be ensured that the range of the test parameter range is wide enough to cover most possible test results, while not being too wide to lose the meaning of testing.

[0063] The generated parameter error range is determined as the test parameter range, which is used to evaluate whether the manufacturing process of the wafer is stable and whether adjustment is needed, providing an accurate basis for updating the MAP chart.

[0064] S13, updating the MAP chart according to the test parameter range.

[0065] After the test parameter range is determined, the test data of each chip of the wafer is compared with the test parameter range to determine whether each chip is a good product.

[0066] In an optional implementation, the updating of the MAP map according to the test parameter range comprises:

[0067] traversing each coordinate value in the test data, and determining whether the traversed coordinate value is within the test parameter range;

[0068] when the coordinate value is within the test parameter range, marking the position corresponding to the coordinate value in the MAP map as a first mark;

[0069] when the coordinate value is not within the test parameter range, marking the position corresponding to the coordinate value in the MAP map as a second mark;

[0070] at the end of the traversal, completing the updating of the MAP map.

[0071] traversing each coordinate value in the test data, the coordinate value generally represents a specific position or region on the wafer, one coordinate value corresponds to one chip, and each coordinate value is associated with a corresponding performance parameter or quality index.

[0072] During the traversal, for each coordinate value, it is determined whether it falls within the test parameter range calculated according to the test data. When the traversed coordinate value is within the test parameter range, it indicates that the performance parameter or quality index of the region or position corresponding to the coordinate value is as expected, i.e. the chip corresponding to the coordinate value is a good product, and the position corresponding to the coordinate value in the MAP map is marked as a first mark. This mark can be a color, symbol or other visual element, indicating that the position meets the requirements.

[0073] On the contrary, if the traversed coordinate value is not within the test parameter range, it indicates that the performance parameter or quality index of the region or position corresponding to the coordinate value may be abnormal or not meet the requirements, i.e. the chip corresponding to the coordinate value is a defective product, and the position corresponding to the coordinate value in the MAP map is marked as a second mark. Unlike the first mark, the second mark usually uses a different color, symbol or visual element to highlight the potential problem area. In other words, for chips outside the test parameter range, corresponding failure marks will be made on the MAP map, such as modifying the originally marked Bin1 chip to BinN (N is a specified value). Through this intuitive marking method, chips with substandard performance can be clearly identified, providing clear guidance for subsequent production processes.

[0074] When all coordinate values in the test data are traversed, all positions on the MAP map will be correctly marked as the first mark or the second mark. At this time, the updating process of the MAP map has been completed, such as Figure 2The updated MAP chart will clearly show which areas on the wafer are in compliance and which areas may have potential problems, thus providing important reference information for subsequent production process adjustment and optimization.

[0075] The optional implementation described above, since the test parameter range is calculated based on actual test data, the updated MAP chart can accurately reflect the performance and quality of each area on the wafer; by directly identifying the areas in compliance and potential problems on the MAP chart, the user can intuitively understand the performance and quality of the wafer.

[0076] S14, screening the chips on the wafer according to the updated MAP chart.

[0077] The updated MAP chart is used as the final test result and applied to subsequent production processes. The updated MAP chart not only reflects the overall test situation of the wafer, but also accurately identifies the performance status of each chip. Therefore, in the production process, targeted chip selection and classification can be performed according to the updated MAP chart, ensuring that only qualified chips (good products) can enter the next stage of production process, thereby effectively improving product quality and production efficiency.

[0078] In an optional implementation, the screening of the chips on the wafer according to the updated MAP chart comprises:

[0079] determining a first target chip position corresponding to the first mark and a second target chip position corresponding to the second mark in the wafer;

[0080] picking out the chip corresponding to the first target chip position and retaining the chip corresponding to the second target chip position.

[0081] In the updated MAP chart, first determine the positions marked as the first mark (usually indicating areas in compliance with performance and quality), which will correspond to the first target chip positions on the wafer. At the same time, determine the positions marked as the second mark (usually indicating areas that may have performance or quality problems), which will correspond to the second target chip positions on the wafer.

[0082] For the first target chip position, the corresponding chip is considered to be in compliance with performance and quality. Therefore, these chips need to be picked out from the wafer for subsequent processing, testing or packaging. For the second target chip position, the corresponding chip may have performance or quality problems. These chips should be retained on the wafer and not be picked out for further analysis, repair or processing, or may be directly determined as defective products.

[0083] In the screening process, which chips are selected and which chips are retained can be recorded in detail, providing data basis for subsequent production management, quality tracking and process improvement.

[0084] The above optional implementation can ensure that only chips with performance and quality meeting the requirements are selected for subsequent processing or use, thereby improving the overall quality and reliability of the products and providing important data support for production management and quality monitoring.

[0085] The existing chip test screening method often uses a fixed test parameter range. However, due to the slight differences between each wafer, the fixed test parameter range cannot accurately reflect the true performance of the wafer. The embodiments of the present application dynamically adjust the test parameter range according to the test data for each wafer, and the dynamically generated test parameter range can more accurately reflect the performance and quality of each wafer, ensuring that each wafer can be evaluated under the most suitable test conditions, reducing false positives and missed detections, and improving the accuracy and efficiency of chip quality screening. Compared with using a fixed test parameter range, dynamically generating a test parameter range is more flexible and adaptable, and can better cope with the differences and changes between different wafers. At the same time, since the determination of the test parameter range is based on statistical analysis and preset coefficients, the accuracy and reliability are also guaranteed. By collecting and analyzing test data in real time, the test parameter range is continuously optimized, the test efficiency and accuracy are improved, the defective rate is reduced, and the performance and consistency of the products are ensured. Through the intuitive MAP icon identification, unqualified chips can be quickly identified and removed, reducing the downtime of the production line and labor costs, and bringing significant benefits to the semiconductor manufacturing industry.

[0086] In an optional implementation, the method further comprises:

[0087] For the target position point identified as the second mark in the MAP, K neighbor position points of the target position point are obtained;

[0088] According to the identification corresponding to the K neighbor position points, the chip corresponding to the target position point is classified according to performance level.

[0089] In the MAP, first identify those target position points marked as the second label. For each target position point marked as the second label, further obtain K neighboring position points of the position point. The selection of the neighboring position points is based on spatial distance, ensuring that the chip positions spatially close to the target position point are considered. K determines the number of neighbors that each target position point needs to consider. In actual application, K is selected based on specific application scenarios and needs, for example, K can be 8, 24, etc. For example, in a 3*3 matrix, assuming the point in the middle is considered as the target position point, its 8 neighboring position points are located above, below, left, right, and upper left, upper right, lower left, and lower right of the target position point.

[0090] For each target position point, according to the labels corresponding to the K neighboring position points, the chip corresponding to the target position point is classified into a performance level. If most of the neighboring position points represent high-performance chips, then the chip corresponding to the target position point is likely to also have high performance, and therefore can be classified as high performance. If most of the neighboring position points represent low-performance chips, then the chip corresponding to the target position point is likely to also have low performance, and therefore is classified as low performance.

[0091] The obtained chip performance level classification result can be used in various application scenarios, such as inventory management, quality control, maintenance scheduling, etc.

[0092] In the above optional implementation, the spatial position information of the updated MAP and the characteristics of the neighboring position points are used to classify the chip corresponding to the target position point into a performance level, taking into account the spatial relationship between the data, which can more accurately reflect the performance differences between the chips and improve the accuracy and reliability of the classification.

[0093] In an optional implementation, the performance level classification of the chip corresponding to the target position point according to the labels corresponding to the K neighboring position points comprises:

[0094] determining whether each of the K neighboring position points is a boundary position point or a central position point;

[0095] when the neighboring position point is the boundary position point, calculating a first weighted value according to the number of boundary position points and a preset first weight;

[0096] when the neighboring position point is the central position point, determining whether the central position point is a straight line position point or an inclined line position point of the target position point;

[0097] when the central position point is the straight line position point of the target position point, calculating a second weighted value according to the label corresponding to the straight line position point and a preset second weight;

[0098] When the center position point is a diagonal position point of the target position point, a third weighted value is calculated according to an identifier corresponding to the diagonal position point and a preset third weight;

[0099] A weighted sum value is calculated according to the first weighted value, the second weighted value and the third weighted value;

[0100] The chip corresponding to the target position point is classified according to the weighted sum value.

[0101] In the MAP graph, if a neighbor position point is located on the edge of the graph or the boundary of a specific area, the neighbor position point is considered as a boundary position point. In contrast to the boundary position point, the center position point refers to a neighbor position point not located on the edge or the boundary of a specific area.

[0102] If the center position point and the target position point are connected by a straight line (i.e., the center position point and the target position point are in the same row or the same column), the center position point is a straight line position point. In contrast to the straight line position point, if the center position point and the target position point are connected by a diagonal line (i.e., the center position point and the target position point are not in the same row or the same column), the center position point is a diagonal position point.

[0103] The first weight, the second weight and the third weight are preset values, which are used to reflect the relative importance of different types of neighbor position points to the performance evaluation of the target position point when calculating the weighted value.

[0104] The K neighbor position points are traversed to determine whether each neighbor position point is a boundary position point or a center position point. For the boundary position point, the number of all boundary position points is calculated, and a first weighted value is calculated using the preset first weight and the number. The first weighted value reflects the influence of the boundary position point on the performance evaluation of the target position point.

[0105] For the center position point, it is further determined whether the center position point is a straight line position point or a diagonal position point. For the straight line position point, a second weighted value is calculated according to an identifier (i.e., a first mark or a second mark) corresponding to the straight line position point and a preset second weight. When the identifier corresponding to the straight line position point is the first mark, the second weighted value is calculated according to a first mark value (e.g., 0) corresponding to the first mark and the preset second weight. When the identifier corresponding to the straight line position point is the second mark, the second weighted value is calculated according to a second mark value (e.g., 1) corresponding to the second mark and the preset second weight.

[0106] For the diagonal position point, a third weighted value is calculated according to the identifier (i.e., the first mark or the second mark) corresponding to the diagonal position point and a preset third weight. When the identifier corresponding to the diagonal position point is the first mark, the third weighted value is calculated according to a first mark value (for example, 0) corresponding to the first mark and the preset third weight. When the identifier corresponding to the diagonal position point is the second mark, the third weighted value is calculated according to a second mark value (for example, 1) corresponding to the second mark and the preset third weight.

[0107] The first weighted value, the second weighted value, and the third weighted value are added to obtain a weighted sum value. According to the size of the weighted sum value, the chip corresponding to the target position point is classified into a performance level.

[0108] For example, the first weight corresponding to the boundary position point is 0.2, the second weight corresponding to the straight line position point is 1, and the third weight corresponding to the diagonal position point is 0.62. Among the 8 neighboring position points of the target position point X, there are 5 boundary position points, 2 straight line position points, and 1 diagonal position point. Among the 2 straight line position points, 1 corresponds to the first mark, and the other corresponds to the second mark. The identifier corresponding to the diagonal position point is the second mark. Therefore, the weighted sum value of the target position point X is (5*0.2+1*1+1*0.62=2.62) / 8=0.3275.

[0109] In the above optional implementation, by dividing the neighboring position points into boundary position points and center position points, and further subdividing the center position points into straight line position points and diagonal position points, the characteristics of the chip in the spatial distribution are considered, making the performance evaluation more comprehensive and accurately reflecting the actual performance of the chip. By setting different weights (first weight, second weight, and third weight) for different types of neighboring position points, the contribution of the neighboring position points to the performance evaluation can be adjusted according to their characteristics and importance, making the evaluation more flexible and accurate. By considering the weighted values of different types of neighboring position points, the weighted sum value calculated can more accurately reflect the performance of the chip corresponding to the target position point, helping to reduce the possibility of misjudgment and improve the accuracy of performance evaluation. In an optional implementation, the performance level classification of the chip corresponding to the target position point according to the weighted sum value includes:

[0110] Obtaining a level threshold range corresponding to each preset performance level;

[0111] Comparing the weighted sum value with the level threshold range corresponding to each preset performance level;

[0112] When the weighted sum value is located in a target level threshold range, the preset performance level corresponding to the target level threshold range is determined as the performance level of the chip corresponding to the target position point.

[0113] The preset performance level is defined according to business requirements or industry standards to quantitatively evaluate the performance level of the chip. Each performance level corresponds to a threshold range, and different performance levels correspond to different threshold ranges. The threshold range indicates the interval in which the performance score of the chip should fall under the level. The smaller the performance level, the smaller the corresponding threshold range, and the smaller the probability that the corresponding chip is a defective product. The larger the performance level, the larger the corresponding threshold range, and the larger the probability that the corresponding chip is a defective product. For example, the performance level is level one, and the corresponding threshold range is [X1, X2). That is, the chip with a performance score between X1 and X2 is determined to be level one. The performance level is level two, and the corresponding threshold range is [X2, X3). That is, the chip with a performance score between X2 and X3 is classified as level two. The performance level is level three, and the corresponding threshold range is [X3, X4). That is, the chip with a performance score between X3 and X4 is classified as level three, and X1 < X2 < X3 < X4.

[0114] After calculating the weighted sum value of the chip corresponding to the target position point, the weighted sum value is compared with the level threshold range corresponding to each preset performance level to determine which threshold range of the performance level the weighted sum value belongs to. If the weighted sum value is exactly located in the threshold range of a certain preset performance level, it can be determined that the chip corresponding to the target position point belongs to the performance level.

[0115] The above-mentioned optional implementation can more accurately determine the actual performance level of the chip initially determined as a defective product by comparing the weighted sum value with the preset level threshold range, avoiding the practice of simply classifying all chips below the test parameter range as defective products, thereby possibly discovering some chips that are originally close to the qualified standard but are misjudged due to certain reasons. In addition, through the subdivision of the performance level, resources can be better utilized and managed. For chips that are close to the qualified standard but slightly insufficient, repair, retesting, or downgrading can be used as a strategy to avoid unnecessary waste.

[0116] The wafer size tested by the embodiment of the present application is 8 inches, the batch number is RELXX3000, the specific wafer identifier is RELXX3000-11, the notch / plane direction on the wafer is 180 degrees, the direction is downward (in semiconductor manufacturing, the notch / plane on the wafer is used for alignment and identification), the width of each Die (chip) is 117400um, and the height of the Die is 71600um.

[0117] The number of rows is 276, and the number of columns is 168, which describes the layout of the Die on the wafer, that is, there are 276 rows and 168 columns of Die on the wafer.

[0118] The detection starting position is the upper left corner, that is, the test probe starts from the upper left corner of the wafer.

[0119] Probe Direction: Back, describes the moving direction of the test probe is back.

[0120] Test Start / End Time: XXXX to XXXX, describes the duration of the test.

[0121] Number of Die Passed: 34127.

[0122] Number of Die Failed: 71.

[0123] Total Number of Die on Wafer: 34198.

[0124] Calculated Yield: 99.7924%, that is, the percentage of the number of Die passed to the total number of Die on the wafer.

[0125] Figure 3 is a structural diagram of a chip test screening device provided by an embodiment of the present application.

[0126] In some embodiments, the chip test screening device 30 can include functional modules composed of computer program segments. The computer programs of each program segment in the chip test screening device 30 can be stored in the memory of an electronic device and executed by at least one processor to perform (see detailed description) the functions of chip test screening. Figure 1

[0127] In this embodiment, the chip test screening device 30 can be divided into functional modules according to the functions it performs. The functional modules can include a test module 301, a generation module 302, an update module 303, a screening module 304, an acquisition module 305, and a classification module 306. The module referred to in the present application refers to a series of computer program segments that can be executed by at least one processor and can complete a fixed function, which are stored in the memory. In this embodiment, the functions of each module will be described in detail in subsequent embodiments.

[0128] The test module 301 is configured to test a wafer using a pre-written test program to obtain test data and a MAP graph of the wafer.

[0129] The generation module 302 is configured to generate a test parameter range according to the test data.

[0130] The update module 303 is configured to update the MAP graph according to the test parameter range.

[0131] The screening module 304 is configured to screen chips on the wafer according to the updated MAP graph.

[0132] ​The acquisition module 305 is configured to acquire K neighbor position points of a target position point marked as the second mark in the MAP.

[0133] The classification module 306 is configured to classify the chip corresponding to the target position point according to the marks corresponding to the K neighbor position points.

[0134] Optionally, the generation module 302 generates a test parameter range according to the test data, and the generation of the test parameter range according to the test data comprises:

[0135] calculating a statistical value according to the test data;

[0136] generating a test parameter range according to the statistical value and a preset coefficient.

[0137] Optionally, the update module 303 updates the MAP according to the test parameter range, and the update of the MAP according to the test parameter range comprises:

[0138] traversing each coordinate value in the test data, and judging whether the traversed coordinate value is in the test parameter range;

[0139] when the coordinate value is in the test parameter range, marking a position corresponding to the coordinate in the MAP as a first mark;

[0140] when the coordinate value is not in the test parameter range, marking a position corresponding to the coordinate in the MAP as a second mark;

[0141] at the end of the traversal, completing the update of the MAP.

[0142] Optionally, the screening module 304 screens the chips on the wafer according to the updated MAP, and the screening of the chips on the wafer according to the updated MAP comprises:

[0143] determining a first target chip position corresponding to the first mark and a second target chip position corresponding to the second mark in the updated MAP in the wafer;

[0144] selecting the chip corresponding to the first target chip position and reserving the chip corresponding to the second target chip position.

[0145] Optionally, the classification module 306 classifies the chip corresponding to the target position point according to the marks corresponding to the K neighbor position points, and the classification of the chip corresponding to the target position point according to the marks corresponding to the K neighbor position points comprises:

[0146] judging whether each neighbor position point in the K neighbor position points is a boundary position point or a center position point;

[0147] When the near-neighbor position point is the boundary position point, a first weighted value is calculated according to the number of the boundary position points and a preset first weight;

[0148] When the near-neighbor position point is the center position point, it is determined whether the center position point is a straight-line position point or an oblique-line position point of the target position point;

[0149] When the center position point is the straight-line position point of the target position point, a second weighted value is calculated according to an identifier corresponding to the straight-line position point and a preset second weight;

[0150] When the center position point is the oblique-line position point of the target position point, a third weighted value is calculated according to an identifier corresponding to the oblique-line position point and a preset third weight;

[0151] A weighted sum value is calculated according to the first weighted value, the second weighted value and the third weighted value;

[0152] The chip corresponding to the target position point is classified according to the performance level according to the weighted sum value.

[0153] Optionally, the classification of the chip corresponding to the target position point according to the performance level according to the weighted sum value comprises:

[0154] A level threshold range corresponding to each preset performance level is obtained;

[0155] The weighted sum value is compared with the level threshold range corresponding to each preset performance level;

[0156] When the weighted sum value is in a target level threshold range, a preset performance level corresponding to the target level threshold range is determined as the performance level of the chip corresponding to the target position point.

[0157] It should be understood that various changes and specific embodiments of the chip test screening method provided in the above embodiments are also applicable to the chip test screening device in the present embodiment. Through the detailed description of the chip test screening method, those skilled in the art can clearly understand the implementation process of the chip test screening device in the present embodiment. For the sake of brevity of the description, it will not be described in detail here.

[0158] The present application also provides a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement all or part of the steps of the chip test screening method.

[0159] Reference is made to Figure 4As shown, the test device provided by the embodiment of the present application is a structure schematic diagram of the test device. In the preferred embodiment of the present application, the test device 4 comprises a memory 41, at least one processor 42 and at least one communication bus 43.

[0160] Those skilled in the art should understand that, Figure 4 The structure of the test device shown is not a limitation of the embodiment of the present application, and can be a bus type structure or a star type structure. The test device 4 can further comprise more or less other hardware or software, or different component arrangements.

[0161] In some embodiments, the test device 4 is a device capable of automatically performing numerical calculation and / or information processing according to pre-set or stored instructions, and the hardware thereof comprises but is not limited to a microprocessor, an application specific integrated circuit, a programmable gate array, a digital processor and an embedded device, etc. The test device 4 can further comprise a client device, which comprises but is not limited to any electronic product capable of human-computer interaction with a client through a keyboard, a mouse, a remote controller, a touchpad or a sound control device, such as a personal computer, a tablet computer, a smart phone, a digital camera, etc.

[0162] It should be noted that the test device 4 is only an example, and other existing or future electronic products can also be applicable to the present application and should be included in the protection scope of the present application by reference.

[0163] In some embodiments, the memory 41 stores a computer program which, when executed by the at least one processor 42, implements all or part of the steps of the chip test screening method as described. The memory 41 includes a Read-Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), a One-time Programmable Read-Only Memory (OTPROM), an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc Read-Only Memory (CD-ROM) or other optical disk storage, magnetic disk storage, magnetic tape storage, or any other medium of storage of computer-readable instructions which can be used for carrying or storing data. Further, the computer-readable storage medium can include a program storage area and a data storage area, wherein the program storage area can store an operating system, application programs required by at least one function, and the like.

[0164] In some embodiments, the at least one processor 42 is a control unit of the test device 4, which connects various components of the test device 4 through various interfaces and lines, and performs various functions of the test device 4 and processes data by running or executing programs or modules stored in the memory 41 and calling data stored in the memory 41. For example, the at least one processor 42 implements all or part of the steps of the chip test screening method as described in the embodiments of the present application when executing the computer program stored in the memory; or implements all or part of the functions of the chip test screening method device. The at least one processor 42 can be composed of integrated circuits, for example, can be composed of a single packaged integrated circuit, or can be composed of multiple packaged integrated circuits with the same function or different functions, including one or more combinations of central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips.

[0165] In some embodiments, the at least one communication bus 43 is configured to enable connection communication between the memory 41 and the at least one processor 42. Although not shown, the test device 4 can further include a power supply (such as a battery) for powering the various components. Preferably, the power supply can be logically coupled to the at least one processor 42 via a power management device, which can be configured to manage charging, discharging, power usage, and the like. The power supply can further include one or more AC or DC power sources, recharging circuitry, power failure detection circuitry, power conversion or inverter circuitry, power status reporting circuitry, and the like. The test device 4 can further include a variety of sensors, Bluetooth modules, Wi-Fi modules, and the like, which are not described herein.

[0166] The integrated units implemented in the form of software functional modules described above can be stored in a computer readable storage medium. The software functional modules stored in the storage medium include a plurality of instructions for causing a test device (which can be a personal computer, a test device, or a network device, etc.) or a processor to perform part of the methods described in the various embodiments of the present application.

[0167] In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other manners. For example, the division of the above-described apparatus embodiments is merely an example, and the present application can be combined with other apparatuses or be divided into other types of apparatuses to implement the present application.

[0168] The modules described as separated components can or can not be physically separated, and the components displayed as modules can or can not be physical units, and can be located in one position or distributed on a plurality of network units. Part or all of the modules can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

Claims

1. A method of chip test screening, characterized by, The method comprises: testing a wafer using a pre-written test program to obtain test data and a MAP graph of the wafer, the test data comprising direct current parameters and alternating current parameters, the direct current parameters comprising output voltage, double output current, maximum current, leakage current and start-up level, the alternating current parameters comprising transmission delay, setup and hold time, speed test and access time, and the MAP graph being a manufacturing process analysis graph for showing data distribution and performance in a manufacturing process; generating a test parameter range according to the test data; updating the MAP graph according to the test parameter range; screening chips on the wafer according to the updated MAP graph; the generating of the test parameter range according to the test data comprises: calculating a statistical value according to the test data; generating a test parameter range according to the statistical value and a preset coefficient, the test parameter range being determined by multiplying upper and lower limits of the statistical value by the preset coefficient, and the preset coefficient being a number greater than 1 for considering data volatility and test uncertainty; the updating of the MAP graph according to the test parameter range comprises: traversing each coordinate value in the test data and determining whether the traversed coordinate value is within the test parameter range; when the coordinate value is within the test parameter range, marking a position corresponding to the coordinate in the MAP graph as a first mark; when the coordinate value is not within the test parameter range, marking the position corresponding to the coordinate in the MAP graph as a second mark; at the end of the traversal, updating the MAP graph is completed; for a target position point marked as the second mark in the MAP graph, obtaining K neighboring position points of the target position point; classifying chips corresponding to the target position point into performance levels according to marks corresponding to the K neighboring position points; the classifying of the chips corresponding to the target position point into performance levels according to the marks corresponding to the K neighboring position points comprises: determining whether each neighboring position point in the K neighboring position points is a boundary position point or a central position point; when the neighboring position point is the boundary position point, calculating a first weighted value according to a number of the boundary position points and a preset first weight; when the neighboring position point is the central position point, determining whether the central position point is a straight line position point or an inclined line position point of the target position point; when the central position point is the straight line position point of the target position point, calculating a second weighted value according to a mark corresponding to the straight line position point and a preset second weight; when the central position point is the inclined line position point of the target position point, calculating a third weighted value according to a mark corresponding to the inclined line position point and a preset third weight; calculating a weighted sum value according to the first weighted value, the second weighted value and the third weighted value; classifying the chips corresponding to the target position point into performance levels according to the weighted sum value.

2. The method of claim 1, wherein, the classifying of the chips corresponding to the target position point into performance levels according to the weighted sum value comprises: obtaining a level threshold range corresponding to each preset performance level; comparing the weighted sum value with the level threshold range corresponding to each preset performance level; when the weighted sum value is in a target level threshold range, determining a preset performance level corresponding to the target level threshold range as the performance level of the chip corresponding to the target position point.

3. The method of claim 1, wherein the method further comprises: the screening of the chips on the wafer according to the updated MAP includes: determining a first target chip position corresponding to the first mark and a second target chip position corresponding to the second mark in the updated MAP in the wafer; picking out the chip corresponding to the first target chip position and reserving the chip corresponding to the second target chip position.

4. A chip test screening apparatus characterized by comprising: The device includes: a test module configured to test a wafer using a pre-written test program to obtain test data and a MAP of the wafer, the test data including direct current parameters and alternating current parameters, the direct current parameters including output voltage, double output current, maximum current, leakage current and turn-on level, the alternating current parameters including transmission delay, setup and hold time, speed test and access time, and the MAP being a manufacturing process analysis diagram for showing data distribution and performance in a manufacturing process; a generation module configured to generate a test parameter range according to the test data; an update module configured to update the MAP according to the test parameter range; a screening module configured to screen the chips on the wafer according to the updated MAP; the generation module is specifically configured to: calculate a statistical value according to the test data; generate a test parameter range according to the statistical value and a preset coefficient, the test parameter range being determined by multiplying upper and lower limits of the statistical value by the preset coefficient, and the preset coefficient being a number greater than 1 for considering data volatility and test uncertainty; the update module is specifically configured to: traverse each coordinate value in the test data and determine whether the traversed coordinate value is within the test parameter range; when the coordinate value is within the test parameter range, identify a position corresponding to the coordinate in the MAP as a first mark; when the coordinate value is not within the test parameter range, identify the position corresponding to the coordinate in the MAP as a second mark; update the MAP at the end of the traversal; the generation module is further configured to: for a target position point identified as the second mark in the MAP, obtain K neighbor position points of the target position point; classify the chip corresponding to the target position point according to the identification of the K neighbor position points; the generation module classifies the chip corresponding to the target position point according to the identification of the K neighbor position points includes: determine whether each neighbor position point in the K neighbor position points is a boundary position point or a central position point; when the neighbor position point is the boundary position point, calculate a first weighted value according to a number of the boundary position points and a preset first weight; determining whether the center position point is a straight line position point or an oblique line position point of the target position point when the near position point is the center position point; calculating a second weighted value according to an identifier corresponding to the straight line position point and a preset second weight when the center position point is the straight line position point of the target position point; calculating a third weighted value according to an identifier corresponding to the oblique line position point and a preset third weight when the center position point is the oblique line position point of the target position point; calculating a weighted sum value according to the first weighted value, the second weighted value and the third weighted value; classifying the chip corresponding to the target position point according to the weighted sum value.

5. A test apparatus, characterized by, The computer program is executed by the processor to implement the steps of the chip test screening method according to any one of claims 1 to 3.

6. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the chip test screening method according to any one of claims 1 to 3.

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