A semiconductor device structure, gate-source structure and preparation method thereof
By using dielectric layer etching technology to form grooves and retain sidewall dielectric layers in semiconductor devices, the tight connection between the gate and the source is achieved, and the problem of difficulty in shortening the gate and source spacing in the prior art is solved, reducing the problem of reducing the distance between the gate and the source in the prior art. The on-resistance and cost of the device.
Patent Information
- Application Number
- CN202411054030.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-02
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2044-08-02
AI Technical Summary
In existing semiconductor devices, the spacing between the gate and source is difficult to effectively shorten, resulting in a large on-resistance, affecting device cost and performance.
By forming a channel layer and a barrier layer on the functional layer of the semiconductor device, grooves are formed using dielectric layer etching technology, sidewall dielectric layers are retained to prepare gate and source, and electrical is realized through two-dimensional carrier gas Connect or disconnect, control gate source spacing.
Effectively shorten and control the gate source spacing, maintain device yield, reduce costs, and improve device performance.
Smart Images
Figure CN118571757B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device structure, a gate-source structure and a preparation method thereof. Background Art
[0002] In semiconductor devices, specific on-resistance (Rsp, Specific Rdson, the product of the chip area of the device and the on-resistance) is an important indicator for measuring device performance. On the premise of meeting other electrical properties, the smaller the Rsp, the smaller the device area and the lower its corresponding cost. At present, in order to reduce Rsp, reduce the grain area and reduce costs, the commonly used method is to shorten the distance between the gate and source of the device as much as possible. For example, in the current mainstream gallium nitride high electron mobility transistor (GaN HEMT) manufacturing process, the preparation steps of the gate and source are separate, and the electrode is mainly formed by stripping or etching process to form functional partitions such as gate functional area, source functional area, drain functional area, etc., so the gate-source spacing depends on the exposure accuracy and alignment accuracy of the lithography machine, and the manufacturing difficulty is large. In addition, the metal morphology of the electrode is difficult to control, and abnormal metal morphology can easily cause device failure and affect the wafer yield. Therefore, in order to ensure the mass manufacturability of the device, the horizontal spacing between the gate and source of the GaN HEMT is generally maintained between 3-5um, which will result in a larger Rsp of the device, fail to effectively reduce costs, and is not conducive to the performance release of the power device. Summary of the invention
[0003] In view of the technical problems existing in the prior art, the present invention proposes a semiconductor device structure, a gate-source structure and a preparation method thereof, so as to shorten and control the gate-source distance.
[0004] According to one aspect of the present invention, the invention provides a method for preparing a gate-source structure of a semiconductor device, wherein the semiconductor device comprises a functional layer, wherein the functional layer comprises at least a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V compounds; and the method comprises the following steps:
[0005] Providing a first structural layer above the first region of the functional layer, wherein the first structural layer includes, from bottom to top, a gate dielectric layer or a P-type material layer and a gate metal layer, and at least a portion of the gate metal layer serves as a gate of the semiconductor device;
[0006] Providing a first dielectric layer above the first structural layer, wherein the first dielectric layer at least covers the gate metal layer;
[0007] Etching downward from the first dielectric layer above the first region until reaching the functional layer to obtain a first groove, wherein the sidewalls of the first groove are the first dielectric layer and the first structural layer from top to bottom;
[0008] Providing a second dielectric layer above the current structure and covering at least the sidewalls of the first groove;
[0009] Etching the second dielectric in the first groove to retain a second dielectric layer with a first preset thickness on a side wall of the first groove; and
[0010] A metal is provided in the first groove of the second dielectric layer with a first preset thickness remaining on the sidewall to obtain a source of the semiconductor device.
[0011] Optionally, when etching the second medium in the first groove, after etching away the second medium at the bottom of the first groove, continue to etch downward a part of the barrier layer or the entire barrier layer or a part of the channel layer in the functional layer.
[0012] According to another aspect of the present invention, the invention also provides a method for preparing a semiconductor device structure, comprising the following steps:
[0013] A semiconductor epitaxial wafer is provided as a functional layer, wherein the functional layer at least comprises a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; and the channel layer and the barrier layer are III-V group compounds;
[0014] forming a gate, a source and a drain on the functional layer respectively, wherein the source and the drain can be electrically connected or disconnected through the two-dimensional carrier gas in the functional layer; and
[0015] A passivation layer and a plurality of pads are formed above the current structure, wherein the passivation layer covers the gate, the source and the drain, and the plurality of pads are formed above the passivation layer, and the plurality of pads are electrically connected to the gate, the source and the drain through dielectric through holes to obtain a gate pad, a source pad and a drain pad;
[0016] Wherein, the gate and the source are formed according to the gate-source structure preparation method of the semiconductor device.
[0017] Optionally, when a first dielectric layer is provided above the first structural layer, the first dielectric layer extends to a preset drain region, and correspondingly, while etching to obtain a first groove, etching is performed downward from the first dielectric layer in the preset drain region until the functional layer is reached to obtain a second groove, or after forming a gate and a source, etching is performed downward from the first dielectric layer in the preset drain region until the functional layer is reached to obtain a second groove; and metal is provided in the second groove to obtain a drain.
[0018] Optionally, when the first groove and the second groove are obtained at the same time, when a second dielectric layer is provided above the current structure, the second dielectric layer is provided above the first dielectric layer, and the second dielectric layer at least covers the sidewalls of the first groove and the second groove; the method further includes: etching the second dielectric in the second groove, retaining the second dielectric layer of the second preset thickness on the sidewall of the second groove or etching away all the second dielectric in the second groove; providing metal in the second groove whose sidewall retains the second preset thickness to obtain a drain, or providing metal in the second groove whose entire second dielectric is etched away to obtain a drain.
[0019] Optionally, when providing a first structural layer above the first region of the functional layer, the first structural layer extends from the first region to the preset drain region, and the method further includes: etching downward from the first dielectric layer in the preset drain region until reaching the functional layer to obtain a second groove; correspondingly, when providing a second dielectric layer above the current structure, the second dielectric layer is provided above the first dielectric layer, and the second dielectric layer at least covers the sidewalls of the first groove and the sidewalls of the second groove; the method further includes: etching the second dielectric in the second groove, retaining the second dielectric layer with a second preset thickness on the sidewalls of the second groove; and providing metal in the second groove with the sidewalls retained with the second preset thickness to obtain a drain.
[0020] Optionally, providing the first structural layer includes:
[0021] Providing a gate dielectric layer or a P-type material layer above the functional layer;
[0022] Providing a patterned metal layer above the gate dielectric layer, or providing a metal layer above the P-type material layer, and patterning the P-type material layer and the metal layer; wherein the patterned metal layer includes a gate metal layer located in the first region and a drain metal layer located in the preset drain region;
[0023] Correspondingly, when the first dielectric layer is provided, the first dielectric layer at least covers the gate metal layer and the drain metal layer.
[0024] Optionally, the method for preparing the semiconductor device structure further comprises: electrically connecting the drain metal layer and the drain or drain pad through a dielectric through-hole.
[0025] According to another aspect of the present invention, the invention further provides a semiconductor device structure, comprising a functional layer, a dielectric layer, an electrode and a pad, wherein the functional layer comprises at least a channel layer and a barrier layer, and a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V group compounds; the dielectric layer comprises at least a gate dielectric layer or a P-type material layer, a first dielectric layer, a second dielectric layer and a passivation layer; the electrode comprises a gate, a source and a drain;
[0026] A first structural layer is located above the first region of the functional layer, and the first structural layer includes a gate dielectric layer or a P-type material layer and a gate metal layer from bottom to top, and at least part of the gate metal layer serves as a gate; a first dielectric layer is located above the first structural layer; a first groove is formed downward from the first dielectric layer above the first region, penetrating the first structural layer to the functional layer, and the sidewall of the first groove is covered with a second dielectric layer of a first preset thickness; the metal provided in the first groove with the second dielectric layer of a first preset thickness retained on the sidewall forms the source; a second groove is formed in the preset drain region of the functional layer, and the metal provided in the second groove forms the drain; the source and the drain can be electrically connected or disconnected through the two-dimensional carrier gas in the functional layer;
[0027] The passivation layer is located above the electrode and the first dielectric layer, and a plurality of pads are formed above the passivation layer. The plurality of pads are electrically connected to the gate, source and drain through dielectric through holes to obtain a gate pad, a source pad and a drain pad.
[0028] Optionally, the preset drain region includes a first dielectric layer extending from the first region.
[0029] Optionally, the preset drain region includes a drain metal layer and a first dielectric layer, wherein the first dielectric layer is located above the drain metal layer; and the drain metal layer is electrically connected to the drain or the drain pad through a dielectric through-hole.
[0030] Optionally, the horizontal spacing region between the drain metal layer and the gate metal layer includes a first dielectric or a passivation layer dielectric.
[0031] Optionally, the preset drain region includes a first structural layer and a first dielectric layer extending from the first region, wherein the first dielectric layer is located above the first structural layer; and the inner sidewall of the second groove is covered with a second dielectric layer of a second preset thickness.
[0032] According to another aspect of the present invention, the invention further provides a gate-source structure of a semiconductor device, comprising:
[0033] A functional layer, the functional layer at least comprising a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V group compounds;
[0034] A first structural layer, the first structural layer is located above the first region of the functional layer, the first structural layer comprises a gate dielectric layer or a P-type material layer and a gate metal layer from bottom to top, at least a portion of the gate metal layer serves as a gate;
[0035] A first dielectric layer, wherein the first dielectric layer is located above the first structural layer;
[0036] A first groove is formed downward from the first dielectric layer above the first region and penetrates the first structural layer to the functional layer, and the sidewall of the first groove is covered with a second dielectric layer of a first preset thickness; the metal provided in the first groove with the sidewall of the second dielectric layer of a first preset thickness retained forms a source.
[0037] The embodiment of the present invention achieves the purpose of shortening and controlling the gate-source distance by controlling the dielectric thickness between the gate and the source, thereby maintaining the device yield and effectively reducing the device cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The preferred embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:
[0039] Figure 1 is a flow chart of a method for preparing a semiconductor device structure according to Embodiment 1 of the present invention;
[0040] Figure 2 is a schematic diagram of the structural principle obtained after providing a semiconductor epitaxial wafer as a functional layer 10 according to the first embodiment of the present invention;
[0041] Figure 3 is a schematic diagram of the structural principle after providing the first structural layer 20 on the functional layer 10 according to the first embodiment of the present invention;
[0042] Figure 4 is a schematic diagram of the structural principle after a first dielectric layer 301 is provided on the first structural layer 20 according to the first embodiment of the present invention;
[0043] Figure 5 is a schematic diagram of the structural principle after the groove is etched according to the first embodiment of the present invention;
[0044] Figure 6 is a schematic diagram of a structure principle after providing a second dielectric layer 302 according to an implementation of the present invention;
[0045] Figure 7It is a schematic diagram of the structural principle after etching the second medium in the groove according to an embodiment of the present invention;
[0046] Figure 8 It is a schematic diagram of a structure principle after providing metal in a groove to form a source electrode 22 and a drain electrode 23 according to the present invention;
[0047] Fig. 9 is a schematic diagram of the structural principle of a semiconductor device according to Embodiment 1 of the present invention;
[0048] Fig.10 is a flow chart of a method for preparing a gate-source structure of a semiconductor device according to Embodiment 1 of the present invention;
[0049] Fig.11 is a schematic diagram of the device structure principle corresponding to each step in the semiconductor device structure preparation process according to the second embodiment of the present invention;
[0050] Fig.12 is a schematic diagram of the structural principle of a semiconductor device according to a third embodiment of the present invention;
[0051] Fig.13 is a schematic diagram of the device structure principle corresponding to each step in the semiconductor device structure preparation process according to the fourth embodiment of the present invention; and
[0052] Fig.14 It is a schematic diagram of the device structure principle corresponding to each step in the semiconductor device structure preparation process according to the fifth embodiment of the present invention. DETAILED DESCRIPTION
[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0054] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.
[0055] The present invention provides a semiconductor device structure, a gate-source structure and a method for manufacturing the same, which achieves the purpose of shortening and controlling the gate-source distance by controlling the dielectric thickness between the gate and the source. The present invention is described in detail below through specific embodiments. Embodiment 1
[0056] Figure 1 1 is a flow chart of a method for preparing a semiconductor device structure according to Embodiment 1 of the present invention. The method for preparing a semiconductor device structure in this embodiment comprises the following steps:
[0057] Step S1, providing a semiconductor epitaxial wafer as a functional layer 10. The functional layer 10 at least includes a channel layer and a barrier layer, wherein a two-dimensional carrier gas 111 is formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V compounds.
[0058] Step S2, forming a gate electrode 21, a source electrode 22 and a drain electrode 23 respectively on the functional layer 10. The source electrode 22 and the drain electrode 23 are electrically connected or disconnected through the two-dimensional carrier gas 111 in the functional layer 10.
[0059] Step S3, forming a passivation layer 40 and a plurality of pads 50 on the current structure. The plurality of pads 50 are electrically connected to the gate 21, the source 22 and the drain 23 through dielectric vias to obtain a gate pad, a source pad and a drain pad.
[0060] See also Figure 2 , Figure 2 It is a schematic diagram of the structural principle obtained after providing a semiconductor epitaxial wafer as a functional layer 10 according to the first embodiment of the present invention. The semiconductor epitaxial wafer in step S1 includes a substrate 100 and an epitaxial layer 110. The semiconductor epitaxial wafer is obtained by sequentially epitaxially growing a channel layer and a barrier layer on the surface of the substrate 100 using an epitaxial process, and serves as the functional layer 10 of the semiconductor device prepared in step S1. The material of the substrate 100 is, for example, intrinsic GaN or materials such as silicon (Si), silicon carbide (SiC) or sapphire (Sapphire, whose main component is Al2O3). The material of the substrate 100 in this embodiment is Si. When the substrate 100 is a non-intrinsic substrate, a buffer layer (not shown in the figure) can be further introduced to reduce the influence of lattice differences. The buffer layer can be aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (Al X Ga (1-X)N), indium gallium nitride (InGaN), aluminum indium nitride (AlInN) and aluminum indium gallium nitride (AlGaInN) are used to reduce the influence of the difference in lattice constant and thermal expansion coefficient between the substrate 100 and the epitaxial layer 110, and effectively avoid cracking of the nitride epitaxial layer 110. The buffer layer is an optional structure, and the buffer layer can be a multilayer structure, in which each layer is composed of different materials. A nucleation layer can also be introduced between the substrate 100 and the buffer layer to avoid the melt-back effect. The material of the channel layer is, for example, GaN, and the material of the barrier layer is, for example, Al X Ga (1-X) N, the channel layer and the barrier layer constitute a heterojunction, in which a two-dimensional carrier gas 111 is provided, such as a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG). The materials of the channel layer and the barrier layer constituting the heterojunction can also be other III-V semiconductor materials, such as AlN, GaN, InN and compounds of these materials, such as AlGaN, InGaN, AlInGaN, etc.
[0061] In step S2, the process of forming the gate 21 and the source 22 is shown in FIG. Fig.10 As shown, Fig.10 : is a flow chart of a method for preparing a gate-source structure of a semiconductor device according to Embodiment 1 of the present invention. In this embodiment, the method for preparing a gate-source structure includes:
[0062] Step S21, providing a first structural layer 20 above the first region 101 of the functional layer 10. The first structural layer 20 includes a gate dielectric layer 201 (or a P-type material layer) and a gate metal layer 202 from bottom to top, and part or all of the gate metal layer 202 can be used as a gate 21. In this embodiment, the first structural layer 20 extends to the second region 102 as a drain region, see Figure 3 , Figure 3 1 is a schematic diagram of a structure principle after providing a first structure layer 20 on a functional layer 10 according to an implementation of the present invention.
[0063] Step S22, providing a first dielectric layer 301 on the first structural layer 20. The first dielectric layer 301 at least covers the gate metal layer 202. Figure 4 , Figure 4 3 is a schematic diagram of a structure principle after providing a first dielectric layer 301 above the first structural layer 20 according to the present invention.
[0064] Step S23, etching downward from the first dielectric layer 301 above the gate metal layer 202 in the first region 101 until reaching the functional layer 10 to obtain a first groove 31. The sidewalls of the first groove 31 are the first dielectric layer 301 and the first structural layer 20 from top to bottom. At the same time, etching downward from the first dielectric layer 301 above the gate metal layer 202 in the second region 102 until reaching the functional layer 10 to obtain a second groove 32, see Figure 5 , Figure 5 It is a schematic diagram of the structural principle after etching the groove according to an implementation of the present invention.
[0065] Step S24, providing a second dielectric layer 302 above the current structure. The second dielectric layer 302 covers the bottom and inner wall of the first groove 31 and the second groove 32. Figure 6 , Figure 6 3 is a schematic diagram of a structure principle after providing a second dielectric layer 302 according to an implementation of the present invention.
[0066] Step S25, etching the second dielectric layer 302, retaining the second dielectric layer 302 with the first preset thickness on the side wall of the first groove 31. In the present embodiment, the second dielectric in the second groove 32 is also etched, retaining the second dielectric layer 302 with the second preset thickness on the side wall of the second groove. In the present embodiment, the second dielectric on the surface of the first dielectric layer 301 and at the bottom of the groove is etched away, and the second dielectric layer 302 with the preset thickness on the side wall is retained according to the design parameters. Among them, the first preset thickness of the second dielectric layer 302 on the side wall of the first groove and the second preset thickness of the side wall of the second groove may be the same or different. In addition, when etching the second dielectric layer 302 at the bottom of the first groove 31 and the second groove 32, only the surface of the barrier layer may be etched, or etching may continue to etch away part or all of the barrier layer in the functional layer 10 at the bottom of the groove. As shown in the figure, the entire barrier layer at the bottom of the groove is etched away, and part of the channel layer may also be etched away, so as to facilitate the metal in the groove to form an ohmic contact with the functional layer 10, for details, see Figure 7 , Figure 7 It is a schematic diagram of the structural principle after etching the second medium in the groove according to the present invention.
[0067] Step S26, providing metal in the first groove 31 of the current sidewall with the second dielectric layer 302 of the first preset thickness to obtain the source 22. In this embodiment, at the same time, providing metal in the second groove 32 of the current sidewall with the second dielectric layer 302 of the second preset thickness to obtain the drain 23, wherein a portion of the gate metal layer 202 between the first groove 31 and the second groove 32 serves as the gate 21, see Figure 8 , Figure 82 is a schematic diagram of a structure principle after providing metal in a groove to form a source electrode 22 and a drain electrode 23 according to the present invention. The source electrode 22 and the drain electrode 23 form an ohmic contact with the functional layer 10, so that they can be electrically connected or disconnected through the two-dimensional carrier gas 111 in the functional layer 10.
[0068] In this embodiment, the gate 21 is provided with a gate dielectric layer 201, such as silicon nitride, titanium nitride, aluminum oxide, etc. When no driving voltage is applied to the gate and source electrodes, the source 22 and the drain 23 are electrically connected through the two-dimensional carrier gas 111; when a driving voltage is applied to the gate and source electrodes, the two-dimensional carrier gas 111 below the gate dielectric layer 201 is depleted, thereby disconnecting the electrical connection between the source 22 and the drain 23, and obtaining a depletion-type semiconductor device. When the gate dielectric layer 201 is aluminum nitride, etc., the gate metal layer 202 can form a Schottky junction with the functional layer 10 under certain process conditions, that is, the gate structure is a Schottky gate, and a depletion-type semiconductor device is also obtained. When the gate 21 is under a P-type material layer (such as p-GaN, p-AlGaN, etc.), when no driving voltage is applied to the gate and source electrodes, the P-type material layer depletes the two-dimensional carrier gas 111 in the channel layer below it, and the source 22 and the drain 23 are not electrically connected; when a driving voltage is applied to the gate and source electrodes, a two-dimensional carrier gas 111 is generated in the channel layer below the P-type material layer, thereby establishing the electrical connection between the source 22 and the drain 23, and an enhanced semiconductor device can be obtained.
[0069] In this embodiment, the drain 23 is prepared while preparing the source 22. The material of the first dielectric layer 301 is, for example, silicon nitride, silicon oxide, high-k dielectric (such as aluminum oxide, aluminum nitride, etc.), and the material of the gate dielectric layer 201 is, for example, silicon nitride, aluminum oxide, etc. Before etching downward from the first dielectric layer 301 in step S23, firstly, a first groove 31 region and a second groove 32 region are defined on the upper surface of the first dielectric layer 301 corresponding to the first region 101 and the second region 102 using photoresist, and then etching is performed using a high selectivity etching method. The etching gas used has different rates when etching each structural layer. Taking the first dielectric layer 301 as silicon nitride as an example, firstly, F-based gas or F-based mixed gas such as CF4, SF6 is used to etch the first dielectric layer 301, and then the gate metal layer 202 is etched by switching to chlorine-based gas, and then the gate dielectric layer 201 is etched to the surface of the functional layer 10 by switching to F-based gas or F-based mixed gas. In this embodiment, the rate ratio of the F-based gas or the F-based mixed gas when etching the gate dielectric layer 201 and the functional layer 10 (such as the barrier layer) is, for example, greater than or equal to 70:1.
[0070] In step S3, the passivation layer 40 may include multiple layers. For example, after the source and drain electrodes are obtained in step S2, a passivation layer is deposited thereon, and then a pad metal layer is grown thereon and patterned, and then a passivation layer is deposited at an appropriate position above the pad metal layer, covering part of the pad metal layer while exposing part of the pad metal layer, and the exposed part of the pad metal layer forms a plurality of pads 50, see Fig. 9 , Fig. 9 2 is a schematic diagram of the structure principle of a semiconductor device according to the first embodiment of the present invention. In addition, the pads are electrically connected to the gate 21, the source 22 and the drain 23 through dielectric through-holes to obtain a gate pad, a source pad and a drain pad.
[0071] The gate metal layer 202 in the present invention is a composite metal layer deposited by electron beam evaporation or sputtering, such as TiAl, TiAl, TiN, etc. It can also be a composite structure of aluminum oxide, aluminum nitride plus metal, or titanium nitride plus metal.
[0072] In addition, when metal is provided in the first groove 31 and the second groove 32 respectively to form the source 22 and the drain 23, a multi-layer Ti / Al / Ni / Au sequence can be evaporated by an electron beam evaporation process, and the thickness of each layer depends on specific requirements. Then, an ohmic contact for the drain / source metal is prepared by a rapid thermal annealing process to ensure the stability of the source 22 and the drain 23.
[0073] The gate 21, source 22 and drain 23 in the present invention may also include corresponding field plates. Taking the gate field plate as an example, when providing the first structural layer 20 above the first region 101 of the functional layer 10, after providing the gate dielectric layer 201 and before providing the gate metal layer 202, one or more layers of field plate dielectrics are first provided, and the field plate dielectrics are etched by photolithography to form corresponding multi-step steps in the gate region, and then the gate metal layer 202 is provided. The field plate preparation process of the source 22 and the drain 23 is similar and will not be repeated here.
[0074] The first dielectric layer 301 in the present invention completely covers the gate metal layer 202, thereby wrapping and passivating the gate metal layer 202. The material of the first dielectric layer 301 is silicon nitride, silicon oxide, high-k dielectric (aluminum oxide, aluminum nitride, etc.), etc., which can be provided by chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The first dielectric layer 301 serves as a passivation layer of the gate metal layer 202 to protect the gate metal layer 202 from being affected by other processes. In addition, it also serves as a sacrificial layer when etching the second dielectric layer 302 to protect the upper surface of the gate metal layer 202, and also serves as an isolation layer on the upper surface of the gate metal layer 202 to avoid interconnection when providing the source and drain metal layers later.
[0075] The material of the second dielectric layer 302 can be silicon nitride, silicon oxide, high-k dielectric (aluminum oxide, aluminum nitride, etc.), etc. Various dielectric layers can be provided by means of CVD, ALD, etc. In this embodiment, the gate-source spacing is controlled by controlling the thickness of the second dielectric layer 302 on the sidewall of the first groove. In addition, as a passivation layer, it can reduce the leakage risk of the device. When the second dielectric is a high-k material, the second dielectric in the second groove can increase the withstand voltage of the drain 23, reduce the risk of device breakdown, and thus improve the overall performance of the device.
[0076] The semiconductor device structure provided in this embodiment includes a functional layer 10, a dielectric layer, an electrode and a pad, wherein the dielectric layer at least includes a gate dielectric layer 201, a first dielectric layer 301, a second dielectric layer 302 and a passivation layer 40, and the electrode includes a gate 21, a source 22 and a drain 23. The functional layer 10 at least includes a channel layer and a barrier layer, and a two-dimensional carrier gas 111 is formed in the region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V compounds. The gate dielectric layer 201 is deposited on the upper surface of the barrier layer, and the gate metal layer 202 is deposited on the upper surface of the gate dielectric layer 201, and the first dielectric layer 301 is formed above it; a first groove 31 is formed from the first dielectric layer 301 downwardly through the gate metal layer 202 and the gate dielectric layer 201 to the functional layer 10, and the sidewall of the first groove 31 is covered with a second dielectric layer 302 of a first preset thickness. The metal provided from the first groove 31 constitutes the source 22; the metal provided from the second groove 32 of the preset drain region of the functional layer 10 constitutes the drain 23, and the source 22 and the drain 22 are respectively electrically connected through the two-dimensional carrier gas 111 in the functional layer 10. The passivation layer 40 is located above the electrode and the first dielectric layer 301, and the plurality of pads 50 are formed on the passivation layer 40, and the plurality of pads 50 are respectively electrically connected to the gate 21, the source 22 and the drain 23 through dielectric through holes to obtain a gate pad, a source pad and a drain pad.
[0077] In this embodiment, the distance between the source 22 and the gate 21 is the thickness of the second dielectric layer 302 on the side wall of the first groove, which can be obtained during etching according to the design parameters of the device. Therefore, the distance between the source 22 and the gate 21 in the semiconductor device in this embodiment can be controlled by the dielectric thickness, so the required gate-source distance can be produced according to the design parameters, and the device yield can be maintained during the production process, thereby effectively reducing the device cost. Embodiment 2
[0078] See also Fig.11 , Fig.11 1 is a schematic diagram of the device structure principle corresponding to each step in the semiconductor device structure preparation process according to the second embodiment of the present invention. The preparation method in this embodiment includes the following steps:
[0079] Step S31 , providing a semiconductor epitaxial wafer as the functional layer 10 .
[0080] Step S32 , providing a first structural layer 20 above the first region 101 of the functional layer 10 .
[0081] Step S33, providing a first dielectric layer 301 on the first structural layer 20. The first dielectric layer 301 covers the gate metal layer 202 in the first structural layer 20 and extends to the second region 102 preset as the drain region.
[0082] In step S34 , the first dielectric layer 301 above the gate metal layer 202 in the first region 101 is etched downward until it reaches the functional layer 10 to obtain a first groove 31 , and the first dielectric layer 301 above the second region 102 is etched downward until it reaches the functional layer 10 to obtain a second groove 32 .
[0083] Step S35 , providing a second dielectric layer 302 above the current structure.
[0084] Step S36, etching the second dielectric layer 302, leaving the second dielectric layer 302 of the first preset thickness on the sidewall of the first groove, and leaving the second dielectric layer 302 of the second preset thickness on the sidewall of the second groove. The first preset thickness and the second preset thickness may be equal or unequal.
[0085] Step S37 , providing metal in the first groove 31 whose sidewalls retain the second dielectric layer 302 of the first preset thickness and in the second groove 32 whose sidewalls retain the second dielectric layer 302 of the second preset thickness to obtain the source 22 and the drain 23 .
[0086] Step S38 , forming a passivation layer 40 and a plurality of pads 50 on the current structure, wherein the plurality of pads 50 are electrically connected to the gate 21 , the source 22 and the drain 23 through dielectric through holes to obtain a gate pad, a source pad and a drain pad.
[0087] In this embodiment, the gate metal layer 202 is provided only above the first region 101. By controlling the distance between the second groove 32 and the gate metal layer 202 in the first region 101, the drain-gate distance can be controlled, thereby meeting different withstand voltage requirements of the device. Embodiment 3
[0088] See also Fig.12 , Fig.121 is a schematic diagram of the structure principle of a semiconductor device according to Embodiment 3 of the present invention. The gate dielectric layer 201 in the semiconductor device structure in this embodiment extends from the first region 101 to the second region 102. The preparation steps thereof refer to Embodiment 2. When the first structural layer 20 is provided above the first region 101 of the functional layer 10, the gate dielectric layer 201 extends from the first region 101 to the second region 102. The gate metal layer 202 is provided only on the gate dielectric layer 201 above the first region 101.
[0089] In addition, although Fig.11 and Fig.12 The upper surface of the first dielectric layer 301 in the structure shown is a horizontal plane, but it may not be a horizontal plane, for example Fig.11 In the structure corresponding to step S32, after the first structure layer 20 is formed in the first region 101, the upper surface of the device structure forms a step shape, and then a first dielectric layer 301 is deposited on the current step-shaped device structure. At this time, the first dielectric layer 301 is coated on the upper surface of the step-shaped device structure. The following preparation steps can be continued on the current structure, or the thickness of the deposition can be increased when the first dielectric layer 301 is deposited, and then a planarization process is performed to obtain Fig.11 The structure corresponding to step S33 in Fig.12 The structure shown. Embodiment 4
[0090] See also Fig.13 , Fig.13 1 is a schematic diagram of the device structure principle corresponding to each step in the semiconductor device structure preparation process according to the fourth embodiment of the present invention. The preparation method in this embodiment includes the following steps:
[0091] Step S41 , providing a semiconductor epitaxial wafer as the functional layer 10 .
[0092] Step S42 , providing a first structural layer 20 above the first region 101 of the functional layer 10 .
[0093] Step S43 : providing a first dielectric layer 301 above the first structural layer 20 , wherein the first dielectric layer 301 extends to the second region 102 preset as the drain region.
[0094] Step S44 , etching the first dielectric layer 301 above the gate metal layer 202 in the first region 101 downwards until reaching the functional layer 10 to obtain a first groove 31 .
[0095] Step S45, providing a second dielectric layer 302 above the current structure.
[0096] Step S46, etching the second dielectric layer 302, leaving the second dielectric layer 302 with a first preset thickness on the sidewall of the first groove.
[0097] Step S47 , providing metal in the first groove 31 whose sidewalls retain the second dielectric layer 302 of the first preset thickness to obtain the source 22 .
[0098] Step S48 , etching downward from the first dielectric layer 301 in the second region 102 until reaching the functional layer 10 to obtain a second groove 32 .
[0099] Step S49 , providing metal in the second groove 32 to obtain the drain 23 .
[0100] Step S410 , forming a passivation layer 40 and a plurality of pads 50 on the current structure, wherein the plurality of pads 50 are electrically connected to the gate 21 , the source 22 and the drain 23 through dielectric through holes to obtain a gate pad, a source pad and a drain pad.
[0101] After the gate and source electrodes are completed, the drain 23 is obtained in the same way in the preset drain region in this embodiment. In addition, in step S45, when the second dielectric layer 302 is provided above the current structure, although in the structure shown in the figure, the second dielectric layer 302 also covers the first dielectric layer 301 above the second region 102 as the drain region, it can be known that the second region 102 as the drain region may not be covered. Embodiment 5
[0102] See also Fig.14 , Fig.14 1 is a schematic diagram of the device structure principle corresponding to each step in the semiconductor device structure preparation process according to Embodiment 5 of the present invention. The preparation method in this embodiment includes the following steps:
[0103] Step S51 , providing a semiconductor epitaxial wafer as the functional layer 10 .
[0104] Step S52, providing a first structural layer 20 above the first region 101 of the functional layer 10. First, a gate dielectric layer 201 is provided above the functional layer 10, and then a patterned metal layer 200 is provided thereon, wherein the patterned metal layer 200 at least includes a gate metal layer 202 above the first region 101 and a drain metal layer 203 above the second region 102. In addition, when a P-type material layer is used instead of the gate dielectric layer 201, the P-type material layer and the metal layer 200 may also be patterned together.
[0105] Step S53 : providing a first dielectric layer 301 on the first structural layer 20 , wherein the first dielectric layer 301 covers the gate metal layer 202 and the drain metal layer 203 on the second region 102 .
[0106] Step S54 , etching downward from the first dielectric layer 301 above the gate metal layer 202 in the first region 101 until reaching the functional layer 10 to obtain a first groove 31 , and etching downward from the first dielectric layer 301 above the second region 102 until reaching the functional layer 10 to obtain a second groove 32 .
[0107] Step S55 , providing a second dielectric layer 302 above the current structure.
[0108] Step S56, etching the second dielectric layer 302, retaining the second dielectric layer 302 of the first preset thickness on the sidewall of the first groove, and retaining the second dielectric layer 302 of the second preset thickness on the sidewall of the second groove. The first preset thickness and the second preset thickness may be equal or unequal. In this embodiment, when etching the second dielectric at the bottom of the two grooves, part of the barrier layer is etched away.
[0109] Step S57, providing metal in the first groove 31 whose sidewall retains the second dielectric layer 302 of the first preset thickness and in the second groove 32 whose sidewall retains the second dielectric layer 302 of the second preset thickness to obtain the source 22 and the drain 23, wherein the gate metal layer 202 above the first area 101 serves as the gate 21, and the drain metal layer 203 above the second area 102 is electrically connected to the metal provided in the second groove 32 through the dielectric through hole, so that they jointly serve as the drain 23, or are electrically connected to the drain pad.
[0110] Step S58 , forming a passivation layer 40 and a plurality of pads 50 on the current structure, wherein the plurality of pads 50 are electrically connected to the gate 21 , the source 22 and the drain 23 through dielectric through holes to obtain a gate pad, a source pad and a drain pad.
[0111] Due to the gate metal layer 202 and the drain metal layer 203, the first dielectric layer 301 in this embodiment presents a groove between the gate 21 and the drain 23, such as Fig.14 However, it can be known that the groove can be filled with a passivation layer medium when providing the passivation layer 40, such as Fig.14 In the structure corresponding to step S58, when providing the first dielectric layer 301 in step S53, the deposition thickness of the first dielectric layer 301 is increased and then the surface is flattened without presenting the groove, that is, the middle area between the gate metal layer 202 and the drain metal layer 203 includes the first dielectric or the passivation layer dielectric.
[0112] Referring to the above embodiments, it can be seen that the gate-source structure in the semiconductor device provided by the present invention is unique, so that the distance between the gate 21 and the source 22 is determined by the dielectric thickness of the side wall of the groove, and the dielectric thickness can be controlled during etching, the manufacturing difficulty is small, and it is not affected by the metal morphology constituting the electrode, so it can reduce Rsp, effectively reduce costs, and meet the device yield requirements. The dielectric structure at the drain 23 in the semiconductor device provided by the present invention can have a variety of structures, such as, the second groove 32 can include a second dielectric layer 302, or it can not include the second dielectric layer 302; the drain region, starting from the functional layer 10, can only include the first dielectric layer 301, or it can include the drain metal layer 203 and the first dielectric layer 301 from bottom to top, or it can include the gate dielectric layer 201, the drain metal layer 203 and the first dielectric layer 301 from bottom to top. When the drain region includes the drain metal layer 203, the drain metal layer 203 is electrically connected to the metal in the second groove 32 through the dielectric through hole, and has the same potential as the drain 23. In addition, the horizontal spacing region between the drain metal layer 203 and the gate metal layer 202 includes a dielectric, such as a first dielectric or a passivation layer dielectric.
[0113] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present invention. Therefore, all equivalent technical solutions should also fall within the scope of the present invention.
Claims
1. A method for preparing a gate-source structure of a semiconductor device, wherein the semiconductor device comprises a functional layer, wherein the functional layer comprises at least a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; wherein the channel layer and the barrier layer are III-V compounds; wherein: The method comprises: Providing a first structural layer above the first region of the functional layer, wherein the first structural layer includes, from bottom to top, a gate dielectric layer or a P-type material layer and a gate metal layer, and at least a portion of the gate metal layer serves as a gate of the semiconductor device; Providing a first dielectric layer above the first structural layer, wherein the first dielectric layer at least covers the gate metal layer; Etching downward from the first dielectric layer above the first region until reaching the functional layer to obtain a first groove; Providing a second dielectric layer above the current structure and covering at least the sidewalls of the first groove; Etching the second dielectric in the first groove to retain a second dielectric layer with a first preset thickness on a side wall of the first groove; and A metal is provided in the first groove of the second dielectric layer with a first preset thickness remaining on the sidewall to obtain a source of the semiconductor device.
2. The method for preparing a gate-source structure of a semiconductor device according to claim 1, characterized in that: When etching the second medium in the first groove, after etching away the second medium at the bottom of the first groove, continue to etch downward a part of the barrier layer or the entire barrier layer or a part of the channel layer in the functional layer.
3. A method for preparing a semiconductor device structure, characterized in that: include: A semiconductor epitaxial wafer is provided as a functional layer, wherein the functional layer at least comprises a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; and the channel layer and the barrier layer are III-V group compounds; A gate, a source electrode and a drain electrode are respectively formed on the functional layer, wherein the source electrode and the drain electrode can be electrically connected or disconnected through the two-dimensional carrier gas in the functional layer; as well as A passivation layer and a plurality of pads are formed above the current structure, wherein the passivation layer covers the gate, the source and the drain, and the plurality of pads are formed above the passivation layer, and the plurality of pads are electrically connected to the gate, the source and the drain through dielectric through holes to obtain a gate pad, a source pad and a drain pad; Wherein, the gate and the source are formed according to the method of claim 1 or 2.
4. The method for preparing a semiconductor device structure according to claim 3, characterized in that: When a first dielectric layer is provided above the first structural layer, the first dielectric layer extends to the preset drain region. Correspondingly, while etching to obtain the first groove, etching is performed downward from the first dielectric layer in the preset drain region until the functional layer is reached to obtain a second groove, or after forming the gate and the source, etching is performed downward from the first dielectric layer in the preset drain region until the functional layer is reached to obtain a second groove; and metal is provided in the second groove to obtain a drain.
5. The method for preparing a semiconductor device structure according to claim 4, characterized in that: When the first groove and the second groove are obtained at the same time, when the second dielectric layer is provided above the current structure, the second dielectric layer is provided above the first dielectric layer, and the second dielectric layer at least covers the sidewalls of the first groove and the second groove; the method further includes: etching the second dielectric in the second groove, retaining the second dielectric layer of the second preset thickness on the sidewall of the second groove or etching away all the second dielectric in the second groove; providing metal in the second groove whose sidewall retains the second preset thickness to obtain a drain, or providing metal in the second groove whose entire second dielectric is etched away to obtain a drain.
6. The method for preparing a semiconductor device structure according to claim 3, characterized in that: When providing a first structural layer above the first region of the functional layer, the first structural layer extends from the first region to the preset drain region, and the method further includes: etching downward from the first dielectric layer in the preset drain region until reaching the functional layer to obtain a second groove; correspondingly, when providing a second dielectric layer above the current structure, the second dielectric layer is provided above the first dielectric layer, and the second dielectric layer at least covers the sidewalls of the first groove and the second groove; the method further includes: etching the second dielectric in the second groove, retaining the second dielectric layer with a second preset thickness on the sidewall of the second groove; and providing metal in the second groove with the sidewall retained with the second preset thickness to obtain a drain.
7. The method for preparing a semiconductor device structure according to claim 3, characterized in that: When providing the first structural layer, the method includes: Providing a gate dielectric layer or a P-type material layer above the functional layer; Providing a patterned metal layer above the gate dielectric layer, or providing a metal layer above the P-type material layer, and patterning the P-type material layer and the metal layer; wherein the patterned metal layer includes a gate metal layer located in the first region and a drain metal layer located in the preset drain region; Correspondingly, when the first dielectric layer is provided, the first dielectric layer at least covers the gate metal layer and the drain metal layer.
8. The method for preparing a semiconductor device structure according to claim 7, characterized in that: Further including: The drain metal layer and the drain or the drain pad are electrically connected through a dielectric through-hole.
9. A semiconductor device structure, characterized in that: It comprises a functional layer, a dielectric layer, an electrode and a pad, wherein the functional layer comprises at least a channel layer and a barrier layer, and a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V compounds; the dielectric layer comprises at least a gate dielectric layer or a P-type material layer, a first dielectric layer, a second dielectric layer and a passivation layer; the electrode comprises a gate, a source and a drain; Wherein, a first structural layer is located above the first region of the functional layer, and the first structural layer includes a gate dielectric layer or a P-type material layer and a gate metal layer from bottom to top, and at least part of the gate metal layer serves as a gate; a first dielectric layer is located above the first structural layer; a first groove is formed downward from the first dielectric layer above the first region, penetrating the first structural layer to the functional layer, and the sidewall of the first groove is covered with a second dielectric layer of a first preset thickness; the metal provided in the first groove with the second dielectric layer of a first preset thickness retained on the sidewall forms the source; a second groove is formed in the preset drain region of the functional layer, and the metal provided in the second groove forms the drain; the source and the drain can be electrically connected or disconnected through the two-dimensional carrier gas in the functional layer; The passivation layer is located above the electrode and the first dielectric layer, and a plurality of pads are formed above the passivation layer, and the plurality of pads are electrically connected to the gate, the source and the drain through dielectric through holes to obtain a gate pad, a source pad and a drain pad; The distance between the source electrode and the gate electrode is the thickness of the second dielectric layer on the side wall of the first groove, and the distance between the source electrode and the gate electrode is controlled by the thickness of the second dielectric layer on the side wall of the first groove.
10. The semiconductor device structure according to claim 9, characterized in that: The preset drain region includes a first dielectric layer extending from the first region.
11. The semiconductor device structure according to claim 10, characterized in that: The preset drain region includes a drain metal layer and a first dielectric layer, wherein the first dielectric layer is located above the drain metal layer; the drain metal layer is electrically connected to the drain or the drain pad through a dielectric through-hole.
12. The semiconductor device structure according to claim 11, characterized in that: The horizontal spacing region between the drain metal layer and the gate metal layer includes a first dielectric or a passivation layer dielectric.
13. The semiconductor device structure according to claim 9, characterized in that: The preset drain region includes a first structural layer and a first dielectric layer extending from the first region, wherein the first dielectric layer is located above the first structural layer; and the inner sidewall of the second groove is covered with a second dielectric layer with a second preset thickness.
14. A gate-source structure of a semiconductor device, characterized in that: include: A functional layer, the functional layer at least comprising a channel layer and a barrier layer, wherein a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V group compounds; A first structural layer, the first structural layer is located above the first region of the functional layer, the first structural layer comprises a gate dielectric layer or a P-type material layer and a gate metal layer from bottom to top, at least a portion of the gate metal layer serves as a gate; A first dielectric layer, wherein the first dielectric layer is located above the first structural layer; A first groove is formed downward from the first dielectric layer above the first region, penetrating the first structural layer to the functional layer, and the sidewall of the first groove is covered with a second dielectric layer of a first preset thickness; the metal provided in the first groove with the second dielectric layer of a first preset thickness remaining on the sidewall forms a source electrode; The distance between the source electrode and the gate electrode is the thickness of the second dielectric layer on the side wall of the first groove, and the distance between the source electrode and the gate electrode is controlled by the thickness of the second dielectric layer on the side wall of the first groove.