Wafer and bonding method

Abstract

The present application discloses a wafer and a bonding method. The wafer bonding method includes providing a first substrate and a second substrate, wherein the first substrate and the second substrate respectively have a substrate surface and a bonding surface that are arranged opposite to each other; polishing the bonding surface of the first substrate and the bonding surface of the second substrate; aligning the bonding surface of the first substrate with the bonding surface of the second substrate, placing the substrate in a bonding chamber for bonding, and having a first ambient pressure P in the bonding chamber. 1 , the bonding chamber has a second ambient pressure P 2 ; Satisfy P 1 <P 2 ; Anneal the first substrate and the second substrate wafer to complete bonding. The wafer bonding method provided by the present application improves the wafer preparation process by controlling the environmental pressure during the bonding process, and combines the previous polishing process and the subsequent annealing process, solves the problem that intrinsic void defects may be generated at the bonding interface during silicon-silicon bonding or silicon-oxygen bonding, and provides conditions for preparing silicon-on-insulator wafers without interface void defects.

Description

Technical Field

[0001] The present application belongs to the technical field of silicon-on-insulator manufacturing, and specifically relates to a wafer and a bonding method. Background Art

[0002] At present, the mainstream preparation technologies of silicon-on-insulator (SOI) wafers can be divided into oxygen-injection isolation SIMOX technology, smart stripping technology (Smart-cut) and BESOI bonding thinning technology. Except for the oxygen-injection isolation technology, which is an injection and annealing process on a silicon wafer substrate, the BESOI and Smart-cut processes are both carried out on the basis of bonding two silicon wafers, so the bonding process has become one of the most critical processes of silicon-on-insulator wafers. However, affected by factors such as the surface particle value, flatness, surface roughness, and surface hydrophilicity of the wafers to be bonded, void defects will appear at the bonding interface of the two wafers during the bonding process; in addition, the bonding interface is also prone to defects called "intrinsic voids". The size of this "intrinsic void" defect is between 50 and 500μm, mainly distributed at the edge of the bonded silicon wafer. Due to the resolution, conventional IR infrared detection (resolution>500μm) cannot detect this defect, and it needs to be tested by high-resolution ultrasonic microscopy SAM. How to improve SOI wafer preparation technology and reduce the intrinsic void defects generated in the bonding process is a problem that needs to be solved at present. Summary of the invention

[0003] The present application provides a wafer and a bonding method, aiming to solve the problem of intrinsic void defects existing at the bonding interface in the existing wafer bonding process.

[0004] On the one hand, the present application provides a wafer bonding method, comprising the following steps:

[0005] Providing a first substrate and a second substrate, wherein the first substrate and the second substrate respectively have a substrate surface and a bonding surface that are arranged opposite to each other;

[0006] performing a polishing process on the bonding surface of the first substrate and the bonding surface of the second substrate;

[0007] Aligning the bonding surface of the first substrate with the bonding surface of the second substrate, placing them in a bonding chamber for bonding, wherein the bonding chamber has a first environmental pressure P1, and the bonding chamber has a second environmental pressure P2; satisfying P1≤P2;

[0008] The first substrate and the second substrate wafers are annealed to complete bonding.

[0009] In some embodiments, the second ambient pressure P2 and the first ambient pressure P1 further satisfy: 10 4Pa≤P2-P1≤10 5 Pa.

[0010] In some embodiments, the step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes:

[0011] The bonding chamber is evacuated to control the pressure in the bonding chamber to be 0-10 5 Pa.

[0012] In some embodiments, the bonding time is 10 to 60 seconds.

[0013] In some embodiments, the step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes:

[0014] A pressure F is applied to the substrate surface of the first substrate, satisfying: 0.5N≤F≤6N.

[0015] In some embodiments, the step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes:

[0016] A protective gas is introduced into the bonding chamber.

[0017] In some embodiments, the amount of the protective gas introduced is 1-8% of the total volume of the gas in the bonding chamber.

[0018] In some embodiments, the shielding gas includes at least one of helium and nitrogen.

[0019] In some embodiments, the flow ratio of hydrogen to helium is 1:1 to 1:100.

[0020] In some embodiments, the annealing temperature is 1000-1200°C.

[0021] On the other hand, an embodiment of the present application provides a wafer, which is manufactured by the manufacturing method in any of the above embodiments, and includes a first substrate layer and a second substrate layer arranged in sequence.

[0022] In some embodiments, the thickness of the first substrate layer is 300-1000 μm.

[0023] In some embodiments, the second substrate layer has a thickness of 300-1000 μm.

[0024] The wafer bonding method provided in the present application includes providing a first substrate and a second substrate, wherein the first substrate and the second substrate respectively have a substrate surface and a bonding surface that are relatively arranged; polishing the bonding surface of the first substrate and the bonding surface of the second substrate; aligning the bonding surface of the first substrate with the bonding surface of the second substrate, placing them in a bonding chamber for bonding, wherein the bonding chamber has a first environmental pressure P1, and the bonding chamber has a second environmental pressure P2; satisfying P1<P2; annealing the first substrate and the second substrate wafers to complete the bonding. The wafer bonding method provided in the present application improves the wafer preparation process by controlling the environmental pressure during the bonding process, and combines the preceding polishing process and the subsequent annealing process, solves the problem that intrinsic void defects may be generated at the bonding interface during silicon-silicon bonding or silicon-oxygen bonding, and provides conditions for preparing silicon-on-insulator wafers without interface void defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0026] Figure 1 A SAM characterization diagram of a wafer provided in Example 1 of the present application;

[0027] Figure 2 This is a SAM characterization diagram of a wafer provided for Comparative Example 1 of the present application. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0029] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features.

[0030] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application.

[0031] The first embodiment of the present application provides a wafer bonding method, comprising the following steps:

[0032] Providing a first substrate and a second substrate, wherein the first substrate and the second substrate respectively have a substrate surface and a bonding surface that are arranged opposite to each other;

[0033] Polishing the bonding surface of the first substrate and the bonding surface of the second substrate;

[0034] Align the bonding surface of the first substrate with the bonding surface of the second substrate, place them in a bonding chamber for bonding, the bonding chamber has a first environmental pressure P1, and the bonding chamber has a second environmental pressure P2; satisfying P1<P2;

[0035] The first substrate and the second substrate wafer are annealed to complete bonding.

[0036] During the wafer bonding process, the generation of "intrinsic void" defects is related to the Joule-Thomson effect, that is, when the flowing gas encounters a sudden change in pressure, it will cause a change in temperature. Specifically, the upper and lower wafers to be bonded will generate a bonding wave under the action of the van der Waals force. The bonding wave is transmitted to the nearby air, forming a compression-like action. When the bonding wave is transmitted at a relatively fast speed, the air at the corresponding interface is subjected to a drastic change in pressure, which not only changes the local pressure, but also causes the temperature to drop significantly. The water vapor in the air will rapidly nucleate and liquefy to form tiny water droplets when it reaches its condensation point temperature under relatively low pressure. These small water droplets will hinder the bonding of the upper and lower wafers, and ultimately lead to the formation of "intrinsic void" defects. By controlling the environmental pressure inside and outside the bonding chamber during the bonding process, combined with the previous polishing process and subsequent annealing treatment, it is possible to reduce the amount of impurities such as dust and moisture in the air outside the bonding chamber that enter the bonding chamber, thereby reducing the situation in which water vapor liquefies to form water droplets during the bonding process, leading to "intrinsic voids"; at the same time, the environmental pressure inside the bonding chamber is lower than the environmental pressure outside the bonding chamber, which can further protect the bonding interface from external factors (such as temperature, humidity, etc.), thereby ensuring the integrity and stability of the bonding interface.

[0037] In some embodiments, the second ambient pressure P2 has a pressure difference ΔP with the first ambient pressure P1.

[0038] =P2-P1,10 4 Pa≤△P≤10 5 Pa. It is understood that the value of ΔP (unit: Pa) can be 10 4 , 2×10 4 , 4×10 4 , 6×10 4 , 8×10 4 , 10 5 When △P is small enough, the pressure change at the interface during the bonding wave transmission process is small, and water vapor condensation will not occur, but it will cause impurities in the air outside the bonding chamber to enter the bonding chamber, which will also affect the bonding quality; when the value of △P meets the above range of values, the pressure change at the interface during the bonding wave transmission process is not enough to cause water vapor condensation to nucleate, while ensuring the quality of bonding.

[0039] In some embodiments, the step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes:

[0040] Evacuate the bonding chamber and control the pressure inside the bonding chamber to less than 10 5 It is understood that the pressure in the bonding chamber (unit: Pa) can be 0, 100, 10 3, 10 4 , 10 5 When the pressure in the control chamber satisfies the above range, the pressure change at the interface during the transmission of the bonding wave can also be reduced, thereby effectively reducing the intrinsic void.

[0041] In some embodiments, the bonding time is 10 to 60 seconds. It is understandable that the bonding time (unit: s) can be any value of 10, 20, 30, 40, 50, 60 or a range between any two values. The bonding process requires a certain amount of time to ensure that the bonding interface is fully contacted and bonded, thereby ensuring the integrity of the bonding interface. If the bonding time is too long, the local temperature difference in the bonding chamber will be too large. On the one hand, more water vapor will liquefy to form water droplets, and on the other hand, unnecessary crystal growth may occur. Therefore, when the bonding time meets the above range of values, the wafer can be controlled to be fully contacted during the bonding process, while ensuring the quality of the bonding interface.

[0042] In some embodiments, the step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes:

[0043] A pressure F is applied to the substrate surface of the first substrate, satisfying: 0.5N≤F≤6N.

[0044] It can be understood that the value of F (unit: N) can be any value among 0.5, 1, 2, 4, 6 or a range between any two values. The smaller the pressure applied to the substrate surface of the first substrate, the slower the transmission speed of the bonding wave, the smaller the change in air pressure at the interface when reaching the edge, and the less likely it is to condense into water droplets and produce intrinsic void defects; but if the pressure applied to the substrate surface of the first substrate is too small, the upper and lower sheets will not be fully bonded, so that the local area is wrapped with air and cannot escape, resulting in void defects caused by air bubbles. Therefore, when F meets the above value range, it can reduce the void defects caused by water vapor and air at the same time.

[0045] In some embodiments, the step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes:

[0046] A protective gas is introduced into the bonding chamber.

[0047] The Joule coefficient of the shielding gas is relatively small, which can slow down the Joule-Thomson effect, thereby reducing the problem of gas cooling into tiny water droplets and effectively improving the intrinsic void problem.

[0048] In some embodiments, the amount of the protective gas introduced is 1% to 8% of the total volume of the gas in the bonding chamber. It is understood that the amount of the protective gas introduced can be any value of 1%, 3%, 5%, 7%, 8%, or a range between any two values. When the amount of the protective gas introduced meets the above range, the Joule-Thomson effect can be significantly mitigated.

[0049] In some embodiments, the shielding gas includes at least one of helium and nitrogen.

[0050] In some embodiments, the flow ratio of helium to nitrogen is 1:1 to 1:100.

[0051] In some embodiments, the annealing temperature is 1000-1200°C. It is understood that the annealing temperature (unit: °C) can be any value of 1000, 1050, 1100, 1150, 1200 or a range between any two values; further, the annealing temperature can be preferably 1100-1200°C. It is understood that the annealing temperature (unit: °C) can be any value of 1100, 1150, 1200 or a range between any two values. When the annealing temperature meets the above range, the integrity and stability of the wafer after bonding can be further ensured.

[0052] On the other hand, an embodiment of the present application provides a wafer, which is manufactured by the manufacturing method in any of the above embodiments, and includes a first substrate layer and a second substrate layer arranged in sequence.

[0053] In some embodiments, the thickness of the first substrate layer is 300-1000 μm. It is understood that the value (unit: μm) of the thickness of the first substrate layer can be any value among 300, 500, 700, 1000 or a range between any two values; further, the thickness of the first substrate layer can preferably be 600-800 μm. It is understood that the value (unit: μm) of the thickness of the first substrate layer can be any value among 600, 650, 700, 750, 800 or a range between any two values.

[0054] In some embodiments, the thickness of the second substrate layer is 300-1000 μm. It is understood that the value (unit: μm) of the thickness of the second substrate layer can be any value among 300, 500, 700, 1000 or a range between any two values; further, the thickness of the second substrate layer can preferably be 600-800 μm. It is understood that the value (unit: μm) of the thickness of the second substrate layer can be any value among 600, 650, 700, 750, 800 or a range between any two values.

[0055] The wafer and bonding method provided by the present application are described below in conjunction with specific embodiments:

[0056] Example 1

[0057] This embodiment provides a wafer bonding method, comprising the following steps:

[0058] Providing a first substrate and a second substrate, wherein the first substrate and the second substrate respectively have a substrate surface and a bonding surface that are arranged opposite to each other;

[0059] performing a polishing process on the bonding surface of the first substrate and the bonding surface of the second substrate;

[0060] Aligning the bonding surface of the first substrate with the bonding surface of the second substrate, placing them in a bonding chamber for bonding, wherein the bonding chamber has a first environmental pressure P1, and the bonding chamber has a second environmental pressure P2; satisfying P1<P2;

[0061] The first substrate and the second substrate wafers are annealed to complete bonding.

[0062] The bonded wafers were tested by ultrasonic microscope SAM. The results are as follows: Figure 1 As shown. Figure 1 It can be seen that the wafer bonding interface obtained by bonding using the solution provided in the present application is smooth and has no intrinsic void defects.

[0063] Embodiments 2 to 10

[0064] The wafer bonding methods provided in Examples 2 to 10 are consistent with those in Example 1, with only the process parameters being adjusted.

[0065] Comparative Example 1

[0066] The wafer bonding method provided in Comparative Example 1 is consistent with that in Example 1, except that the pressure inside the bonding chamber is the same as the pressure outside the bonding chamber.

[0067] The bonded wafers were tested by ultrasonic microscope SAM. The results are as follows: Figure 2 As shown. Figure 2 It can be seen that a large number of intrinsic void defects appear at the edge of the wafer bonding interface obtained by bonding using the solution provided in the present application, and the quality is not ideal.

[0068] Comparative Examples 2 to 5

[0069] The wafer bonding methods provided in Comparative Examples 2 to 5 are consistent with those in Comparative Example 1, with only the process parameters being adjusted.

[0070] The process parameters in Examples 1 to 10 and Comparative Examples 1 to 5 are shown in Table 1.

[0071] Table 1

[0072]

[0073]

[0074] The intrinsic void defect densities of the wafers prepared in the above-mentioned embodiments and comparative examples were tested in turn, and the results are shown in Table 2.

[0075] Table 2

[0076] Void defect density Example 1 0 Example 2 0 Example 3 0 Example 4 0 Example 5 0 Example 6 0 Example 7 0 Example 8 0 Example 9 0 Example 10 0 Comparative Example 1 314 Comparative Example 2 275 Comparative Example 3 198 Comparative Example 4 226 Comparative Example 5 183

[0077] According to Table 2, it can be seen that the wafer prepared using the solution provided in the present application can effectively reduce the void defects on the flat surface of the wafer and improve the wafer quality under the condition of controlling the pressure inside and outside the bonding chamber to meet a certain pressure difference.

[0078] The above is a detailed introduction to a wafer and a bonding method provided in the embodiments of the present application. Specific examples are used in the present application to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A wafer bonding method, characterized in that: The steps include: Providing a first substrate and a second substrate, wherein the first substrate and the second substrate respectively have a substrate surface and a bonding surface that are arranged opposite to each other; performing a polishing process on the bonding surface of the first substrate and the bonding surface of the second substrate; Aligning the bonding surface of the first substrate with the bonding surface of the second substrate, placing them in a bonding chamber for bonding, wherein the bonding chamber has a first environmental pressure P1, and the bonding chamber has a second environmental pressure P2; satisfying P1<P2; Wherein, the second environmental pressure P2 and the first environmental pressure P1 satisfy: 10 4 Pa≤P2-P1≤10 5 Pa; the bonding time is 10 to 60 seconds; The first substrate and the second substrate wafers are annealed to complete bonding.

2. A wafer bonding method according to claim 1, characterized in that: The step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes: The bonding chamber is evacuated to control the pressure in the bonding chamber to be 0-10 5 Pa.

3. A wafer bonding method according to claim 1, characterized in that: The step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes: A pressure F is applied to the substrate surface of the first substrate, satisfying: 0.5N≤F≤6N.

4. A wafer bonding method according to claim 1, characterized in that: The step of aligning the bonding surface of the first substrate with the bonding surface of the second substrate and placing them in a bonding chamber for bonding further includes: A protective gas is introduced into the bonding chamber.

5. A wafer bonding method according to claim 4, characterized in that: The amount of the protective gas introduced is 1% to 8% of the total volume of the gas in the bonding chamber.

6. A wafer bonding method according to claim 4, characterized in that: The protective gas includes at least one of helium and nitrogen.

7. A wafer bonding method according to claim 6, characterized in that: The flow ratio of the helium gas to the nitrogen gas is 1:1 to 1:

100.

8. The wafer bonding method according to claim 1, characterized in that: The annealing temperature is 1000-1200°C.

9. A wafer, characterized in that: The wafer is manufactured by the bonding method according to any one of claims 1 to 8, and comprises a first substrate layer and a second substrate layer arranged in sequence.

10. The wafer according to claim 9, characterized in that: The thickness of the first substrate layer is 300-1000 μm; and / or, The thickness of the second substrate layer is 300-1000 μm.

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