Semiconductor structure and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a target layer structure and a conductive structure. The target layer structure includes at least one dielectric layer, and at least one trench is provided within the dielectric layer. The conductive structure is located within the trench and is in direct contact with the dielectric layer. The bottom surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D2, wherein the maximum surface roughness D1 is greater than the maximum surface roughness D2. This disclosure aims to improve process reliability and the electrical performance of high-density integrated memories.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Memory, a commonly used semiconductor storage device in computers, typically consists of an array region composed of multiple memory cells and a peripheral area composed of control circuitry. A memory cell can, for example, employ a 1T1C architecture, comprising a transistor and a capacitor, with the transistor controlling the capacitor to store or release charge. The control circuitry addresses and drives the target memory cell for data access via word lines (WLs) and bit lines (BLs) connecting the memory cells. However, with the increasing demand for memory storage capacity, such as the need for embedded word line technology, higher reliability requirements are placed on the manufacturing process, and trench manufacturing defects can easily affect the electrical performance of high-density integrated memory. Summary of the Invention

[0003] Based on this, the present disclosure provides a semiconductor structure and its manufacturing method, which is beneficial to improving process reliability and the electrical performance of high-density integrated memory.

[0004] To achieve the above objectives, in a first aspect, some embodiments of this disclosure provide a semiconductor structure, including: a target layer structure and a conductive structure. The target layer structure includes at least one dielectric layer, and at least one trench is provided within the dielectric layer. The conductive structure is located within the trench and is in direct contact with the dielectric layer. The bottom surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D2, wherein the maximum surface roughness D1 > the maximum surface roughness D2.

[0005] In some embodiments of this disclosure, the bottom of the trench has multiple recesses. The bottom of the conductive structure has multiple protrusions that fill the recesses.

[0006] In some embodiments of this disclosure, the distance from any protrusion along the first direction to the midpoint of the bottom surface of the conductive structure is greater than the distance from the protrusion to the edge of the conductive structure; wherein, the first direction is perpendicular to the depth direction of the trench, and the first direction is the width direction of the trench.

[0007] In some embodiments of this disclosure, the bottom surface of the conductive structure includes: a central region and a peripheral region adjacent to the central region; wherein the surface roughness of the central region is less than that of the peripheral region.

[0008] In some embodiments of this disclosure, the bottom surface of the conductive structure includes: a first region, a second region, and a third region arranged equidistantly along a first direction; wherein the first direction is perpendicular to the depth direction of the trench and the first direction is the width direction of the trench; the surface roughness of the second region and the third region is greater than the surface roughness of the first region.

[0009] In some embodiments of this disclosure, the surface roughness of the second region and the third region is the same or similar; or, the surface roughness of the third region is greater than that of the second region.

[0010] In some embodiments of this disclosure, the semiconductor structure further includes a substrate. The target layer structure is located on the substrate. The minimum distances from the second region and the third region to the substrate are both greater than the minimum distance from the first region to the substrate.

[0011] In some embodiments of this disclosure, the target layer structure includes at least two dielectric layers stacked along the depth direction of the trench. The conductive structure is only filled in the first dielectric layer at the bottom of the trench.

[0012] In some embodiments of this disclosure, the first dielectric layer includes a silicon oxide layer, a silicon dioxide layer, an undoped silicon glass layer, a doped silicon nitride layer, a tetraethoxysilane layer, or a fluorosilicone glass layer. The conductive structure includes a metallic conductive layer.

[0013] In some embodiments of this disclosure, the width of the conductive structure gradually increases in a first direction along the depth direction away from the bottom of the trench; wherein the first direction is perpendicular to the depth direction of the trench and is the width direction of the trench.

[0014] In some embodiments of this disclosure, the target layer structure includes at least two dielectric layers stacked along the depth direction of the trench. A conductive structure fills the trench in each dielectric layer, and the corresponding portions of the conductive structure in different dielectric layers have different widths in a first direction; wherein the first direction is perpendicular to the depth direction of the trench and is also the width direction of the trench.

[0015] In some embodiments of this disclosure, the conductive structure includes a first metal layer and a second metal layer. The first metal layer conformally covers the bottom and sides of the trench. The second metal layer covers the first metal layer and fills the trench. The maximum surface roughness of the bottom surface of the first metal layer is greater than the maximum surface roughness of its sides.

[0016] In some embodiments of this disclosure, the top surface of the second metal layer away from the bottom of the trench is lower than or higher than the top surface of the first metal layer away from the bottom of the trench.

[0017] Secondly, some embodiments of this disclosure also provide a method for manufacturing a semiconductor structure, which may include the following steps.

[0018] Prepare a target layer structure, which includes at least one dielectric layer.

[0019] At least one trench is formed within the dielectric layer.

[0020] A conductive structure that directly contacts the dielectric layer is formed in a trench; wherein the bottom surface of the conductive structure that directly contacts the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure that directly contacts the dielectric layer has a maximum surface roughness D2, wherein the maximum surface roughness D1 > the maximum surface roughness D2.

[0021] In some embodiments of this disclosure, forming at least one trench within the dielectric layer further includes forming a plurality of pits at the bottom of the trench.

[0022] The conductive structure that forms a direct contact dielectric layer in the trench further includes: forming a plurality of protrusions at the bottom of the conductive structure to fill the pits.

[0023] The embodiments disclosed herein may have, or at least have, the following advantages:

[0024] This embodiment of the invention forms trenches within the dielectric layer of the target layer structure, and forms conductive structures that are in direct contact with the dielectric layer within the trenches. The bottom and side surfaces of the conductive structures can have different surface roughnesses; specifically, the maximum surface roughness D1 of the bottom surface of the conductive structure is greater than the maximum surface roughness D2 of the side surface. Thus, in the context of continuously shrinking device dimensions, the conductive structures formed within the trenches and in direct contact with the dielectric layer can ensure the electrical performance of the conductive structure based on the smaller maximum surface roughness of its side surface compared to its bottom surface, while simultaneously regulating the contact performance and bottom electric field distribution of the conductive structure based on the larger maximum surface roughness of its bottom surface compared to its side surface. This effectively improves the electrical performance of the trench conductive structure and ensures its process reliability, thereby contributing to improved electrical performance of high-density integrated memories.

[0025] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic cross-sectional view of a semiconductor structure provided in some embodiments;

[0028] Figure 2 This is a schematic diagram illustrating a surface roughness characteristic provided in some embodiments;

[0029] Figure 3 This is a schematic cross-sectional view of another semiconductor structure provided in some embodiments;

[0030] Figure 4 This is a schematic cross-sectional view of yet another semiconductor structure provided in some embodiments;

[0031] Figure 5 This is a cross-sectional schematic diagram and a partially enlarged view of another semiconductor structure provided in some embodiments;

[0032] Figure 6 This is a cross-sectional schematic diagram and a partially enlarged view of another semiconductor structure provided in some embodiments;

[0033] Figure 7 This is a cross-sectional schematic diagram and a partially enlarged view of another semiconductor structure provided in some embodiments;

[0034] Figure 8 This is a schematic cross-sectional view of yet another semiconductor structure provided in some embodiments;

[0035] Figure 9 This is a schematic cross-sectional view of yet another semiconductor structure provided in some embodiments;

[0036] Figure 10 This is a schematic cross-sectional view of yet another semiconductor structure provided in some embodiments;

[0037] Figure 11 This is a schematic cross-sectional view of yet another semiconductor structure provided in some embodiments;

[0038] Figure 12 This is a schematic cross-sectional view of yet another semiconductor structure provided in some embodiments;

[0039] Figure 13 A scanning electron microscope image of a cross-section of a semiconductor structure provided in some embodiments;

[0040] Figure 14 This is a schematic cross-sectional view of yet another semiconductor structure provided in some embodiments;

[0041] Figure 15 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in some embodiments.

[0042] Explanation of reference numerals in the attached figures:

[0043] 1-Target layer structure, G-Trench, 2-Conductive structure, 10-Substrate, 11-First dielectric layer, 12-Second dielectric layer, 13-Third dielectric layer, 14-Fourth dielectric layer, 21-Bump, 201-First metal layer, 202-Second metal layer, 203-Gate insulating layer, 204-Insulating capping layer, 3-Interconnect structure, S d - Bottom surface of the conductive structure, S r -The side of the conductive structure, R C -Middle area, R P - Surrounding areas, R1-First area, R2-Second area, R3-Third area. Detailed Implementation

[0044] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0046] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0047] It should be understood that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is a transmission of electrical signals or data between the connected objects.

[0048] It should be understood that the singular forms of “a,” “an,” and “the” can also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] As the demand for memory storage capacity continues to increase, such as the need to use embedded word lines, the reliability requirements of the manufacturing process are becoming higher. Defects in trench manufacturing can also affect the electrical performance of high-density integrated memory, especially the electrical performance of conductive structures (such as embedded word lines) that are fabricated using trenches with a high aspect ratio.

[0050] Based on this, the present disclosure provides a semiconductor structure and its manufacturing method, which is beneficial to improving the process reliability of trench conductive structures and the electrical performance of high-density integrated memory.

[0051] Please see Figure 1 This disclosure provides a semiconductor structure in some embodiments. The semiconductor structure includes a target layer structure 1 and a conductive structure 2. The target layer structure 1 includes at least one dielectric layer, and at least one trench G is provided within the dielectric layer. The conductive structure 2 is located within the trench G and is in direct contact with the dielectric layer. The bottom surface S of the conductive structure 2, which is in direct contact with the dielectric layer... d The side surface S of the conductive structure 2, which has the maximum surface roughness D1 and is in direct contact with the dielectric layer. r It has a maximum surface roughness D2, where the maximum surface roughness D1 is greater than the maximum surface roughness D2. Surface roughness, as referred to herein, means the dimensional difference between the highest and lowest structural features of a surface; in one embodiment, please refer to... Figure 2 The maximum surface roughness D1 is used to represent the distance 5 between the highest point 4 and the lowest point 3 of the rough surface. In this embodiment, a trench G is formed within the dielectric layer of the target layer structure 1, and a conductive structure 2 that directly contacts the dielectric layer is formed within the trench G. This allows the bottom surface S of the conductive structure 2 to be made more flexible. d and side S r They have different surface roughnesses, specifically making the bottom surface S of conductive structure 2... d The maximum surface roughness D1 is greater than that of the conductive structure 2 side surface S r The maximum surface roughness D2. Thus, in the context of continuously shrinking component dimensions, the conductive structure 2 formed within the trench G and in direct contact with the dielectric layer can be based on its side surface S r Relative to the bottom surface Sd A smaller maximum surface roughness D2 corresponds to ensuring the electrical performance of the conductive structure 2, while based on its bottom surface S d Compared to the side S r A larger maximum surface roughness D1 corresponds to the control of the contact performance of the conductive structure 2 and its bottom electric field distribution, thereby effectively improving the electrical performance of the trench conductive structure and ensuring its process reliability, which in turn helps to improve the electrical performance of high-density integrated memory.

[0052] It is worth mentioning that, in this embodiment of the present disclosure, the bottom surface S of the conductive structure 2... d and side S r Surface roughness can be controlled by controlling the morphology of the trench G. For example, please refer to... Figure 3 The bottom of the trench G has multiple pits. The bottom of the conductive structure 2 has multiple protrusions 21 filling the pits, which define the surface roughness of the conductive structure 2. The bottom surface S of the conductive structure 2 d The surface roughness can be controlled by the morphology of the protrusions 21 formed at the bottom of the conductive structure 2, and the longitudinal cross-sectional profile of the protrusions 21 can be, for example, arc-shaped. This embodiment does not limit the number, size, or location distribution of the pits within the trench G. The pits at the bottom of the trench G can be formed, for example, by directional etching using a plasma etching process.

[0053] In addition, it should be noted that the bottom surface S of conductive structure 2 d and side S r There are many different ways to implement surface roughness.

[0054] In some embodiments of this disclosure, please refer to Figure 4 The distance L1 from any protrusion 21 along the first direction (e.g., the X direction) to the midpoint O1 of the bottom surface of the conductive structure 2 is greater than the distance L2 from the protrusion 21 to the edge O2 of the conductive structure 2; wherein, the first direction (e.g., the X direction) is perpendicular to the depth direction (e.g., the Z direction) of the trench G, and the first direction (e.g., the X direction) is the width direction of the trench G.

[0055] In this embodiment, each protrusion 21 is distributed between the midpoint O1 of the bottom surface of the conductive structure 2 and the edge O2 of the conductive structure 2, avoiding the positions of the midpoint O1 and the corners of the edge O2. After ensuring that the distance L1 from the protrusion 21 along the first direction (e.g., the X direction) to the midpoint O1 of the bottom surface of the conductive structure 2 is greater than the distance L2 from the protrusion 21 to the edge O2 of the conductive structure 2, the bottom surface S of the conductive structure 2 can be adjusted by the setting position of each protrusion 21. d The surface roughness and contact performance are improved, and the bottom electric field distribution of the conductive structure 2 is balanced.

[0056] For example, the number of protrusions 21 is even, and they can be symmetrically distributed in a first direction (e.g., the X direction) with the midpoint O1 of the bottom surface of the conductive structure 2 as the center.

[0057] In other embodiments of this disclosure, please refer to Figure 5 The bottom surface S of conductive structure 2 d Includes: intermediate region R C and the adjacent middle region R C The surrounding area R P Among them, the middle region R C The surface roughness is less than that of the surrounding area R P Surface roughness.

[0058] This disclosure embodiment addresses the intermediate region R. C The area is not limited and can be matched to the requirements from the bottom surface S of conductive structure 2. d The geometric center is defined according to the preset dimensions.

[0059] In some embodiments of this disclosure, please refer to Figure 6 The bottom surface of the conductive structure 2 includes a first region R1, a second region R2, and a third region R3 arranged equidistantly along a first direction (e.g., the X direction); wherein the first direction (e.g., the X direction) is perpendicular to the depth direction (e.g., the Z direction) of the trench G, and the first direction (e.g., the X direction) is the width direction of the trench (G); the surface roughness of the second region R2 and the third region R3 is greater than the surface roughness of the first region R1.

[0060] Optionally, the surface roughness of the second region R2 and the third region R3 is the same or similar.

[0061] Optionally, the surface roughness of the third region R3 is greater than that of the second region R2.

[0062] In some embodiments of this disclosure, please refer to Figure 7 The semiconductor structure also includes a substrate 10. The target layer structure 1 is located on the substrate 10. The minimum distance (e.g., L) between the second region R2 and the third region R3 and the substrate. 12 and L 13 All of these are greater than the minimum distance L from the first region R1 to the substrate 10. 11 That is, the bottom surface of the conductive structure 2 can be tilted relative to the surface of the substrate 10 and extend along a preset direction.

[0063] In some embodiments of this disclosure, please refer to Figure 8 The target layer structure 1 includes at least two dielectric layers stacked along the depth direction (e.g., the Z direction) of the trench G. The conductive structure 2 is filled only in the first dielectric layer 11 at the bottom of the trench G.

[0064] Optionally, the first dielectric layer 11 includes a silicon oxide layer, a silicon dioxide layer, an undoped silicon glass layer (USG), a doped silicon nitride layer (NDC), a tetraethoxysilane layer (TEOS), or a fluorosilicone glass layer (FSG).

[0065] Optionally, the conductive structure 2 includes a metal conductive layer.

[0066] In some examples, such as Figure 8 As shown, the target layer structure 1 includes a first dielectric layer 11, a second dielectric layer 12, a third dielectric layer 13, and a fourth dielectric layer 14 stacked along the depth direction (e.g., the Z direction) of the trench G; wherein, the first dielectric layer 11 is an undoped silicon glass layer (USG), the second dielectric layer 12 is a doped silicon nitride layer (NDC), the third dielectric layer 13 is a tetraethoxysilane layer (TEOS), and the fourth dielectric layer 14 is a fluorosilicone glass layer (FSG). Accordingly, the conductive structure 2 is filled only in the first dielectric layer 11 at the bottom of the trench G. The portions of the trench G located in the second dielectric layer 12, the third dielectric layer 13, and the fourth dielectric layer 14 can be filled to form an interconnect structure 3. The interconnect structure 3 is connected to the conductive structure 2, and the interconnect structure 3 can be made of the same material or a different material than the conductive structure 2.

[0067] Furthermore, in some embodiments of this disclosure, the target layer structure 1 includes at least two dielectric layers stacked along the depth direction (e.g., the Z direction) of the trench G, and the conductive structure 2 is filled in each dielectric layer corresponding to the trench G, which is also permissible.

[0068] In some embodiments of this disclosure, please refer to Figure 9 Along the depth direction away from the bottom of the trench G (e.g., the Z direction), the width of the conductive structure 2 gradually increases in the first direction (e.g., the X direction); wherein the first direction (e.g., the X direction) is perpendicular to the depth direction (e.g., the Z direction) of the trench (G), and the first direction (e.g., the X direction) is the width direction of the trench (G).

[0069] For example, along the depth direction away from the bottom of the trench G (e.g., the Z direction), the bottom width of the conductive structure 2 is W1, the middle width of the conductive structure 2 is W2, and the top width of the conductive structure 2 is W3, wherein the top width is W3 > the middle width is W2 > the bottom width is W1.

[0070] In some embodiments of this disclosure, please refer to Figure 10The target layer structure 1 includes at least two dielectric layers stacked along the depth direction (e.g., the Z direction) of the trench G; for example, it includes a first dielectric layer 11 and a second dielectric layer 12. The conductive structure 2 fills the trench G in each dielectric layer, and the corresponding portions of the conductive structure 2 in different dielectric layers have different widths in a first direction (e.g., the X direction); wherein, the first direction (e.g., the X direction) is perpendicular to the depth direction (e.g., the Z direction) of the trench G, and the first direction (e.g., the X direction) is the width direction of the trench G.

[0071] In some embodiments of this disclosure, please refer to Figure 11 The conductive structure 2 includes a first metal layer 201 and a second metal layer 202. The first metal layer 201 conformally covers the bottom and side surfaces of the trench G. The second metal layer 202 covers the first metal layer 201 and fills the trench G. The maximum surface roughness of the bottom surface of the first metal layer 201 is greater than the maximum surface roughness of its side surfaces.

[0072] For example, the first metal layer 201 includes, but is not limited to, a titanium nitride layer.

[0073] For example, the second metal layer 202 includes, but is not limited to, a tungsten layer.

[0074] In some embodiments of this disclosure, please refer to Figure 12 and Figure 13 The top surface of the second metal layer 202 away from the bottom of the trench G is lower than the top surface of the first metal layer 201 away from the bottom of the trench G.

[0075] In some embodiments of this disclosure, please refer to Figure 14 It is also permissible for the top surface of the second metal layer 202, which is away from the bottom of the trench G, to be higher than the top surface of the first metal layer 201, which is away from the bottom of the trench G.

[0076] It should be noted that the conductive structure 2 provided in the embodiments of this disclosure can be applied to submicron interlayer damascene interconnect structures, high aspect ratio intralayer interconnect structures, or buried word lines of memory, etc. Furthermore, the target layer structure 1 provided in the embodiments of this disclosure is not limited to including the substrate 10 and the film layer stacked on the surface of the substrate 10; it may also include a film layer formed within the substrate 10, for example... Figure 14 The shallow trench isolation structure (STI) shown in the figure.

[0077] In some examples, please refer to Figure 14 , Figure 14 A partial cross-sectional structure of a memory is shown. For example... Figure 14As shown, the substrate 10 of the memory has a shallow trench isolation structure (STI), which separates multiple active regions (AA) within the substrate 10. The substrate 10 also has multiple word line trenches for forming buried word lines (WL); some of these word line trenches are located within the shallow trench isolation structure (STI). Accordingly, the trench G described in some of the aforementioned embodiments can be a word line trench located within the shallow trench isolation structure (STI), and the conductive structure 2 can correspond to a buried word line (WL).

[0078] For example, the embedded word line WL includes a grid insulating layer 203, a first metal layer 201, a second metal layer 202 and an insulating cap layer 204 sequentially disposed in the word line trench; wherein, the maximum surface roughness of the bottom surface of the embedded word line WL located in the word line trench within the shallow trench isolation structure STI is greater than the maximum surface roughness of its side surface.

[0079] For example, a shallow trench isolation (STI) structure may include a single layer or multiple layers of dielectric material. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorosilicone glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric material, organic polymer dielectric material, or combinations of the above materials, but are not limited thereto.

[0080] For example, the insulating cap layer 204 and the gate insulating layer 203 may each include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), or a combination of the above materials, but are not limited thereto.

[0081] In some embodiments, the gate insulating layer 203 may include a high-k constant metal oxide dielectric material, such as hafnium oxide (HfO), hafnium silicate oxide (HfSiO), hafnium silicate nitride oxide (HfSiON), aluminum oxide (AlO), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), tantalum oxide (TaO), zirconium oxide (ZrO), zirconium silicate oxide (ZrSiO), or hafnium zirconium oxide (HfZrO), but is not limited thereto.

[0082] For example, the material of the first metal layer 201 may include n-type work function metals such as titanium aluminum oxide (TiAl), zirconium aluminum oxide (ZrAl), tungsten aluminum oxide (WAl), tantalum aluminum oxide (TaAl), hafnium aluminum oxide (HfAl), or TiAlC (titanium aluminum carbide), or combinations thereof, or may include p-type work function metals such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), or combinations thereof, but is not limited thereto.

[0083] For example, the second metal layer 202 may include metallic materials such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), combinations of the above metallic materials such as compounds, alloys, and / or composite layers, but is not limited thereto.

[0084] In addition, the substrate 10 of the memory may include other circuit elements and structures, such as bit line structures and interconnect structures, which are not shown in the figure for the sake of simplicity.

[0085] This disclosure also provides a method for manufacturing a semiconductor structure, using some embodiments thereof, for manufacturing the semiconductor structures described in the above embodiments. The manufacturing method of this semiconductor structure also possesses the technical advantages of the aforementioned semiconductor structures, and will not be detailed here. Furthermore, each layer structure involved in the following method embodiments can be implemented in conjunction with the aforementioned descriptions corresponding to the same features.

[0086] Please see Figure 15 The manufacturing method of a semiconductor structure may include the following steps S100~S300.

[0087] S100, Prepare the target layer structure, the target layer structure including at least one dielectric layer.

[0088] S200, at least one trench is formed in the dielectric layer.

[0089] S300, a conductive structure that directly contacts the dielectric layer is formed in the trench; wherein, the bottom surface of the conductive structure that directly contacts the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure that directly contacts the dielectric layer has a maximum surface roughness D2, wherein the maximum surface roughness D1 > the maximum surface roughness D2.

[0090] In some embodiments of this disclosure, step S200, which involves forming at least one trench G within the dielectric layer, further includes forming a plurality of pits at the bottom of the trench.

[0091] Accordingly, step S300, which forms a conductive structure in the trench that directly contacts the dielectric layer, further includes forming a plurality of protrusions at the bottom of the conductive structure that fill the pits, the protrusions defining the surface roughness of the conductive structure.

[0092] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0093] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The target layer structure includes at least one dielectric layer, wherein at least one trench is provided in the dielectric layer; A conductive structure is located within the trench and is in direct contact with the dielectric layer; Wherein, the bottom surface and at least part of the side surface of the conductive structure are in contact with the same dielectric layer; the bottom surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D2, wherein the maximum surface roughness D1 > the maximum surface roughness D2. The bottom surface of the conductive structure includes: a first region, a second region, and a third region arranged equidistantly along a first direction; Wherein, the first direction is perpendicular to the depth direction of the trench, and the first direction is the width direction of the trench; the surface roughness of the second region and the third region is greater than the surface roughness of the first region.

2. The semiconductor structure according to claim 1, characterized in that, The bottom of the trench has multiple pits; the bottom of the conductive structure has multiple protrusions that fill each of the pits.

3. The semiconductor structure according to claim 2, characterized in that, The distance from any of the protrusions along the first direction to the midpoint of the bottom surface of the conductive structure is greater than the distance from the protrusion to the edge of the conductive structure; wherein, the first direction is perpendicular to the depth direction of the trench, and the first direction is the width direction of the trench.

4. The semiconductor structure according to claim 1, characterized in that, The second region and the third region have the same surface roughness; Alternatively, the surface roughness of the third region is greater than that of the second region.

5. The semiconductor structure according to claim 1, characterized in that, It also includes the substrate; The target layer structure is located on the substrate; The minimum distance from the second region and the third region to the substrate is greater than the minimum distance from the first region to the substrate.

6. The semiconductor structure according to claim 1, characterized in that, The target layer structure includes at least two dielectric layers stacked along the depth direction of the trench; the conductive structure is only filled in the first dielectric layer at the bottom of the trench.

7. The semiconductor structure according to claim 6, characterized in that, The first dielectric layer includes a silicon oxide layer, an undoped silicon glass layer, a doped silicon nitride layer, a tetraethoxysilane layer, or a fluorosilicone glass layer; The conductive structure includes a metal conductive layer.

8. The semiconductor structure according to claim 1, characterized in that, Along the depth direction away from the bottom of the trench, the width of the conductive structure gradually increases in a first direction; wherein, the first direction is perpendicular to the depth direction of the trench, and the first direction is the width direction of the trench.

9. The semiconductor structure according to claim 1, characterized in that, The target layer structure includes at least two dielectric layers stacked along the depth direction of the trench; the conductive structure fills the trench in each of the dielectric layers, and the corresponding portions of the conductive structure in different dielectric layers have different widths in a first direction; wherein, the first direction is perpendicular to the depth direction of the trench, and the first direction is the width direction of the trench.

10. The semiconductor structure according to claim 1, characterized in that, The conductive structure includes: A first metal layer conformally covers the bottom and sides of the trench; A second metal layer covers the first metal layer and fills the trench; The maximum surface roughness of the bottom surface of the first metal layer is greater than the maximum surface roughness of its side surface.

11. The semiconductor structure according to claim 10, characterized in that, The top surface of the second metal layer away from the bottom of the trench is lower than or higher than the top surface of the first metal layer away from the bottom of the trench.

12. A method for manufacturing a semiconductor structure, characterized in that, include: A target layer structure is prepared, the target layer structure comprising at least one dielectric layer; At least one trench is formed within the dielectric layer; A conductive structure that directly contacts the dielectric layer is formed in the trench; Wherein, the bottom surface and at least part of the side surface of the conductive structure are in contact with the same dielectric layer; the bottom surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D2, wherein the maximum surface roughness D1 > the maximum surface roughness D2. The bottom surface of the conductive structure includes: a first region, a second region, and a third region arranged equidistantly along a first direction; Wherein, the first direction is perpendicular to the depth direction of the trench, and the first direction is the width direction of the trench; the surface roughness of the second region and the third region is greater than the surface roughness of the first region.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that, The method of forming at least one trench in the dielectric layer further includes: forming a plurality of pits at the bottom of the trench; The method of forming a conductive structure in the trench that directly contacts the dielectric layer further includes: forming a plurality of protrusions at the bottom of the conductive structure that fill each of the pits.

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